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1; RUN: llc < %s -debug-entry-values -mtriple=arm64-apple-darwin | FileCheck %s2 3; Stackmap Header: no constants - 18 callsites4; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps5; CHECK-NEXT: __LLVM_StackMaps:6; Header7; CHECK-NEXT: .byte 38; CHECK-NEXT: .byte 09; CHECK-NEXT: .short 010; Num Functions11; CHECK-NEXT: .long 2212; Num LargeConstants13; CHECK-NEXT: .long 014; Num Callsites15; CHECK-NEXT: .long 2216 17; Functions and stack size18; CHECK-NEXT: .quad _test19; CHECK-NEXT: .quad 1620; CHECK-NEXT: .quad 121; CHECK-NEXT: .quad _property_access122; CHECK-NEXT: .quad 1623; CHECK-NEXT: .quad 124; CHECK-NEXT: .quad _property_access225; CHECK-NEXT: .quad 3226; CHECK-NEXT: .quad 127; CHECK-NEXT: .quad _property_access328; CHECK-NEXT: .quad 3229; CHECK-NEXT: .quad 130; CHECK-NEXT: .quad _anyreg_test131; CHECK-NEXT: .quad 1632; CHECK-NEXT: .quad 133; CHECK-NEXT: .quad _anyreg_test234; CHECK-NEXT: .quad 1635; CHECK-NEXT: .quad 136; CHECK-NEXT: .quad _patchpoint_spilldef37; CHECK-NEXT: .quad 11238; CHECK-NEXT: .quad 139; CHECK-NEXT: .quad _patchpoint_spillargs40; CHECK-NEXT: .quad 12841; CHECK-NEXT: .quad 142; CHECK-NEXT: .quad _generic_test_i143; CHECK-NEXT: .quad 1644; CHECK-NEXT: .quad 145; CHECK-NEXT: .quad _generic_test_i846; CHECK-NEXT: .quad 1647; CHECK-NEXT: .quad 148; CHECK-NEXT: .quad _generic_test_i1649; CHECK-NEXT: .quad 1650; CHECK-NEXT: .quad 151; CHECK-NEXT: .quad _generic_test_i2952; CHECK-NEXT: .quad 1653; CHECK-NEXT: .quad 154; CHECK-NEXT: .quad _generic_test_i3255; CHECK-NEXT: .quad 1656; CHECK-NEXT: .quad 157; CHECK-NEXT: .quad _generic_test_i6458; CHECK-NEXT: .quad 1659; CHECK-NEXT: .quad 160; CHECK-NEXT: .quad _generic_test_p061; CHECK-NEXT: .quad 1662; CHECK-NEXT: .quad 163; CHECK-NEXT: .quad _generic_test_f1664; CHECK-NEXT: .quad 1665; CHECK-NEXT: .quad 166; CHECK-NEXT: .quad _generic_test_f3267; CHECK-NEXT: .quad 1668; CHECK-NEXT: .quad 169; CHECK-NEXT: .quad _generic_test_f6470; CHECK-NEXT: .quad 1671; CHECK-NEXT: .quad 172; CHECK-NEXT: .quad _generic_test_v16i873; CHECK-NEXT: .quad 1674; CHECK-NEXT: .quad 175; CHECK-NEXT: .quad _generic_test_v4i3276; CHECK-NEXT: .quad 1677; CHECK-NEXT: .quad 178; CHECK-NEXT: .quad _generic_test_v4f3279; CHECK-NEXT: .quad 1680; CHECK-NEXT: .quad 181; CHECK-NEXT: .quad _generic_test_v2f6482; CHECK-NEXT: .quad 1683; CHECK-NEXT: .quad 184 85 86; test87; CHECK-LABEL: .long L{{.*}}-_test88; CHECK-NEXT: .short 089; 3 locations90; CHECK-NEXT: .short 391; Loc 0: Register92; CHECK-NEXT: .byte 193; CHECK-NEXT: .byte 094; CHECK-NEXT: .short 495; CHECK-NEXT: .short {{[0-9]+}}96; CHECK-NEXT: .short 097; CHECK-NEXT: .long 098; Loc 1: Register99; CHECK-NEXT: .byte 1100; CHECK-NEXT: .byte 0101; CHECK-NEXT: .short 4102; CHECK-NEXT: .short {{[0-9]+}}103; CHECK-NEXT: .short 0104; CHECK-NEXT: .long 0105; Loc 2: Constant 3106; CHECK-NEXT: .byte 4107; CHECK-NEXT: .byte 0108; CHECK-NEXT: .short 8109; CHECK-NEXT: .short 0110; CHECK-NEXT: .short 0111; CHECK-NEXT: .long 3112define i64 @test() nounwind ssp uwtable {113entry:114 call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, ptr null, i32 2, i32 1, i32 2, i64 3)115 ret i64 0116}117 118; property access 1 - %obj is an anyreg call argument and should therefore be in a register119; CHECK-LABEL: .long L{{.*}}-_property_access1120; CHECK-NEXT: .short 0121; 2 locations122; CHECK-NEXT: .short 2123; Loc 0: Register <-- this is the return register124; CHECK-NEXT: .byte 1125; CHECK-NEXT: .byte 0126; CHECK-NEXT: .short 8127; CHECK-NEXT: .short {{[0-9]+}}128; CHECK-NEXT: .short 0129; CHECK-NEXT: .long 0130; Loc 1: Register131; CHECK-NEXT: .byte 1132; CHECK-NEXT: .byte 0133; CHECK-NEXT: .short 8134; CHECK-NEXT: .short {{[0-9]+}}135; CHECK-NEXT: .short 0136; CHECK-NEXT: .long 0137define i64 @property_access1(ptr %obj) nounwind ssp uwtable {138entry:139 %f = inttoptr i64 281474417671919 to ptr140 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, ptr %f, i32 1, ptr %obj)141 ret i64 %ret142}143 144; property access 2 - %obj is an anyreg call argument and should therefore be in a register145; CHECK-LABEL: .long L{{.*}}-_property_access2146; CHECK-NEXT: .short 0147; 2 locations148; CHECK-NEXT: .short 2149; Loc 0: Register <-- this is the return register150; CHECK-NEXT: .byte 1151; CHECK-NEXT: .byte 0152; CHECK-NEXT: .short 8153; CHECK-NEXT: .short {{[0-9]+}}154; CHECK-NEXT: .short 0155; CHECK-NEXT: .long 0156; Loc 1: Register157; CHECK-NEXT: .byte 1158; CHECK-NEXT: .byte 0159; CHECK-NEXT: .short 8160; CHECK-NEXT: .short {{[0-9]+}}161; CHECK-NEXT: .short 0162; CHECK-NEXT: .long 0163define i64 @property_access2() nounwind ssp uwtable {164entry:165 %obj = alloca i64, align 8166 %f = inttoptr i64 281474417671919 to ptr167 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, ptr %f, i32 1, ptr %obj)168 ret i64 %ret169}170 171; property access 3 - %obj is a frame index172; CHECK-LABEL: .long L{{.*}}-_property_access3173; CHECK-NEXT: .short 0174; 2 locations175; CHECK-NEXT: .short 2176; Loc 0: Register <-- this is the return register177; CHECK-NEXT: .byte 1178; CHECK-NEXT: .byte 0179; CHECK-NEXT: .short 8180; CHECK-NEXT: .short {{[0-9]+}}181; CHECK-NEXT: .short 0182; CHECK-NEXT: .long 0183; Loc 1: Direct FP - 8184; CHECK-NEXT: .byte 2185; CHECK-NEXT: .byte 0186; CHECK-NEXT: .short 8187; CHECK-NEXT: .short 29188; CHECK-NEXT: .short 0189; CHECK-NEXT: .long -8190define i64 @property_access3() nounwind ssp uwtable {191entry:192 %obj = alloca i64, align 8193 %f = inttoptr i64 281474417671919 to ptr194 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, ptr %f, i32 0, ptr %obj)195 ret i64 %ret196}197 198; anyreg_test1199; CHECK-LABEL: .long L{{.*}}-_anyreg_test1200; CHECK-NEXT: .short 0201; 14 locations202; CHECK-NEXT: .short 14203; Loc 0: Register <-- this is the return register204; CHECK-NEXT: .byte 1205; CHECK-NEXT: .byte 0206; CHECK-NEXT: .short 8207; CHECK-NEXT: .short {{[0-9]+}}208; CHECK-NEXT: .short 0209; CHECK-NEXT: .long 0210; Loc 1: Register211; CHECK-NEXT: .byte 1212; CHECK-NEXT: .byte 0213; CHECK-NEXT: .short 8214; CHECK-NEXT: .short {{[0-9]+}}215; CHECK-NEXT: .short 0216; CHECK-NEXT: .long 0217; Loc 2: Register218; CHECK-NEXT: .byte 1219; CHECK-NEXT: .byte 0220; CHECK-NEXT: .short 8221; CHECK-NEXT: .short {{[0-9]+}}222; CHECK-NEXT: .short 0223; CHECK-NEXT: .long 0224; Loc 3: Register225; CHECK-NEXT: .byte 1226; CHECK-NEXT: .byte 0227; CHECK-NEXT: .short 8228; CHECK-NEXT: .short {{[0-9]+}}229; CHECK-NEXT: .short 0230; CHECK-NEXT: .long 0231; Loc 4: Register232; CHECK-NEXT: .byte 1233; CHECK-NEXT: .byte 0234; CHECK-NEXT: .short 8235; CHECK-NEXT: .short {{[0-9]+}}236; CHECK-NEXT: .short 0237; CHECK-NEXT: .long 0238; Loc 5: Register239; CHECK-NEXT: .byte 1240; CHECK-NEXT: .byte 0241; CHECK-NEXT: .short 8242; CHECK-NEXT: .short {{[0-9]+}}243; CHECK-NEXT: .short 0244; CHECK-NEXT: .long 0245; Loc 6: Register246; CHECK-NEXT: .byte 1247; CHECK-NEXT: .byte 0248; CHECK-NEXT: .short 8249; CHECK-NEXT: .short {{[0-9]+}}250; CHECK-NEXT: .short 0251; CHECK-NEXT: .long 0252; Loc 7: Register253; CHECK-NEXT: .byte 1254; CHECK-NEXT: .byte 0255; CHECK-NEXT: .short 8256; CHECK-NEXT: .short {{[0-9]+}}257; CHECK-NEXT: .short 0258; CHECK-NEXT: .long 0259; Loc 8: Register260; CHECK-NEXT: .byte 1261; CHECK-NEXT: .byte 0262; CHECK-NEXT: .short 8263; CHECK-NEXT: .short {{[0-9]+}}264; CHECK-NEXT: .short 0265; CHECK-NEXT: .long 0266; Loc 9: Register267; CHECK-NEXT: .byte 1268; CHECK-NEXT: .byte 0269; CHECK-NEXT: .short 8270; CHECK-NEXT: .short {{[0-9]+}}271; CHECK-NEXT: .short 0272; CHECK-NEXT: .long 0273; Loc 10: Register274; CHECK-NEXT: .byte 1275; CHECK-NEXT: .byte 0276; CHECK-NEXT: .short 8277; CHECK-NEXT: .short {{[0-9]+}}278; CHECK-NEXT: .short 0279; CHECK-NEXT: .long 0280; Loc 11: Register281; CHECK-NEXT: .byte 1282; CHECK-NEXT: .byte 0283; CHECK-NEXT: .short 8284; CHECK-NEXT: .short {{[0-9]+}}285; CHECK-NEXT: .short 0286; CHECK-NEXT: .long 0287; Loc 12: Register288; CHECK-NEXT: .byte 1289; CHECK-NEXT: .byte 0290; CHECK-NEXT: .short 8291; CHECK-NEXT: .short {{[0-9]+}}292; CHECK-NEXT: .short 0293; CHECK-NEXT: .long 0294; Loc 13: Register295; CHECK-NEXT: .byte 1296; CHECK-NEXT: .byte 0297; CHECK-NEXT: .short 8298; CHECK-NEXT: .short {{[0-9]+}}299; CHECK-NEXT: .short 0300; CHECK-NEXT: .long 0301define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {302entry:303 %f = inttoptr i64 281474417671919 to ptr304 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, ptr %f, i32 13, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)305 ret i64 %ret306}307 308; anyreg_test2309; CHECK-LABEL: .long L{{.*}}-_anyreg_test2310; CHECK-NEXT: .short 0311; 14 locations312; CHECK-NEXT: .short 14313; Loc 0: Register <-- this is the return register314; CHECK-NEXT: .byte 1315; CHECK-NEXT: .byte 0316; CHECK-NEXT: .short 8317; CHECK-NEXT: .short {{[0-9]+}}318; CHECK-NEXT: .short 0319; CHECK-NEXT: .long 0320; Loc 1: Register321; CHECK-NEXT: .byte 1322; CHECK-NEXT: .byte 0323; CHECK-NEXT: .short 8324; CHECK-NEXT: .short {{[0-9]+}}325; CHECK-NEXT: .short 0326; CHECK-NEXT: .long 0327; Loc 2: Register328; CHECK-NEXT: .byte 1329; CHECK-NEXT: .byte 0330; CHECK-NEXT: .short 8331; CHECK-NEXT: .short {{[0-9]+}}332; CHECK-NEXT: .short 0333; CHECK-NEXT: .long 0334; Loc 3: Register335; CHECK-NEXT: .byte 1336; CHECK-NEXT: .byte 0337; CHECK-NEXT: .short 8338; CHECK-NEXT: .short {{[0-9]+}}339; CHECK-NEXT: .short 0340; CHECK-NEXT: .long 0341; Loc 4: Register342; CHECK-NEXT: .byte 1343; CHECK-NEXT: .byte 0344; CHECK-NEXT: .short 8345; CHECK-NEXT: .short {{[0-9]+}}346; CHECK-NEXT: .short 0347; CHECK-NEXT: .long 0348; Loc 5: Register349; CHECK-NEXT: .byte 1350; CHECK-NEXT: .byte 0351; CHECK-NEXT: .short 8352; CHECK-NEXT: .short {{[0-9]+}}353; CHECK-NEXT: .short 0354; CHECK-NEXT: .long 0355; Loc 6: Register356; CHECK-NEXT: .byte 1357; CHECK-NEXT: .byte 0358; CHECK-NEXT: .short 8359; CHECK-NEXT: .short {{[0-9]+}}360; CHECK-NEXT: .short 0361; CHECK-NEXT: .long 0362; Loc 7: Register363; CHECK-NEXT: .byte 1364; CHECK-NEXT: .byte 0365; CHECK-NEXT: .short 8366; CHECK-NEXT: .short {{[0-9]+}}367; CHECK-NEXT: .short 0368; CHECK-NEXT: .long 0369; Loc 8: Register370; CHECK-NEXT: .byte 1371; CHECK-NEXT: .byte 0372; CHECK-NEXT: .short 8373; CHECK-NEXT: .short {{[0-9]+}}374; CHECK-NEXT: .short 0375; CHECK-NEXT: .long 0376; Loc 9: Register377; CHECK-NEXT: .byte 1378; CHECK-NEXT: .byte 0379; CHECK-NEXT: .short 8380; CHECK-NEXT: .short {{[0-9]+}}381; CHECK-NEXT: .short 0382; CHECK-NEXT: .long 0383; Loc 10: Register384; CHECK-NEXT: .byte 1385; CHECK-NEXT: .byte 0386; CHECK-NEXT: .short 8387; CHECK-NEXT: .short {{[0-9]+}}388; CHECK-NEXT: .short 0389; CHECK-NEXT: .long 0390; Loc 11: Register391; CHECK-NEXT: .byte 1392; CHECK-NEXT: .byte 0393; CHECK-NEXT: .short 8394; CHECK-NEXT: .short {{[0-9]+}}395; CHECK-NEXT: .short 0396; CHECK-NEXT: .long 0397; Loc 12: Register398; CHECK-NEXT: .byte 1399; CHECK-NEXT: .byte 0400; CHECK-NEXT: .short 8401; CHECK-NEXT: .short {{[0-9]+}}402; CHECK-NEXT: .short 0403; CHECK-NEXT: .long 0404; Loc 13: Register405; CHECK-NEXT: .byte 1406; CHECK-NEXT: .byte 0407; CHECK-NEXT: .short 8408; CHECK-NEXT: .short {{[0-9]+}}409; CHECK-NEXT: .short 0410; CHECK-NEXT: .long 0411define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {412entry:413 %f = inttoptr i64 281474417671919 to ptr414 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)415 ret i64 %ret416}417 418; Test spilling the return value of an anyregcc call.419;420; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"421;422; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef423; CHECK-NEXT: .short 0424; CHECK-NEXT: .short 3425; Loc 0: Register (some register that will be spilled to the stack)426; CHECK-NEXT: .byte 1427; CHECK-NEXT: .byte 0428; CHECK-NEXT: .short 8429; CHECK-NEXT: .short {{[0-9]+}}430; CHECK-NEXT: .short 0431; CHECK-NEXT: .long 0432; Loc 1: Register433; CHECK-NEXT: .byte 1434; CHECK-NEXT: .byte 0435; CHECK-NEXT: .short 8436; CHECK-NEXT: .short {{[0-9]+}}437; CHECK-NEXT: .short 0438; CHECK-NEXT: .long 0439; Loc 1: Register440; CHECK-NEXT: .byte 1441; CHECK-NEXT: .byte 0442; CHECK-NEXT: .short 8443; CHECK-NEXT: .short {{[0-9]+}}444; CHECK-NEXT: .short 0445; CHECK-NEXT: .long 0446define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {447entry:448 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)449 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind450 ret i64 %result451}452 453; Test spilling the arguments of an anyregcc call.454;455; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled456;457; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs458; CHECK-NEXT: .short 0459; CHECK-NEXT: .short 5460; Loc 0: Return a register461; CHECK-NEXT: .byte 1462; CHECK-NEXT: .byte 0463; CHECK-NEXT: .short 8464; CHECK-NEXT: .short {{[0-9]+}}465; CHECK-NEXT: .short 0466; CHECK-NEXT: .long 0467; Loc 1: Arg0 in a Register468; CHECK-NEXT: .byte 1469; CHECK-NEXT: .byte 0470; CHECK-NEXT: .short 8471; CHECK-NEXT: .short {{[0-9]+}}472; CHECK-NEXT: .short 0473; CHECK-NEXT: .long 0474; Loc 2: Arg1 in a Register475; CHECK-NEXT: .byte 1476; CHECK-NEXT: .byte 0477; CHECK-NEXT: .short 8478; CHECK-NEXT: .short {{[0-9]+}}479; CHECK-NEXT: .short 0480; CHECK-NEXT: .long 0481; Loc 3: Arg2 spilled to FP -96482; CHECK-NEXT: .byte 3483; CHECK-NEXT: .byte 0484; CHECK-NEXT: .short 8485; CHECK-NEXT: .short 29486; CHECK-NEXT: .short 0487; CHECK-NEXT: .long -96488; Loc 4: Arg3 spilled to FP - 88489; CHECK-NEXT: .byte 3490; CHECK-NEXT: .byte 0491; CHECK-NEXT: .short 8492; CHECK-NEXT: .short 29493; CHECK-NEXT: .short 0494; CHECK-NEXT: .long -88495define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {496entry:497 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind498 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)499 ret i64 %result500}501 502; generic_test_i1503; CHECK-LABEL: .long L{{.*}}-_generic_test_i1504; CHECK-NEXT: .short 0505; 1 location506; CHECK-NEXT: .short 1507; Loc 0: Register <-- this is the return register508; CHECK-NEXT: .byte 1509; CHECK-NEXT: .byte 0510; CHECK-NEXT: .short 4511; CHECK-NEXT: .short {{[0-9]+}}512; CHECK-NEXT: .short 0513; CHECK-NEXT: .long 0514define i1 @generic_test_i1() nounwind ssp uwtable {515entry:516 %ret = call anyregcc i1 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i1(i64 14, i32 20, ptr null, i32 0)517 ret i1 %ret518}519 520; generic_test_i8521; CHECK-LABEL: .long L{{.*}}-_generic_test_i8522; CHECK-NEXT: .short 0523; 1 location524; CHECK-NEXT: .short 1525; Loc 0: Register <-- this is the return register526; CHECK-NEXT: .byte 1527; CHECK-NEXT: .byte 0528; CHECK-NEXT: .short 4529; CHECK-NEXT: .short {{[0-9]+}}530; CHECK-NEXT: .short 0531; CHECK-NEXT: .long 0532define i8 @generic_test_i8() nounwind ssp uwtable {533entry:534 %ret = call anyregcc i8 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i8(i64 14, i32 20, ptr null, i32 0)535 ret i8 %ret536}537 538; generic_test_i16539; CHECK-LABEL: .long L{{.*}}-_generic_test_i16540; CHECK-NEXT: .short 0541; 1 location542; CHECK-NEXT: .short 1543; Loc 0: Register <-- this is the return register544; CHECK-NEXT: .byte 1545; CHECK-NEXT: .byte 0546; CHECK-NEXT: .short 4547; CHECK-NEXT: .short {{[0-9]+}}548; CHECK-NEXT: .short 0549; CHECK-NEXT: .long 0550define i16 @generic_test_i16() nounwind ssp uwtable {551entry:552 %ret = call anyregcc i16 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i16(i64 14, i32 20, ptr null, i32 0)553 ret i16 %ret554}555 556; generic_test_i29557; CHECK-LABEL: .long L{{.*}}-_generic_test_i29558; CHECK-NEXT: .short 0559; 1 location560; CHECK-NEXT: .short 1561; Loc 0: Register <-- this is the return register562; CHECK-NEXT: .byte 1563; CHECK-NEXT: .byte 0564; CHECK-NEXT: .short 4565; CHECK-NEXT: .short {{[0-9]+}}566; CHECK-NEXT: .short 0567; CHECK-NEXT: .long 0568define i29 @generic_test_i29() nounwind ssp uwtable {569entry:570 %ret = call anyregcc i29 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i29(i64 14, i32 20, ptr null, i32 0)571 ret i29 %ret572}573 574; generic_test_i32575; CHECK-LABEL: .long L{{.*}}-_generic_test_i32576; CHECK-NEXT: .short 0577; 1 location578; CHECK-NEXT: .short 1579; Loc 0: Register <-- this is the return register580; CHECK-NEXT: .byte 1581; CHECK-NEXT: .byte 0582; CHECK-NEXT: .short 4583; CHECK-NEXT: .short {{[0-9]+}}584; CHECK-NEXT: .short 0585; CHECK-NEXT: .long 0586define i32 @generic_test_i32() nounwind ssp uwtable {587entry:588 %ret = call anyregcc i32 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i32(i64 14, i32 20, ptr null, i32 0)589 ret i32 %ret590}591 592; generic_test_i64593; CHECK-LABEL: .long L{{.*}}-_generic_test_i64594; CHECK-NEXT: .short 0595; 1 location596; CHECK-NEXT: .short 1597; Loc 0: Register <-- this is the return register598; CHECK-NEXT: .byte 1599; CHECK-NEXT: .byte 0600; CHECK-NEXT: .short 8601; CHECK-NEXT: .short {{[0-9]+}}602; CHECK-NEXT: .short 0603; CHECK-NEXT: .long 0604define i64 @generic_test_i64() nounwind ssp uwtable {605entry:606 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 14, i32 20, ptr null, i32 0)607 ret i64 %ret608}609 610; generic_test_p0611; CHECK-LABEL: .long L{{.*}}-_generic_test_p0612; CHECK-NEXT: .short 0613; 1 location614; CHECK-NEXT: .short 1615; Loc 0: Register <-- this is the return register616; CHECK-NEXT: .byte 1617; CHECK-NEXT: .byte 0618; CHECK-NEXT: .short 8619; CHECK-NEXT: .short {{[0-9]+}}620; CHECK-NEXT: .short 0621; CHECK-NEXT: .long 0622define ptr @generic_test_p0() nounwind ssp uwtable {623entry:624 %ret = call anyregcc ptr (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.p0(i64 14, i32 20, ptr null, i32 0)625 ret ptr %ret626}627 628; generic_test_f16629; CHECK-LABEL: .long L{{.*}}-_generic_test_f16630; CHECK-NEXT: .short 0631; 1 location632; CHECK-NEXT: .short 1633; Loc 0: Register <-- this is the return register634; CHECK-NEXT: .byte 1635; CHECK-NEXT: .byte 0636; CHECK-NEXT: .short 2637; CHECK-NEXT: .short {{[0-9]+}}638; CHECK-NEXT: .short 0639; CHECK-NEXT: .long 0640define half @generic_test_f16() nounwind ssp uwtable {641entry:642 %ret = call anyregcc half (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.f16(i64 14, i32 20, ptr null, i32 0)643 ret half %ret644}645 646; generic_test_f32647; CHECK-LABEL: .long L{{.*}}-_generic_test_f32648; CHECK-NEXT: .short 0649; 1 location650; CHECK-NEXT: .short 1651; Loc 0: Register <-- this is the return register652; CHECK-NEXT: .byte 1653; CHECK-NEXT: .byte 0654; CHECK-NEXT: .short 4655; CHECK-NEXT: .short {{[0-9]+}}656; CHECK-NEXT: .short 0657; CHECK-NEXT: .long 0658define float @generic_test_f32() nounwind ssp uwtable {659entry:660 %ret = call anyregcc float (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.f32(i64 14, i32 20, ptr null, i32 0)661 ret float %ret662}663 664; generic_test_f64665; CHECK-LABEL: .long L{{.*}}-_generic_test_f64666; CHECK-NEXT: .short 0667; 1 location668; CHECK-NEXT: .short 1669; Loc 0: Register <-- this is the return register670; CHECK-NEXT: .byte 1671; CHECK-NEXT: .byte 0672; CHECK-NEXT: .short 8673; CHECK-NEXT: .short {{[0-9]+}}674; CHECK-NEXT: .short 0675; CHECK-NEXT: .long 0676define double @generic_test_f64() nounwind ssp uwtable {677entry:678 %ret = call anyregcc double (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.f64(i64 14, i32 20, ptr null, i32 0)679 ret double %ret680}681 682; generic_test_v16i8683; CHECK-LABEL: .long L{{.*}}-_generic_test_v16i8684; CHECK-NEXT: .short 0685; 1 location686; CHECK-NEXT: .short 1687; Loc 0: Register <-- this is the return register688; CHECK-NEXT: .byte 1689; CHECK-NEXT: .byte 0690; CHECK-NEXT: .short 16691; CHECK-NEXT: .short {{[0-9]+}}692; CHECK-NEXT: .short 0693; CHECK-NEXT: .long 0694define <16 x i8> @generic_test_v16i8() nounwind ssp uwtable {695entry:696 %ret = call anyregcc <16 x i8> (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.v16i8(i64 14, i32 20, ptr null, i32 0)697 ret <16 x i8> %ret698}699 700; generic_test_v4i32701; CHECK-LABEL: .long L{{.*}}-_generic_test_v4i32702; CHECK-NEXT: .short 0703; 1 location704; CHECK-NEXT: .short 1705; Loc 0: Register <-- this is the return register706; CHECK-NEXT: .byte 1707; CHECK-NEXT: .byte 0708; CHECK-NEXT: .short 16709; CHECK-NEXT: .short {{[0-9]+}}710; CHECK-NEXT: .short 0711; CHECK-NEXT: .long 0712define <4 x i32> @generic_test_v4i32() nounwind ssp uwtable {713entry:714 %ret = call anyregcc <4 x i32> (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.v4i32(i64 14, i32 20, ptr null, i32 0)715 ret <4 x i32> %ret716}717 718; generic_test_v4f32719; CHECK-LABEL: .long L{{.*}}-_generic_test_v4f32720; CHECK-NEXT: .short 0721; 1 location722; CHECK-NEXT: .short 1723; Loc 0: Register <-- this is the return register724; CHECK-NEXT: .byte 1725; CHECK-NEXT: .byte 0726; CHECK-NEXT: .short 16727; CHECK-NEXT: .short {{[0-9]+}}728; CHECK-NEXT: .short 0729; CHECK-NEXT: .long 0730define <4 x float> @generic_test_v4f32() nounwind ssp uwtable {731entry:732 %ret = call anyregcc <4 x float> (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.v4f32(i64 14, i32 20, ptr null, i32 0)733 ret <4 x float> %ret734}735 736; generic_test_v2f64737; CHECK-LABEL: .long L{{.*}}-_generic_test_v2f64738; CHECK-NEXT: .short 0739; 1 location740; CHECK-NEXT: .short 1741; Loc 0: Register <-- this is the return register742; CHECK-NEXT: .byte 1743; CHECK-NEXT: .byte 0744; CHECK-NEXT: .short 16745; CHECK-NEXT: .short {{[0-9]+}}746; CHECK-NEXT: .short 0747; CHECK-NEXT: .long 0748define <2 x double> @generic_test_v2f64() nounwind ssp uwtable {749entry:750 %ret = call anyregcc <2 x double> (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.v2f64(i64 14, i32 20, ptr null, i32 0)751 ret <2 x double> %ret752}753 754declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)755declare i32 @llvm.experimental.patchpoint.i32(i64, i32, ptr, i32, ...)756declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)757declare ptr @llvm.experimental.patchpoint.p0(i64, i32, ptr, i32, ...)758declare half @llvm.experimental.patchpoint.f16(i64, i32, ptr, i32, ...)759declare float @llvm.experimental.patchpoint.f32(i64, i32, ptr, i32, ...)760declare double @llvm.experimental.patchpoint.f64(i64, i32, ptr, i32, ...)761declare <16 x i8> @llvm.experimental.patchpoint.v16i8(i64, i32, ptr, i32, ...)762declare <4 x i32> @llvm.experimental.patchpoint.v4i32(i64, i32, ptr, i32, ...)763declare <4 x float> @llvm.experimental.patchpoint.v4f32(i64, i32, ptr, i32, ...)764declare <2 x double> @llvm.experimental.patchpoint.v2f64(i64, i32, ptr, i32, ...)765