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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck %s3 4define i32 @qadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {5; CHECK-LABEL: qadds:6; CHECK: // %bb.0:7; CHECK-NEXT: sqadd s0, s0, s18; CHECK-NEXT: fmov w0, s09; CHECK-NEXT: ret10 %vecext = extractelement <4 x i32> %b, i32 011 %vecext1 = extractelement <4 x i32> %c, i32 012 %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind13 ret i32 %vqadd.i14}15 16define i64 @qaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {17; CHECK-LABEL: qaddd:18; CHECK: // %bb.0:19; CHECK-NEXT: sqadd d0, d0, d120; CHECK-NEXT: fmov x0, d021; CHECK-NEXT: ret22 %vecext = extractelement <2 x i64> %b, i32 023 %vecext1 = extractelement <2 x i64> %c, i32 024 %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind25 ret i64 %vqadd.i26}27 28define i32 @uqadds(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {29; CHECK-LABEL: uqadds:30; CHECK: // %bb.0:31; CHECK-NEXT: uqadd s0, s0, s132; CHECK-NEXT: fmov w0, s033; CHECK-NEXT: ret34 %vecext = extractelement <4 x i32> %b, i32 035 %vecext1 = extractelement <4 x i32> %c, i32 036 %vqadd.i = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind37 ret i32 %vqadd.i38}39 40define i64 @uqaddd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {41; CHECK-LABEL: uqaddd:42; CHECK: // %bb.0:43; CHECK-NEXT: uqadd d0, d0, d144; CHECK-NEXT: fmov x0, d045; CHECK-NEXT: ret46 %vecext = extractelement <2 x i64> %b, i32 047 %vecext1 = extractelement <2 x i64> %c, i32 048 %vqadd.i = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind49 ret i64 %vqadd.i50}51 52declare i64 @llvm.aarch64.neon.uqadd.i64(i64, i64) nounwind readnone53declare i32 @llvm.aarch64.neon.uqadd.i32(i32, i32) nounwind readnone54declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone55declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone56 57define i32 @qsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {58; CHECK-LABEL: qsubs:59; CHECK: // %bb.0:60; CHECK-NEXT: sqsub s0, s0, s161; CHECK-NEXT: fmov w0, s062; CHECK-NEXT: ret63 %vecext = extractelement <4 x i32> %b, i32 064 %vecext1 = extractelement <4 x i32> %c, i32 065 %vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind66 ret i32 %vqsub.i67}68 69define i64 @qsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {70; CHECK-LABEL: qsubd:71; CHECK: // %bb.0:72; CHECK-NEXT: sqsub d0, d0, d173; CHECK-NEXT: fmov x0, d074; CHECK-NEXT: ret75 %vecext = extractelement <2 x i64> %b, i32 076 %vecext1 = extractelement <2 x i64> %c, i32 077 %vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind78 ret i64 %vqsub.i79}80 81define i32 @uqsubs(<4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {82; CHECK-LABEL: uqsubs:83; CHECK: // %bb.0:84; CHECK-NEXT: uqsub s0, s0, s185; CHECK-NEXT: fmov w0, s086; CHECK-NEXT: ret87 %vecext = extractelement <4 x i32> %b, i32 088 %vecext1 = extractelement <4 x i32> %c, i32 089 %vqsub.i = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind90 ret i32 %vqsub.i91}92 93define i64 @uqsubd(<2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {94; CHECK-LABEL: uqsubd:95; CHECK: // %bb.0:96; CHECK-NEXT: uqsub d0, d0, d197; CHECK-NEXT: fmov x0, d098; CHECK-NEXT: ret99 %vecext = extractelement <2 x i64> %b, i32 0100 %vecext1 = extractelement <2 x i64> %c, i32 0101 %vqsub.i = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind102 ret i64 %vqsub.i103}104 105declare i64 @llvm.aarch64.neon.uqsub.i64(i64, i64) nounwind readnone106declare i32 @llvm.aarch64.neon.uqsub.i32(i32, i32) nounwind readnone107declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64) nounwind readnone108declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) nounwind readnone109 110define i32 @qabss(<4 x i32> %b, <4 x i32> %c) nounwind readnone {111; CHECK-LABEL: qabss:112; CHECK: // %bb.0:113; CHECK-NEXT: sqabs s0, s0114; CHECK-NEXT: fmov w0, s0115; CHECK-NEXT: ret116 %vecext = extractelement <4 x i32> %b, i32 0117 %vqabs.i = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %vecext) nounwind118 ret i32 %vqabs.i119}120 121define i64 @qabsd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {122; CHECK-LABEL: qabsd:123; CHECK: // %bb.0:124; CHECK-NEXT: sqabs d0, d0125; CHECK-NEXT: fmov x0, d0126; CHECK-NEXT: ret127 %vecext = extractelement <2 x i64> %b, i32 0128 %vqabs.i = tail call i64 @llvm.aarch64.neon.sqabs.i64(i64 %vecext) nounwind129 ret i64 %vqabs.i130}131 132define i32 @qnegs(<4 x i32> %b, <4 x i32> %c) nounwind readnone {133; CHECK-LABEL: qnegs:134; CHECK: // %bb.0:135; CHECK-NEXT: sqneg s0, s0136; CHECK-NEXT: fmov w0, s0137; CHECK-NEXT: ret138 %vecext = extractelement <4 x i32> %b, i32 0139 %vqneg.i = tail call i32 @llvm.aarch64.neon.sqneg.i32(i32 %vecext) nounwind140 ret i32 %vqneg.i141}142 143define i64 @qnegd(<2 x i64> %b, <2 x i64> %c) nounwind readnone {144; CHECK-LABEL: qnegd:145; CHECK: // %bb.0:146; CHECK-NEXT: sqneg d0, d0147; CHECK-NEXT: fmov x0, d0148; CHECK-NEXT: ret149 %vecext = extractelement <2 x i64> %b, i32 0150 %vqneg.i = tail call i64 @llvm.aarch64.neon.sqneg.i64(i64 %vecext) nounwind151 ret i64 %vqneg.i152}153 154declare i64 @llvm.aarch64.neon.sqneg.i64(i64) nounwind readnone155declare i32 @llvm.aarch64.neon.sqneg.i32(i32) nounwind readnone156declare i64 @llvm.aarch64.neon.sqabs.i64(i64) nounwind readnone157declare i32 @llvm.aarch64.neon.sqabs.i32(i32) nounwind readnone158 159 160define i32 @vqmovund(<2 x i64> %b) nounwind readnone {161; CHECK-LABEL: vqmovund:162; CHECK: // %bb.0:163; CHECK-NEXT: sqxtun s0, d0164; CHECK-NEXT: fmov w0, s0165; CHECK-NEXT: ret166 %vecext = extractelement <2 x i64> %b, i32 0167 %vqmovun.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64 %vecext) nounwind168 ret i32 %vqmovun.i169}170 171define i32 @vqmovnd_s(<2 x i64> %b) nounwind readnone {172; CHECK-LABEL: vqmovnd_s:173; CHECK: // %bb.0:174; CHECK-NEXT: sqxtn s0, d0175; CHECK-NEXT: fmov w0, s0176; CHECK-NEXT: ret177 %vecext = extractelement <2 x i64> %b, i32 0178 %vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %vecext) nounwind179 ret i32 %vqmovn.i180}181 182define i32 @vqmovnd_u(<2 x i64> %b) nounwind readnone {183; CHECK-LABEL: vqmovnd_u:184; CHECK: // %bb.0:185; CHECK-NEXT: uqxtn s0, d0186; CHECK-NEXT: fmov w0, s0187; CHECK-NEXT: ret188 %vecext = extractelement <2 x i64> %b, i32 0189 %vqmovn.i = tail call i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64 %vecext) nounwind190 ret i32 %vqmovn.i191}192 193define i32 @uqxtn_ext(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 %c, float %d, <2 x i64> %e) {194; CHECK-LABEL: uqxtn_ext:195; CHECK: // %bb.0: // %entry196; CHECK-NEXT: mov d0, v3.d[1]197; CHECK-NEXT: uqxtn s0, d0198; CHECK-NEXT: fmov w0, s0199; CHECK-NEXT: ret200entry:201 %e1 = extractelement <2 x i64> %e, i64 1202 %r = tail call i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64 %e1)203 ret i32 %r204}205 206define <4 x i32> @sqxtn_ins(<4 x i32> noundef %a, i64 %c) {207; CHECK-LABEL: sqxtn_ins:208; CHECK: // %bb.0: // %entry209; CHECK-NEXT: fmov d1, x0210; CHECK-NEXT: sqxtn s1, d1211; CHECK-NEXT: mov v0.s[3], v1.s[0]212; CHECK-NEXT: ret213entry:214 %vqmovnd_s64.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %c)215 %vecins = insertelement <4 x i32> %a, i32 %vqmovnd_s64.i, i64 3216 ret <4 x i32> %vecins217}218 219define <4 x i32> @sqxtun_insext(<4 x i32> noundef %a, <2 x i64> %e) {220; CHECK-LABEL: sqxtun_insext:221; CHECK: // %bb.0: // %entry222; CHECK-NEXT: mov d1, v1.d[1]223; CHECK-NEXT: sqxtun s1, d1224; CHECK-NEXT: mov v0.s[3], v1.s[0]225; CHECK-NEXT: ret226entry:227 %c = extractelement <2 x i64> %e, i64 1228 %vqmovnd_s64.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64 %c)229 %vecins = insertelement <4 x i32> %a, i32 %vqmovnd_s64.i, i64 3230 ret <4 x i32> %vecins231}232 233define <4 x i32> @saddluse(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 %c, float %d, <2 x i64> %e) {234; CHECK-LABEL: saddluse:235; CHECK: // %bb.0: // %entry236; CHECK-NEXT: saddlv d1, v1.4s237; CHECK-NEXT: sqxtn s1, d1238; CHECK-NEXT: mov v0.s[1], v1.s[0]239; CHECK-NEXT: ret240entry:241 %vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %b)242 %vqmovnd_s64.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %vaddlvq_s32.i)243 %vecins = insertelement <4 x i32> %a, i32 %vqmovnd_s64.i, i64 1244 ret <4 x i32> %vecins245}246 247declare i32 @llvm.aarch64.neon.scalar.uqxtn.i32.i64(i64) nounwind readnone248declare i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64) nounwind readnone249declare i32 @llvm.aarch64.neon.scalar.sqxtun.i32.i64(i64) nounwind readnone250declare i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32>)251