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1; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false | FileCheck %s2 3define i32 @t1(i32 %a, i32 %b) nounwind readnone ssp {4entry:5; CHECK-LABEL: t1:6; CHECK: add w0, w1, w07; CHECK: ret8 %add = add i32 %b, %a9 ret i32 %add10}11 12define i32 @t2(i32 %a, i32 %b) nounwind readnone ssp {13entry:14; CHECK-LABEL: t2:15; CHECK: udiv w0, w0, w116; CHECK: ret17 %udiv = udiv i32 %a, %b18 ret i32 %udiv19}20 21define i64 @t3(i64 %a, i64 %b) nounwind readnone ssp {22entry:23; CHECK-LABEL: t3:24; CHECK: udiv x0, x0, x125; CHECK: ret26 %udiv = udiv i64 %a, %b27 ret i64 %udiv28}29 30define i32 @t4(i32 %a, i32 %b) nounwind readnone ssp {31entry:32; CHECK-LABEL: t4:33; CHECK: sdiv w0, w0, w134; CHECK: ret35 %sdiv = sdiv i32 %a, %b36 ret i32 %sdiv37}38 39define i64 @t5(i64 %a, i64 %b) nounwind readnone ssp {40entry:41; CHECK-LABEL: t5:42; CHECK: sdiv x0, x0, x143; CHECK: ret44 %sdiv = sdiv i64 %a, %b45 ret i64 %sdiv46}47 48define i32 @t6(i32 %a, i32 %b) nounwind readnone ssp {49entry:50; CHECK-LABEL: t6:51; CHECK: lsl w0, w0, w152; CHECK: ret53 %shl = shl i32 %a, %b54 ret i32 %shl55}56 57define i64 @t7(i64 %a, i64 %b) nounwind readnone ssp {58entry:59; CHECK-LABEL: t7:60; CHECK: lsl x0, x0, x161; CHECK: ret62 %shl = shl i64 %a, %b63 ret i64 %shl64}65 66define i32 @t8(i32 %a, i32 %b) nounwind readnone ssp {67entry:68; CHECK-LABEL: t8:69; CHECK: lsr w0, w0, w170; CHECK: ret71 %lshr = lshr i32 %a, %b72 ret i32 %lshr73}74 75define i64 @t9(i64 %a, i64 %b) nounwind readnone ssp {76entry:77; CHECK-LABEL: t9:78; CHECK: lsr x0, x0, x179; CHECK: ret80 %lshr = lshr i64 %a, %b81 ret i64 %lshr82}83 84define i32 @t10(i32 %a, i32 %b) nounwind readnone ssp {85entry:86; CHECK-LABEL: t10:87; CHECK: asr w0, w0, w188; CHECK: ret89 %ashr = ashr i32 %a, %b90 ret i32 %ashr91}92 93define i64 @t11(i64 %a, i64 %b) nounwind readnone ssp {94entry:95; CHECK-LABEL: t11:96; CHECK: asr x0, x0, x197; CHECK: ret98 %ashr = ashr i64 %a, %b99 ret i64 %ashr100}101 102define i32 @t12(i16 %a, i32 %x) nounwind ssp {103entry:104; CHECK-LABEL: t12:105; CHECK: add w0, w1, w0, sxth106; CHECK: ret107 %c = sext i16 %a to i32108 %e = add i32 %x, %c109 ret i32 %e110}111 112define i32 @t13(i16 %a, i32 %x) nounwind ssp {113entry:114; CHECK-LABEL: t13:115; CHECK: add w0, w1, w0, sxth #2116; CHECK: ret117 %c = sext i16 %a to i32118 %d = shl i32 %c, 2119 %e = add i32 %x, %d120 ret i32 %e121}122 123define i64 @t14(i16 %a, i64 %x) nounwind ssp {124entry:125; CHECK-LABEL: t14:126; CHECK: add x0, x1, w0, uxth #3127; CHECK: ret128 %c = zext i16 %a to i64129 %d = shl i64 %c, 3130 %e = add i64 %x, %d131 ret i64 %e132}133 134; rdar://9160598135define i64 @t15(i64 %a, i64 %x) nounwind ssp {136entry:137; CHECK-LABEL: t15:138; CHECK: add x0, x1, w0, uxtw139; CHECK: ret140 %b = and i64 %a, 4294967295141 %c = add i64 %x, %b142 ret i64 %c143}144 145define i64 @t16(i64 %x) nounwind ssp {146entry:147; CHECK-LABEL: t16:148; CHECK: lsl x0, x0, #1149; CHECK: ret150 %a = shl i64 %x, 1151 ret i64 %a152}153 154; rdar://9166974155define i64 @t17(i16 %a, i64 %x) nounwind ssp {156entry:157; CHECK-LABEL: t17:158; CHECK: sxth [[REG:x[0-9]+]], w0159; CHECK: neg x0, [[REG]], lsl #32160; CHECK: ret161 %tmp16 = sext i16 %a to i64162 %tmp17 = mul i64 %tmp16, -4294967296163 ret i64 %tmp17164}165 166define i32 @t18(i32 %a, i32 %b) nounwind readnone ssp {167entry:168; CHECK-LABEL: t18:169; CHECK: sdiv w0, w0, w1170; CHECK: ret171 %sdiv = call i32 @llvm.aarch64.sdiv.i32(i32 %a, i32 %b)172 ret i32 %sdiv173}174 175define i64 @t19(i64 %a, i64 %b) nounwind readnone ssp {176entry:177; CHECK-LABEL: t19:178; CHECK: sdiv x0, x0, x1179; CHECK: ret180 %sdiv = call i64 @llvm.aarch64.sdiv.i64(i64 %a, i64 %b)181 ret i64 %sdiv182}183 184define i32 @t20(i32 %a, i32 %b) nounwind readnone ssp {185entry:186; CHECK-LABEL: t20:187; CHECK: udiv w0, w0, w1188; CHECK: ret189 %udiv = call i32 @llvm.aarch64.udiv.i32(i32 %a, i32 %b)190 ret i32 %udiv191}192 193define i64 @t21(i64 %a, i64 %b) nounwind readnone ssp {194entry:195; CHECK-LABEL: t21:196; CHECK: udiv x0, x0, x1197; CHECK: ret198 %udiv = call i64 @llvm.aarch64.udiv.i64(i64 %a, i64 %b)199 ret i64 %udiv200}201 202declare i32 @llvm.aarch64.sdiv.i32(i32, i32) nounwind readnone203declare i64 @llvm.aarch64.sdiv.i64(i64, i64) nounwind readnone204declare i32 @llvm.aarch64.udiv.i32(i32, i32) nounwind readnone205declare i64 @llvm.aarch64.udiv.i64(i64, i64) nounwind readnone206 207; 32-bit not.208define i32 @inv_32(i32 %x) nounwind ssp {209entry:210; CHECK: inv_32211; CHECK: mvn w0, w0212; CHECK: ret213 %inv = xor i32 %x, -1214 ret i32 %inv215}216 217; 64-bit not.218define i64 @inv_64(i64 %x) nounwind ssp {219entry:220; CHECK: inv_64221; CHECK: mvn x0, x0222; CHECK: ret223 %inv = xor i64 %x, -1224 ret i64 %inv225}226 227; Multiplying by a power of two plus or minus one is better done via shift228; and add/sub rather than the madd/msub instructions. The latter are 4+ cycles,229; and the former are two (total for the two instruction sequence for subtract).230define i32 @f0(i32 %a) nounwind readnone ssp {231; CHECK-LABEL: f0:232; CHECK-NEXT: add w0, w0, w0, lsl #3233; CHECK-NEXT: ret234 %res = mul i32 %a, 9235 ret i32 %res236}237 238define i64 @f1(i64 %a) nounwind readnone ssp {239; CHECK-LABEL: f1:240; CHECK-NEXT: lsl x8, x0, #4241; CHECK-NEXT: sub x0, x8, x0242; CHECK-NEXT: ret243 %res = mul i64 %a, 15244 ret i64 %res245}246 247define i32 @f2(i32 %a) nounwind readnone ssp {248; CHECK-LABEL: f2:249; CHECK-NEXT: lsl w8, w0, #3250; CHECK-NEXT: sub w0, w8, w0251; CHECK-NEXT: ret252 %res = mul nsw i32 %a, 7253 ret i32 %res254}255 256define i64 @f3(i64 %a) nounwind readnone ssp {257; CHECK-LABEL: f3:258; CHECK-NEXT: add x0, x0, x0, lsl #4259; CHECK-NEXT: ret260 %res = mul nsw i64 %a, 17261 ret i64 %res262}263 264define i32 @f4(i32 %a) nounwind readnone ssp {265; CHECK-LABEL: f4:266; CHECK-NEXT: add w0, w0, w0, lsl #1267; CHECK-NEXT: ret268 %res = mul i32 %a, 3269 ret i32 %res270}271