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1; RUN: llc < %s | FileCheck %s2 3; Vararg saving must save Q registers using the equivalent of STR/STP.4 5target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128"6target triple = "aarch64_be"7 8%struct.__va_list = type { ptr, ptr, ptr, i32, i32 }9 10declare void @llvm.va_start(ptr) nounwind11declare void @llvm.va_end(ptr) nounwind12 13define double @callee(i32 %a, ...) {14; CHECK: stp15; CHECK: stp16; CHECK: stp17; CHECK: stp18; CHECK: stp19; CHECK: stp20entry:21 %vl = alloca %struct.__va_list, align 822 call void @llvm.va_start(ptr %vl)23 %vr_offs_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 424 %vr_offs = load i32, ptr %vr_offs_p, align 425 %0 = icmp sgt i32 %vr_offs, -126 br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg27 28vaarg.maybe_reg: ; preds = %entry29 %new_reg_offs = add i32 %vr_offs, 1630 store i32 %new_reg_offs, ptr %vr_offs_p, align 431 %inreg = icmp slt i32 %new_reg_offs, 132 br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack33 34vaarg.in_reg: ; preds = %vaarg.maybe_reg35 %reg_top_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 236 %reg_top = load ptr, ptr %reg_top_p, align 837 %1 = sext i32 %vr_offs to i6438 %2 = getelementptr i8, ptr %reg_top, i64 %139 %3 = ptrtoint ptr %2 to i6440 %align_be = add i64 %3, 841 %4 = inttoptr i64 %align_be to ptr42 br label %vaarg.end43 44vaarg.on_stack: ; preds = %vaarg.maybe_reg, %entry45 %stack = load ptr, ptr %vl, align 846 %new_stack = getelementptr i8, ptr %stack, i64 847 store ptr %new_stack, ptr %vl, align 848 br label %vaarg.end49 50vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg51 %.sink = phi ptr [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]52 %5 = load double, ptr %.sink, align 853 call void @llvm.va_end(ptr %vl)54 ret double %555}56