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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -debugify-and-strip-all-safe -mcpu=cyclone -verify-machineinstrs -aarch64-enable-ccmp -aarch64-stress-ccmp | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -debugify-and-strip-all-safe -mcpu=cyclone -verify-machineinstrs -aarch64-enable-ccmp -aarch64-stress-ccmp -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4target triple = "arm64-apple-ios"5 6define i32 @single_same(i32 %a, i32 %b) nounwind ssp {7; CHECK-LABEL: single_same:8; CHECK: ; %bb.0: ; %entry9; CHECK-NEXT: cmp w0, #510; CHECK-NEXT: ccmp w1, #17, #4, ne11; CHECK-NEXT: b.ne LBB0_212; CHECK-NEXT: ; %bb.1: ; %if.then13; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill14; CHECK-NEXT: bl _foo15; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload16; CHECK-NEXT: LBB0_2: ; %if.end17; CHECK-NEXT: mov w0, #7 ; =0x718; CHECK-NEXT: ret19entry:20 %cmp = icmp eq i32 %a, 521 %cmp1 = icmp eq i32 %b, 1722 %or.cond = or i1 %cmp, %cmp123 br i1 %or.cond, label %if.then, label %if.end24 25if.then:26 %call = tail call i32 @foo() nounwind27 br label %if.end28 29if.end:30 ret i32 731}32 33; Different condition codes for the two compares.34define i32 @single_different(i32 %a, i32 %b) nounwind ssp {35; CHECK-SD-LABEL: single_different:36; CHECK-SD: ; %bb.0: ; %entry37; CHECK-SD-NEXT: cmp w0, #638; CHECK-SD-NEXT: ccmp w1, #17, #0, ge39; CHECK-SD-NEXT: b.eq LBB1_240; CHECK-SD-NEXT: ; %bb.1: ; %if.then41; CHECK-SD-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill42; CHECK-SD-NEXT: bl _foo43; CHECK-SD-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload44; CHECK-SD-NEXT: LBB1_2: ; %if.end45; CHECK-SD-NEXT: mov w0, #7 ; =0x746; CHECK-SD-NEXT: ret47;48; CHECK-GI-LABEL: single_different:49; CHECK-GI: ; %bb.0: ; %entry50; CHECK-GI-NEXT: cmp w0, #551; CHECK-GI-NEXT: ccmp w1, #17, #0, gt52; CHECK-GI-NEXT: b.eq LBB1_253; CHECK-GI-NEXT: ; %bb.1: ; %if.then54; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill55; CHECK-GI-NEXT: bl _foo56; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload57; CHECK-GI-NEXT: LBB1_2: ; %if.end58; CHECK-GI-NEXT: mov w0, #7 ; =0x759; CHECK-GI-NEXT: ret60entry:61 %cmp = icmp sle i32 %a, 562 %cmp1 = icmp ne i32 %b, 1763 %or.cond = or i1 %cmp, %cmp164 br i1 %or.cond, label %if.then, label %if.end65 66if.then:67 %call = tail call i32 @foo() nounwind68 br label %if.end69 70if.end:71 ret i32 772}73 74; Second block clobbers the flags, can't convert (easily).75define i32 @single_flagclobber(i32 %a, i32 %b) nounwind ssp {76; CHECK-SD-LABEL: single_flagclobber:77; CHECK-SD: ; %bb.0: ; %entry78; CHECK-SD-NEXT: cmp w0, #579; CHECK-SD-NEXT: b.eq LBB2_280; CHECK-SD-NEXT: ; %bb.1: ; %lor.lhs.false81; CHECK-SD-NEXT: lsl w8, w1, #182; CHECK-SD-NEXT: cmp w1, #783; CHECK-SD-NEXT: csinc w8, w8, w1, lt84; CHECK-SD-NEXT: cmp w8, #1685; CHECK-SD-NEXT: b.gt LBB2_386; CHECK-SD-NEXT: LBB2_2: ; %if.then87; CHECK-SD-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill88; CHECK-SD-NEXT: bl _foo89; CHECK-SD-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload90; CHECK-SD-NEXT: LBB2_3: ; %if.end91; CHECK-SD-NEXT: mov w0, #7 ; =0x792; CHECK-SD-NEXT: ret93;94; CHECK-GI-LABEL: single_flagclobber:95; CHECK-GI: ; %bb.0: ; %entry96; CHECK-GI-NEXT: cmp w0, #597; CHECK-GI-NEXT: b.eq LBB2_298; CHECK-GI-NEXT: ; %bb.1: ; %lor.lhs.false99; CHECK-GI-NEXT: lsl w8, w1, #1100; CHECK-GI-NEXT: cmp w1, #7101; CHECK-GI-NEXT: csinc w8, w8, w1, lt102; CHECK-GI-NEXT: cmp w8, #17103; CHECK-GI-NEXT: b.ge LBB2_3104; CHECK-GI-NEXT: LBB2_2: ; %if.then105; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill106; CHECK-GI-NEXT: bl _foo107; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload108; CHECK-GI-NEXT: LBB2_3: ; %if.end109; CHECK-GI-NEXT: mov w0, #7 ; =0x7110; CHECK-GI-NEXT: ret111entry:112 %cmp = icmp eq i32 %a, 5113 br i1 %cmp, label %if.then, label %lor.lhs.false114 115lor.lhs.false: ; preds = %entry116 %cmp1 = icmp slt i32 %b, 7117 %mul = shl nsw i32 %b, 1118 %add = add nsw i32 %b, 1119 %cond = select i1 %cmp1, i32 %mul, i32 %add120 %cmp2 = icmp slt i32 %cond, 17121 br i1 %cmp2, label %if.then, label %if.end122 123if.then: ; preds = %lor.lhs.false, %entry124 %call = tail call i32 @foo() nounwind125 br label %if.end126 127if.end: ; preds = %if.then, %lor.lhs.false128 ret i32 7129}130 131; Second block clobbers the flags and ends with a tbz terminator.132define i32 @single_flagclobber_tbz(i32 %a, i32 %b) nounwind ssp {133; CHECK-LABEL: single_flagclobber_tbz:134; CHECK: ; %bb.0: ; %entry135; CHECK-NEXT: cmp w0, #5136; CHECK-NEXT: b.eq LBB3_2137; CHECK-NEXT: ; %bb.1: ; %lor.lhs.false138; CHECK-NEXT: lsl w8, w1, #1139; CHECK-NEXT: cmp w1, #7140; CHECK-NEXT: csinc w8, w8, w1, lt141; CHECK-NEXT: tbz w8, #3, LBB3_3142; CHECK-NEXT: LBB3_2: ; %if.then143; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill144; CHECK-NEXT: bl _foo145; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload146; CHECK-NEXT: LBB3_3: ; %if.end147; CHECK-NEXT: mov w0, #7 ; =0x7148; CHECK-NEXT: ret149entry:150 %cmp = icmp eq i32 %a, 5151 br i1 %cmp, label %if.then, label %lor.lhs.false152 153lor.lhs.false: ; preds = %entry154 %cmp1 = icmp slt i32 %b, 7155 %mul = shl nsw i32 %b, 1156 %add = add nsw i32 %b, 1157 %cond = select i1 %cmp1, i32 %mul, i32 %add158 %and = and i32 %cond, 8159 %cmp2 = icmp ne i32 %and, 0160 br i1 %cmp2, label %if.then, label %if.end161 162if.then: ; preds = %lor.lhs.false, %entry163 %call = tail call i32 @foo() nounwind164 br label %if.end165 166if.end: ; preds = %if.then, %lor.lhs.false167 ret i32 7168}169 170; Speculatively execute division by zero.171; The sdiv/udiv instructions do not trap when the divisor is zero, so they are172; safe to speculate.173define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {174; CHECK-SD-LABEL: speculate_division:175; CHECK-SD: ; %bb.0: ; %entry176; CHECK-SD-NEXT: cmp w0, #1177; CHECK-SD-NEXT: sdiv w8, w1, w0178; CHECK-SD-NEXT: ccmp w8, #16, #0, ge179; CHECK-SD-NEXT: b.le LBB4_2180; CHECK-SD-NEXT: ; %bb.1: ; %if.end181; CHECK-SD-NEXT: mov w0, #7 ; =0x7182; CHECK-SD-NEXT: ret183; CHECK-SD-NEXT: LBB4_2: ; %if.then184; CHECK-SD-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill185; CHECK-SD-NEXT: bl _foo186; CHECK-SD-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload187; CHECK-SD-NEXT: mov w0, #7 ; =0x7188; CHECK-SD-NEXT: ret189;190; CHECK-GI-LABEL: speculate_division:191; CHECK-GI: ; %bb.0: ; %entry192; CHECK-GI-NEXT: cmp w0, #0193; CHECK-GI-NEXT: sdiv w8, w1, w0194; CHECK-GI-NEXT: ccmp w8, #17, #0, gt195; CHECK-GI-NEXT: b.lt LBB4_2196; CHECK-GI-NEXT: ; %bb.1: ; %if.end197; CHECK-GI-NEXT: mov w0, #7 ; =0x7198; CHECK-GI-NEXT: ret199; CHECK-GI-NEXT: LBB4_2: ; %if.then200; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill201; CHECK-GI-NEXT: bl _foo202; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload203; CHECK-GI-NEXT: mov w0, #7 ; =0x7204; CHECK-GI-NEXT: ret205entry:206 %cmp = icmp sgt i32 %a, 0207 br i1 %cmp, label %land.lhs.true, label %if.end208 209land.lhs.true:210 %div = sdiv i32 %b, %a211 %cmp1 = icmp slt i32 %div, 17212 br i1 %cmp1, label %if.then, label %if.end213 214if.then:215 %call = tail call i32 @foo() nounwind216 br label %if.end217 218if.end:219 ret i32 7220}221 222; Floating point compare.223define i32 @single_fcmp(i32 %a, float %b) nounwind ssp {224; CHECK-SD-LABEL: single_fcmp:225; CHECK-SD: ; %bb.0: ; %entry226; CHECK-SD-NEXT: cmp w0, #1227; CHECK-SD-NEXT: scvtf s1, w0228; CHECK-SD-NEXT: fdiv s0, s0, s1229; CHECK-SD-NEXT: fmov s1, #17.00000000230; CHECK-SD-NEXT: fccmp s0, s1, #8, ge231; CHECK-SD-NEXT: b.ge LBB5_2232; CHECK-SD-NEXT: ; %bb.1: ; %if.end233; CHECK-SD-NEXT: mov w0, #7 ; =0x7234; CHECK-SD-NEXT: ret235; CHECK-SD-NEXT: LBB5_2: ; %if.then236; CHECK-SD-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill237; CHECK-SD-NEXT: bl _foo238; CHECK-SD-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload239; CHECK-SD-NEXT: mov w0, #7 ; =0x7240; CHECK-SD-NEXT: ret241;242; CHECK-GI-LABEL: single_fcmp:243; CHECK-GI: ; %bb.0: ; %entry244; CHECK-GI-NEXT: cmp w0, #0245; CHECK-GI-NEXT: scvtf s1, w0246; CHECK-GI-NEXT: fdiv s0, s0, s1247; CHECK-GI-NEXT: fmov s1, #17.00000000248; CHECK-GI-NEXT: fccmp s0, s1, #8, gt249; CHECK-GI-NEXT: b.ge LBB5_2250; CHECK-GI-NEXT: ; %bb.1: ; %if.end251; CHECK-GI-NEXT: mov w0, #7 ; =0x7252; CHECK-GI-NEXT: ret253; CHECK-GI-NEXT: LBB5_2: ; %if.then254; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill255; CHECK-GI-NEXT: bl _foo256; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload257; CHECK-GI-NEXT: mov w0, #7 ; =0x7258; CHECK-GI-NEXT: ret259entry:260 %cmp = icmp sgt i32 %a, 0261 br i1 %cmp, label %land.lhs.true, label %if.end262 263land.lhs.true:264 %conv = sitofp i32 %a to float265 %div = fdiv float %b, %conv266 %cmp1 = fcmp oge float %div, 1.700000e+01267 br i1 %cmp1, label %if.then, label %if.end268 269if.then:270 %call = tail call i32 @foo() nounwind271 br label %if.end272 273if.end:274 ret i32 7275}276 277; Chain multiple compares.278define void @multi_different(i32 %a, i32 %b, i32 %c) nounwind ssp {279; CHECK-LABEL: multi_different:280; CHECK: ; %bb.0: ; %entry281; CHECK-NEXT: cmp w0, w1282; CHECK-NEXT: sdiv w8, w1, w0283; CHECK-NEXT: ccmp w8, #5, #0, gt284; CHECK-NEXT: ccmp w8, w2, #4, eq285; CHECK-NEXT: b.gt LBB6_2286; CHECK-NEXT: ; %bb.1: ; %if.end287; CHECK-NEXT: ret288; CHECK-NEXT: LBB6_2: ; %if.then289; CHECK-NEXT: b _foo290entry:291 %cmp = icmp sgt i32 %a, %b292 br i1 %cmp, label %land.lhs.true, label %if.end293 294land.lhs.true:295 %div = sdiv i32 %b, %a296 %cmp1 = icmp eq i32 %div, 5297 %cmp4 = icmp sgt i32 %div, %c298 %or.cond = and i1 %cmp1, %cmp4299 br i1 %or.cond, label %if.then, label %if.end300 301if.then:302 %call = tail call i32 @foo() nounwind303 br label %if.end304 305if.end:306 ret void307}308 309; Convert a cbz in the head block.310define i32 @cbz_head(i32 %a, i32 %b) nounwind ssp {311; CHECK-LABEL: cbz_head:312; CHECK: ; %bb.0: ; %entry313; CHECK-NEXT: cmp w0, #0314; CHECK-NEXT: ccmp w1, #17, #0, ne315; CHECK-NEXT: b.eq LBB7_2316; CHECK-NEXT: ; %bb.1: ; %if.then317; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill318; CHECK-NEXT: bl _foo319; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload320; CHECK-NEXT: LBB7_2: ; %if.end321; CHECK-NEXT: mov w0, #7 ; =0x7322; CHECK-NEXT: ret323entry:324 %cmp = icmp eq i32 %a, 0325 %cmp1 = icmp ne i32 %b, 17326 %or.cond = or i1 %cmp, %cmp1327 br i1 %or.cond, label %if.then, label %if.end328 329if.then:330 %call = tail call i32 @foo() nounwind331 br label %if.end332 333if.end:334 ret i32 7335}336 337; Check that the immediate operand is in range. The ccmp instruction encodes a338; smaller range of immediates than subs/adds.339; The ccmp immediates must be in the range 0-31.340define i32 @immediate_range(i32 %a, i32 %b) nounwind ssp {341; CHECK-LABEL: immediate_range:342; CHECK: ; %bb.0: ; %entry343; CHECK-NEXT: cmp w0, #5344; CHECK-NEXT: b.eq LBB8_3345; CHECK-NEXT: ; %bb.1: ; %entry346; CHECK-NEXT: cmp w1, #32347; CHECK-NEXT: b.eq LBB8_3348; CHECK-NEXT: ; %bb.2: ; %if.end349; CHECK-NEXT: mov w0, #7 ; =0x7350; CHECK-NEXT: ret351; CHECK-NEXT: LBB8_3: ; %if.then352; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill353; CHECK-NEXT: bl _foo354; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload355; CHECK-NEXT: mov w0, #7 ; =0x7356; CHECK-NEXT: ret357entry:358 %cmp = icmp eq i32 %a, 5359 %cmp1 = icmp eq i32 %b, 32360 %or.cond = or i1 %cmp, %cmp1361 br i1 %or.cond, label %if.then, label %if.end362 363if.then:364 %call = tail call i32 @foo() nounwind365 br label %if.end366 367if.end:368 ret i32 7369}370 371; Convert a cbz in the second block.372define i32 @cbz_second(i32 %a, i32 %b) nounwind ssp {373; CHECK-LABEL: cbz_second:374; CHECK: ; %bb.0: ; %entry375; CHECK-NEXT: cmp w0, #0376; CHECK-NEXT: ccmp w1, #0, #0, ne377; CHECK-NEXT: b.eq LBB9_2378; CHECK-NEXT: ; %bb.1: ; %if.then379; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill380; CHECK-NEXT: bl _foo381; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload382; CHECK-NEXT: LBB9_2: ; %if.end383; CHECK-NEXT: mov w0, #7 ; =0x7384; CHECK-NEXT: ret385entry:386 %cmp = icmp eq i32 %a, 0387 %cmp1 = icmp ne i32 %b, 0388 %or.cond = or i1 %cmp, %cmp1389 br i1 %or.cond, label %if.then, label %if.end390 391if.then:392 %call = tail call i32 @foo() nounwind393 br label %if.end394 395if.end:396 ret i32 7397}398 399; Convert a cbnz in the second block.400define i32 @cbnz_second(i32 %a, i32 %b) nounwind ssp {401; CHECK-LABEL: cbnz_second:402; CHECK: ; %bb.0: ; %entry403; CHECK-NEXT: cmp w0, #0404; CHECK-NEXT: ccmp w1, #0, #4, ne405; CHECK-NEXT: b.ne LBB10_2406; CHECK-NEXT: ; %bb.1: ; %if.then407; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill408; CHECK-NEXT: bl _foo409; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload410; CHECK-NEXT: LBB10_2: ; %if.end411; CHECK-NEXT: mov w0, #7 ; =0x7412; CHECK-NEXT: ret413entry:414 %cmp = icmp eq i32 %a, 0415 %cmp1 = icmp eq i32 %b, 0416 %or.cond = or i1 %cmp, %cmp1417 br i1 %or.cond, label %if.then, label %if.end418 419if.then:420 %call = tail call i32 @foo() nounwind421 br label %if.end422 423if.end:424 ret i32 7425}426declare i32 @foo()427 428%str1 = type { %str2 }429%str2 = type { [24 x i8], ptr, i32, ptr, i32, [4 x i8], ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8, ptr, ptr, ptr }430 431; Test case distilled from 126.gcc.432; The phi in sw.bb.i.i gets multiple operands for the %entry predecessor.433define void @build_modify_expr(i32 %cond) nounwind ssp {434; CHECK-LABEL: build_modify_expr:435; CHECK: ; %bb.0: ; %entry436; CHECK-NEXT: ret437entry:438 switch i32 %cond, label %sw.bb.i.i [439 i32 69, label %if.end85440 i32 70, label %if.end85441 i32 71, label %if.end85442 i32 72, label %if.end85443 i32 73, label %if.end85444 i32 105, label %if.end85445 i32 106, label %if.end85446 ]447 448if.end85:449 ret void450 451sw.bb.i.i:452 %ref.tr.i.i = phi ptr [ %0, %sw.bb.i.i ], [ undef, %entry ]453 %operands.i.i = getelementptr inbounds %str1, ptr %ref.tr.i.i, i64 0, i32 0, i32 2454 %0 = load ptr, ptr %operands.i.i, align 8455 %code1.i.i.phi.trans.insert = getelementptr inbounds %str1, ptr %0, i64 0, i32 0, i32 0, i64 16456 br label %sw.bb.i.i457}458 459define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {460; CHECK-LABEL: select_and:461; CHECK: ; %bb.0:462; CHECK-NEXT: cmp w1, #5463; CHECK-NEXT: ccmp w0, w1, #0, ne464; CHECK-NEXT: csel x0, x2, x3, lt465; CHECK-NEXT: ret466 %1 = icmp slt i32 %w0, %w1467 %2 = icmp ne i32 5, %w1468 %3 = and i1 %1, %2469 %sel = select i1 %3, i64 %x2, i64 %x3470 ret i64 %sel471}472 473define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {474; CHECK-LABEL: select_or:475; CHECK: ; %bb.0:476; CHECK-NEXT: cmp w1, #5477; CHECK-NEXT: ccmp w0, w1, #8, eq478; CHECK-NEXT: csel x0, x2, x3, lt479; CHECK-NEXT: ret480 %1 = icmp slt i32 %w0, %w1481 %2 = icmp ne i32 5, %w1482 %3 = or i1 %1, %2483 %sel = select i1 %3, i64 %x2, i64 %x3484 ret i64 %sel485}486 487define float @select_or_float(i32 %w0, i32 %w1, float %x2, float %x3) {488; CHECK-LABEL: select_or_float:489; CHECK: ; %bb.0:490; CHECK-NEXT: cmp w1, #5491; CHECK-NEXT: ccmp w0, w1, #8, eq492; CHECK-NEXT: fcsel s0, s0, s1, lt493; CHECK-NEXT: ret494 %1 = icmp slt i32 %w0, %w1495 %2 = icmp ne i32 5, %w1496 %3 = or i1 %1, %2497 %sel = select i1 %3, float %x2,float %x3498 ret float %sel499}500 501define i64 @gccbug(i64 %x0, i64 %x1) {502; CHECK-SD-LABEL: gccbug:503; CHECK-SD: ; %bb.0:504; CHECK-SD-NEXT: cmp x0, #2505; CHECK-SD-NEXT: ccmp x0, #4, #4, ne506; CHECK-SD-NEXT: ccmp x1, #0, #0, eq507; CHECK-SD-NEXT: mov w8, #1 ; =0x1508; CHECK-SD-NEXT: cinc x0, x8, eq509; CHECK-SD-NEXT: ret510;511; CHECK-GI-LABEL: gccbug:512; CHECK-GI: ; %bb.0:513; CHECK-GI-NEXT: cmp x1, #0514; CHECK-GI-NEXT: cset w8, eq515; CHECK-GI-NEXT: cmp x0, #2516; CHECK-GI-NEXT: cset w9, eq517; CHECK-GI-NEXT: cmp x0, #4518; CHECK-GI-NEXT: cset w10, eq519; CHECK-GI-NEXT: orr w9, w10, w9520; CHECK-GI-NEXT: and w8, w9, w8521; CHECK-GI-NEXT: and x8, x8, #0x1522; CHECK-GI-NEXT: add x0, x8, #1523; CHECK-GI-NEXT: ret524 %cmp0 = icmp eq i64 %x1, 0525 %cmp1 = icmp eq i64 %x0, 2526 %cmp2 = icmp eq i64 %x0, 4527 528 %or = or i1 %cmp2, %cmp1529 %and = and i1 %or, %cmp0530 531 %sel = select i1 %and, i64 2, i64 1532 ret i64 %sel533}534 535define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) {536; CHECK-LABEL: select_ororand:537; CHECK: ; %bb.0:538; CHECK-NEXT: cmp w3, #4539; CHECK-NEXT: ccmp w2, #2, #0, gt540; CHECK-NEXT: ccmp w1, #13, #2, ge541; CHECK-NEXT: ccmp w0, #0, #4, ls542; CHECK-NEXT: csel w0, w3, wzr, eq543; CHECK-NEXT: ret544 %c0 = icmp eq i32 %w0, 0545 %c1 = icmp ugt i32 %w1, 13546 %c2 = icmp slt i32 %w2, 2547 %c4 = icmp sgt i32 %w3, 4548 %or = or i1 %c0, %c1549 %and = and i1 %c2, %c4550 %or1 = or i1 %or, %and551 %sel = select i1 %or1, i32 %w3, i32 0552 ret i32 %sel553}554 555define i32 @select_andor(i32 %v1, i32 %v2, i32 %v3) {556; CHECK-LABEL: select_andor:557; CHECK: ; %bb.0:558; CHECK-NEXT: cmp w1, w2559; CHECK-NEXT: ccmp w0, #0, #4, lt560; CHECK-NEXT: ccmp w0, w1, #0, eq561; CHECK-NEXT: csel w0, w0, w1, eq562; CHECK-NEXT: ret563 %c0 = icmp eq i32 %v1, %v2564 %c1 = icmp sge i32 %v2, %v3565 %c2 = icmp eq i32 %v1, 0566 %or = or i1 %c2, %c1567 %and = and i1 %or, %c0568 %sel = select i1 %and, i32 %v1, i32 %v2569 ret i32 %sel570}571 572define i32 @select_andor32(i32 %v1, i32 %v2, i32 %v3) {573; CHECK-SD-LABEL: select_andor32:574; CHECK-SD: ; %bb.0:575; CHECK-SD-NEXT: cmp w1, w2576; CHECK-SD-NEXT: mov w8, #32 ; =0x20577; CHECK-SD-NEXT: ccmp w0, w8, #4, lt578; CHECK-SD-NEXT: ccmp w0, w1, #0, eq579; CHECK-SD-NEXT: csel w0, w0, w1, eq580; CHECK-SD-NEXT: ret581;582; CHECK-GI-LABEL: select_andor32:583; CHECK-GI: ; %bb.0:584; CHECK-GI-NEXT: mov w8, #32 ; =0x20585; CHECK-GI-NEXT: cmp w1, w2586; CHECK-GI-NEXT: ccmp w0, w8, #4, lt587; CHECK-GI-NEXT: ccmp w0, w1, #0, eq588; CHECK-GI-NEXT: csel w0, w0, w1, eq589; CHECK-GI-NEXT: ret590 %c0 = icmp eq i32 %v1, %v2591 %c1 = icmp sge i32 %v2, %v3592 %c2 = icmp eq i32 %v1, 32593 %or = or i1 %c2, %c1594 %and = and i1 %or, %c0595 %sel = select i1 %and, i32 %v1, i32 %v2596 ret i32 %sel597}598 599define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {600; CHECK-SD-LABEL: select_noccmp1:601; CHECK-SD: ; %bb.0:602; CHECK-SD-NEXT: cmp x0, #0603; CHECK-SD-NEXT: ccmp x0, #13, #4, mi604; CHECK-SD-NEXT: cset w8, gt605; CHECK-SD-NEXT: cmp x2, #2606; CHECK-SD-NEXT: ccmp x2, #4, #4, lt607; CHECK-SD-NEXT: csinc w8, w8, wzr, le608; CHECK-SD-NEXT: cmp w8, #0609; CHECK-SD-NEXT: csel x0, xzr, x3, ne610; CHECK-SD-NEXT: ret611;612; CHECK-GI-LABEL: select_noccmp1:613; CHECK-GI: ; %bb.0:614; CHECK-GI-NEXT: mov x0, x3615; CHECK-GI-NEXT: ret616 %c0 = icmp slt i64 %v1, 0617 %c1 = icmp sgt i64 %v1, 13618 %c2 = icmp slt i64 %v3, 2619 %c4 = icmp sgt i64 %v3, 4620 %and0 = and i1 %c0, %c1621 %and1 = and i1 %c2, %c4622 %or = or i1 %and0, %and1623 %sel = select i1 %or, i64 0, i64 %r624 ret i64 %sel625}626 627@g = global i32 0628 629define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) {630; CHECK-SD-LABEL: select_noccmp2:631; CHECK-SD: ; %bb.0:632; CHECK-SD-NEXT: cmp x0, #0633; CHECK-SD-NEXT: ccmp x0, #13, #0, pl634; CHECK-SD-NEXT: cset w8, gt635; CHECK-SD-NEXT: csetm w9, gt636; CHECK-SD-NEXT: cmp w8, #0637; CHECK-SD-NEXT: csel x0, xzr, x3, ne638; CHECK-SD-NEXT: adrp x8, _g@PAGE639; CHECK-SD-NEXT: str w9, [x8, _g@PAGEOFF]640; CHECK-SD-NEXT: ret641;642; CHECK-GI-LABEL: select_noccmp2:643; CHECK-GI: ; %bb.0:644; CHECK-GI-NEXT: cmp x0, #14645; CHECK-GI-NEXT: cset w8, hs646; CHECK-GI-NEXT: tst w8, #0x1647; CHECK-GI-NEXT: csel x0, xzr, x3, ne648; CHECK-GI-NEXT: sbfx w8, w8, #0, #1649; CHECK-GI-NEXT: adrp x9, _g@PAGE650; CHECK-GI-NEXT: str w8, [x9, _g@PAGEOFF]651; CHECK-GI-NEXT: ret652 %c0 = icmp slt i64 %v1, 0653 %c1 = icmp sgt i64 %v1, 13654 %or = or i1 %c0, %c1655 %sel = select i1 %or, i64 0, i64 %r656 %ext = sext i1 %or to i32657 store volatile i32 %ext, ptr @g658 ret i64 %sel659}660 661; The following is not possible to implement with a single cmp;ccmp;csel662; sequence.663define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) {664; CHECK-SD-LABEL: select_noccmp3:665; CHECK-SD: ; %bb.0:666; CHECK-SD-NEXT: cmp w0, #0667; CHECK-SD-NEXT: ccmp w0, #13, #0, pl668; CHECK-SD-NEXT: cset w8, gt669; CHECK-SD-NEXT: cmp w0, #22670; CHECK-SD-NEXT: mov w9, #44 ; =0x2c671; CHECK-SD-NEXT: ccmp w0, w9, #0, ge672; CHECK-SD-NEXT: csel w8, wzr, w8, le673; CHECK-SD-NEXT: cmp w0, #99674; CHECK-SD-NEXT: mov w9, #77 ; =0x4d675; CHECK-SD-NEXT: ccmp w0, w9, #4, ne676; CHECK-SD-NEXT: cset w9, eq677; CHECK-SD-NEXT: tst w8, w9678; CHECK-SD-NEXT: csel w0, w1, w2, ne679; CHECK-SD-NEXT: ret680;681; CHECK-GI-LABEL: select_noccmp3:682; CHECK-GI: ; %bb.0:683; CHECK-GI-NEXT: mov w8, #99 ; =0x63684; CHECK-GI-NEXT: sub w9, w0, #45685; CHECK-GI-NEXT: cmp w0, #77686; CHECK-GI-NEXT: ccmp w0, w8, #4, ne687; CHECK-GI-NEXT: ccmn w9, #23, #2, eq688; CHECK-GI-NEXT: ccmp w0, #14, #0, lo689; CHECK-GI-NEXT: csel w0, w1, w2, hs690; CHECK-GI-NEXT: ret691 %c0 = icmp slt i32 %v0, 0692 %c1 = icmp sgt i32 %v0, 13693 %c2 = icmp slt i32 %v0, 22694 %c3 = icmp sgt i32 %v0, 44695 %c4 = icmp eq i32 %v0, 99696 %c5 = icmp eq i32 %v0, 77697 %or0 = or i1 %c0, %c1698 %or1 = or i1 %c2, %c3699 %and0 = and i1 %or0, %or1700 %or2 = or i1 %c4, %c5701 %and1 = and i1 %and0, %or2702 %sel = select i1 %and1, i32 %v1, i32 %v2703 ret i32 %sel704}705 706; Test the IR CCs that expand to two cond codes.707 708define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {709; CHECK-LABEL: select_and_olt_one:710; CHECK: ; %bb.0:711; CHECK-NEXT: fcmp d0, d1712; CHECK-NEXT: fccmp d2, d3, #4, mi713; CHECK-NEXT: fccmp d2, d3, #1, ne714; CHECK-NEXT: csel w0, w0, w1, vc715; CHECK-NEXT: ret716 %c0 = fcmp olt double %v0, %v1717 %c1 = fcmp one double %v2, %v3718 %cr = and i1 %c1, %c0719 %sel = select i1 %cr, i32 %a, i32 %b720 ret i32 %sel721}722 723define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {724; CHECK-LABEL: select_and_one_olt:725; CHECK: ; %bb.0:726; CHECK-NEXT: fcmp d0, d1727; CHECK-NEXT: fccmp d0, d1, #1, ne728; CHECK-NEXT: fccmp d2, d3, #0, vc729; CHECK-NEXT: csel w0, w0, w1, mi730; CHECK-NEXT: ret731 %c0 = fcmp one double %v0, %v1732 %c1 = fcmp olt double %v2, %v3733 %cr = and i1 %c1, %c0734 %sel = select i1 %cr, i32 %a, i32 %b735 ret i32 %sel736}737 738define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {739; CHECK-LABEL: select_and_olt_ueq:740; CHECK: ; %bb.0:741; CHECK-NEXT: fcmp d0, d1742; CHECK-NEXT: fccmp d2, d3, #0, mi743; CHECK-NEXT: fccmp d2, d3, #8, le744; CHECK-NEXT: csel w0, w0, w1, pl745; CHECK-NEXT: ret746 %c0 = fcmp olt double %v0, %v1747 %c1 = fcmp ueq double %v2, %v3748 %cr = and i1 %c1, %c0749 %sel = select i1 %cr, i32 %a, i32 %b750 ret i32 %sel751}752 753define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {754; CHECK-LABEL: select_and_ueq_olt:755; CHECK: ; %bb.0:756; CHECK-NEXT: fcmp d0, d1757; CHECK-NEXT: fccmp d0, d1, #8, le758; CHECK-NEXT: fccmp d2, d3, #0, pl759; CHECK-NEXT: csel w0, w0, w1, mi760; CHECK-NEXT: ret761 %c0 = fcmp ueq double %v0, %v1762 %c1 = fcmp olt double %v2, %v3763 %cr = and i1 %c1, %c0764 %sel = select i1 %cr, i32 %a, i32 %b765 ret i32 %sel766}767 768define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {769; CHECK-LABEL: select_or_olt_one:770; CHECK: ; %bb.0:771; CHECK-NEXT: fcmp d0, d1772; CHECK-NEXT: fccmp d2, d3, #0, pl773; CHECK-NEXT: fccmp d2, d3, #8, le774; CHECK-NEXT: csel w0, w0, w1, mi775; CHECK-NEXT: ret776 %c0 = fcmp olt double %v0, %v1777 %c1 = fcmp one double %v2, %v3778 %cr = or i1 %c1, %c0779 %sel = select i1 %cr, i32 %a, i32 %b780 ret i32 %sel781}782 783define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {784; CHECK-LABEL: select_or_one_olt:785; CHECK: ; %bb.0:786; CHECK-NEXT: fcmp d0, d1787; CHECK-NEXT: fccmp d0, d1, #8, le788; CHECK-NEXT: fccmp d2, d3, #8, pl789; CHECK-NEXT: csel w0, w0, w1, mi790; CHECK-NEXT: ret791 %c0 = fcmp one double %v0, %v1792 %c1 = fcmp olt double %v2, %v3793 %cr = or i1 %c1, %c0794 %sel = select i1 %cr, i32 %a, i32 %b795 ret i32 %sel796}797 798define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {799; CHECK-LABEL: select_or_olt_ueq:800; CHECK: ; %bb.0:801; CHECK-NEXT: fcmp d0, d1802; CHECK-NEXT: fccmp d2, d3, #4, pl803; CHECK-NEXT: fccmp d2, d3, #1, ne804; CHECK-NEXT: csel w0, w0, w1, vs805; CHECK-NEXT: ret806 %c0 = fcmp olt double %v0, %v1807 %c1 = fcmp ueq double %v2, %v3808 %cr = or i1 %c1, %c0809 %sel = select i1 %cr, i32 %a, i32 %b810 ret i32 %sel811}812 813define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {814; CHECK-LABEL: select_or_ueq_olt:815; CHECK: ; %bb.0:816; CHECK-NEXT: fcmp d0, d1817; CHECK-NEXT: fccmp d0, d1, #1, ne818; CHECK-NEXT: fccmp d2, d3, #8, vc819; CHECK-NEXT: csel w0, w0, w1, mi820; CHECK-NEXT: ret821 %c0 = fcmp ueq double %v0, %v1822 %c1 = fcmp olt double %v2, %v3823 %cr = or i1 %c1, %c0824 %sel = select i1 %cr, i32 %a, i32 %b825 ret i32 %sel826}827 828define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 {829; CHECK-LABEL: select_or_olt_ogt_ueq:830; CHECK: ; %bb.0:831; CHECK-NEXT: fcmp d0, d1832; CHECK-NEXT: fccmp d2, d3, #0, pl833; CHECK-NEXT: fccmp d4, d5, #4, le834; CHECK-NEXT: fccmp d4, d5, #1, ne835; CHECK-NEXT: csel w0, w0, w1, vs836; CHECK-NEXT: ret837 %c0 = fcmp olt double %v0, %v1838 %c1 = fcmp ogt double %v2, %v3839 %c2 = fcmp ueq double %v4, %v5840 %c3 = or i1 %c1, %c0841 %cr = or i1 %c2, %c3842 %sel = select i1 %cr, i32 %a, i32 %b843 ret i32 %sel844}845 846define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 {847; CHECK-LABEL: select_or_olt_ueq_ogt:848; CHECK: ; %bb.0:849; CHECK-NEXT: fcmp d0, d1850; CHECK-NEXT: fccmp d2, d3, #4, pl851; CHECK-NEXT: fccmp d2, d3, #1, ne852; CHECK-NEXT: fccmp d4, d5, #0, vc853; CHECK-NEXT: csel w0, w0, w1, gt854; CHECK-NEXT: ret855 %c0 = fcmp olt double %v0, %v1856 %c1 = fcmp ueq double %v2, %v3857 %c2 = fcmp ogt double %v4, %v5858 %c3 = or i1 %c1, %c0859 %cr = or i1 %c2, %c3860 %sel = select i1 %cr, i32 %a, i32 %b861 ret i32 %sel862}863 864; Verify that we correctly promote f16.865 866define i32 @half_select_and_olt_oge(half %v0, half %v1, half %v2, half %v3, i32 %a, i32 %b) #0 {867; CHECK-SD-LABEL: half_select_and_olt_oge:868; CHECK-SD: ; %bb.0:869; CHECK-SD-NEXT: fcvt s1, h1870; CHECK-SD-NEXT: fcvt s0, h0871; CHECK-SD-NEXT: fcmp s0, s1872; CHECK-SD-NEXT: fcvt s0, h3873; CHECK-SD-NEXT: fcvt s1, h2874; CHECK-SD-NEXT: fccmp s1, s0, #8, mi875; CHECK-SD-NEXT: csel w0, w0, w1, ge876; CHECK-SD-NEXT: ret877;878; CHECK-GI-LABEL: half_select_and_olt_oge:879; CHECK-GI: ; %bb.0:880; CHECK-GI-NEXT: fcvt s0, h0881; CHECK-GI-NEXT: fcvt s1, h1882; CHECK-GI-NEXT: fcvt s2, h2883; CHECK-GI-NEXT: fcvt s3, h3884; CHECK-GI-NEXT: fcmp s0, s1885; CHECK-GI-NEXT: fccmp s2, s3, #8, mi886; CHECK-GI-NEXT: csel w0, w0, w1, ge887; CHECK-GI-NEXT: ret888 %c0 = fcmp olt half %v0, %v1889 %c1 = fcmp oge half %v2, %v3890 %cr = and i1 %c1, %c0891 %sel = select i1 %cr, i32 %a, i32 %b892 ret i32 %sel893}894 895define i32 @half_select_and_olt_one(half %v0, half %v1, half %v2, half %v3, i32 %a, i32 %b) #0 {896; CHECK-SD-LABEL: half_select_and_olt_one:897; CHECK-SD: ; %bb.0:898; CHECK-SD-NEXT: fcvt s1, h1899; CHECK-SD-NEXT: fcvt s0, h0900; CHECK-SD-NEXT: fcmp s0, s1901; CHECK-SD-NEXT: fcvt s0, h3902; CHECK-SD-NEXT: fcvt s1, h2903; CHECK-SD-NEXT: fccmp s1, s0, #4, mi904; CHECK-SD-NEXT: fccmp s1, s0, #1, ne905; CHECK-SD-NEXT: csel w0, w0, w1, vc906; CHECK-SD-NEXT: ret907;908; CHECK-GI-LABEL: half_select_and_olt_one:909; CHECK-GI: ; %bb.0:910; CHECK-GI-NEXT: fcvt s0, h0911; CHECK-GI-NEXT: fcvt s1, h1912; CHECK-GI-NEXT: fcvt s2, h2913; CHECK-GI-NEXT: fcvt s3, h3914; CHECK-GI-NEXT: fcmp s0, s1915; CHECK-GI-NEXT: fccmp s2, s3, #4, mi916; CHECK-GI-NEXT: fccmp s2, s3, #1, ne917; CHECK-GI-NEXT: csel w0, w0, w1, vc918; CHECK-GI-NEXT: ret919 %c0 = fcmp olt half %v0, %v1920 %c1 = fcmp one half %v2, %v3921 %cr = and i1 %c1, %c0922 %sel = select i1 %cr, i32 %a, i32 %b923 ret i32 %sel924}925 926; Also verify that we don't try to generate f128 FCCMPs, using RT calls instead.927 928define i32 @f128_select_and_olt_oge(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32 %b) #0 {929; CHECK-SD-LABEL: f128_select_and_olt_oge:930; CHECK-SD: ; %bb.0:931; CHECK-SD-NEXT: sub sp, sp, #80932; CHECK-SD-NEXT: stp x22, x21, [sp, #32] ; 16-byte Folded Spill933; CHECK-SD-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill934; CHECK-SD-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill935; CHECK-SD-NEXT: mov x19, x1936; CHECK-SD-NEXT: mov x20, x0937; CHECK-SD-NEXT: stp q2, q3, [sp] ; 32-byte Folded Spill938; CHECK-SD-NEXT: bl ___lttf2939; CHECK-SD-NEXT: cmp w0, #0940; CHECK-SD-NEXT: cset w21, mi941; CHECK-SD-NEXT: ldp q0, q1, [sp] ; 32-byte Folded Reload942; CHECK-SD-NEXT: bl ___getf2943; CHECK-SD-NEXT: cmp w0, #0944; CHECK-SD-NEXT: cset w8, pl945; CHECK-SD-NEXT: tst w8, w21946; CHECK-SD-NEXT: csel w0, w20, w19, ne947; CHECK-SD-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload948; CHECK-SD-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload949; CHECK-SD-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload950; CHECK-SD-NEXT: add sp, sp, #80951; CHECK-SD-NEXT: ret952;953; CHECK-GI-LABEL: f128_select_and_olt_oge:954; CHECK-GI: ; %bb.0:955; CHECK-GI-NEXT: sub sp, sp, #80956; CHECK-GI-NEXT: stp x22, x21, [sp, #32] ; 16-byte Folded Spill957; CHECK-GI-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill958; CHECK-GI-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill959; CHECK-GI-NEXT: stp q3, q2, [sp] ; 32-byte Folded Spill960; CHECK-GI-NEXT: mov x19, x0961; CHECK-GI-NEXT: mov x20, x1962; CHECK-GI-NEXT: bl ___lttf2963; CHECK-GI-NEXT: mov x21, x0964; CHECK-GI-NEXT: ldp q1, q0, [sp] ; 32-byte Folded Reload965; CHECK-GI-NEXT: bl ___getf2966; CHECK-GI-NEXT: cmp w21, #0967; CHECK-GI-NEXT: ccmp w0, #0, #8, mi968; CHECK-GI-NEXT: csel w0, w19, w20, pl969; CHECK-GI-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload970; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload971; CHECK-GI-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload972; CHECK-GI-NEXT: add sp, sp, #80973; CHECK-GI-NEXT: ret974 %c0 = fcmp olt fp128 %v0, %v1975 %c1 = fcmp oge fp128 %v2, %v3976 %cr = and i1 %c1, %c0977 %sel = select i1 %cr, i32 %a, i32 %b978 ret i32 %sel979}980 981; This testcase resembles the core problem of http://llvm.org/PR39550982; (an OR operation is 2 levels deep but needs to be implemented first)983define i32 @deep_or(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {984; CHECK-LABEL: deep_or:985; CHECK: ; %bb.0:986; CHECK-NEXT: cmp w2, #20987; CHECK-NEXT: ccmp w2, #15, #4, ne988; CHECK-NEXT: ccmp w1, #0, #4, eq989; CHECK-NEXT: ccmp w0, #0, #4, ne990; CHECK-NEXT: csel w0, w4, w5, ne991; CHECK-NEXT: ret992 %c0 = icmp ne i32 %a0, 0993 %c1 = icmp ne i32 %a1, 0994 %c2 = icmp eq i32 %a2, 15995 %c3 = icmp eq i32 %a2, 20996 997 %or = or i1 %c2, %c3998 %and0 = and i1 %or, %c1999 %and1 = and i1 %and0, %c01000 %sel = select i1 %and1, i32 %x, i32 %y1001 ret i32 %sel1002}1003 1004; Variation of deep_or, we still need to implement the OR first though.1005define i32 @deep_or1(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {1006; CHECK-LABEL: deep_or1:1007; CHECK: ; %bb.0:1008; CHECK-NEXT: cmp w2, #201009; CHECK-NEXT: ccmp w2, #15, #4, ne1010; CHECK-NEXT: ccmp w0, #0, #4, eq1011; CHECK-NEXT: ccmp w1, #0, #4, ne1012; CHECK-NEXT: csel w0, w4, w5, ne1013; CHECK-NEXT: ret1014 %c0 = icmp ne i32 %a0, 01015 %c1 = icmp ne i32 %a1, 01016 %c2 = icmp eq i32 %a2, 151017 %c3 = icmp eq i32 %a2, 201018 1019 %or = or i1 %c2, %c31020 %and0 = and i1 %c0, %or1021 %and1 = and i1 %and0, %c11022 %sel = select i1 %and1, i32 %x, i32 %y1023 ret i32 %sel1024}1025 1026; Variation of deep_or, we still need to implement the OR first though.1027define i32 @deep_or2(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %x, i32 %y) {1028; CHECK-LABEL: deep_or2:1029; CHECK: ; %bb.0:1030; CHECK-NEXT: cmp w2, #201031; CHECK-NEXT: ccmp w2, #15, #4, ne1032; CHECK-NEXT: ccmp w1, #0, #4, eq1033; CHECK-NEXT: ccmp w0, #0, #4, ne1034; CHECK-NEXT: csel w0, w4, w5, ne1035; CHECK-NEXT: ret1036 %c0 = icmp ne i32 %a0, 01037 %c1 = icmp ne i32 %a1, 01038 %c2 = icmp eq i32 %a2, 151039 %c3 = icmp eq i32 %a2, 201040 1041 %or = or i1 %c2, %c31042 %and0 = and i1 %c0, %c11043 %and1 = and i1 %and0, %or1044 %sel = select i1 %and1, i32 %x, i32 %y1045 ret i32 %sel1046}1047 1048; This test is trying to test that multiple ccmp's don't get created in a way1049; that they would have multiple uses. It doesn't seem to.1050define i32 @multiccmp(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %x, i32 %y) #0 {1051; CHECK-SD-LABEL: multiccmp:1052; CHECK-SD: ; %bb.0: ; %entry1053; CHECK-SD-NEXT: stp x22, x21, [sp, #-48]! ; 16-byte Folded Spill1054; CHECK-SD-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill1055; CHECK-SD-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill1056; CHECK-SD-NEXT: mov x19, x51057; CHECK-SD-NEXT: cmp w0, w11058; CHECK-SD-NEXT: cset w20, gt1059; CHECK-SD-NEXT: cmp w2, w31060; CHECK-SD-NEXT: cset w21, ne1061; CHECK-SD-NEXT: tst w20, w211062; CHECK-SD-NEXT: csel w0, w5, w4, ne1063; CHECK-SD-NEXT: bl _callee1064; CHECK-SD-NEXT: tst w20, w211065; CHECK-SD-NEXT: csel w0, w0, w19, ne1066; CHECK-SD-NEXT: bl _callee1067; CHECK-SD-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload1068; CHECK-SD-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload1069; CHECK-SD-NEXT: ldp x22, x21, [sp], #48 ; 16-byte Folded Reload1070; CHECK-SD-NEXT: ret1071;1072; CHECK-GI-LABEL: multiccmp:1073; CHECK-GI: ; %bb.0: ; %entry1074; CHECK-GI-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill1075; CHECK-GI-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill1076; CHECK-GI-NEXT: mov x19, x51077; CHECK-GI-NEXT: cmp w0, w11078; CHECK-GI-NEXT: cset w8, gt1079; CHECK-GI-NEXT: cmp w2, w31080; CHECK-GI-NEXT: cset w9, ne1081; CHECK-GI-NEXT: and w20, w8, w91082; CHECK-GI-NEXT: tst w20, #0x11083; CHECK-GI-NEXT: csel w0, w5, w4, ne1084; CHECK-GI-NEXT: bl _callee1085; CHECK-GI-NEXT: tst w20, #0x11086; CHECK-GI-NEXT: csel w0, w0, w19, ne1087; CHECK-GI-NEXT: bl _callee1088; CHECK-GI-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload1089; CHECK-GI-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload1090; CHECK-GI-NEXT: ret1091entry:1092 %c0 = icmp sgt i32 %s0, %s11093 %c1 = icmp ne i32 %s2, %s31094 %a = and i1 %c0, %c11095 %s = select i1 %a, i32 %y, i32 %x1096 %o = call i32 @callee(i32 %s)1097 %z1 = select i1 %a, i32 %o, i32 %y1098 %p = call i32 @callee(i32 %z1)1099 ret i32 %p1100}1101 1102define i32 @multiccmp2(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %x, i32 %y) #0 {1103; CHECK-SD-LABEL: multiccmp2:1104; CHECK-SD: ; %bb.0: ; %entry1105; CHECK-SD-NEXT: stp x22, x21, [sp, #-48]! ; 16-byte Folded Spill1106; CHECK-SD-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill1107; CHECK-SD-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill1108; CHECK-SD-NEXT: mov x19, x51109; CHECK-SD-NEXT: mov x20, x31110; CHECK-SD-NEXT: mov x21, x01111; CHECK-SD-NEXT: cmp w0, w11112; CHECK-SD-NEXT: cset w8, gt1113; CHECK-SD-NEXT: cmp w2, w31114; CHECK-SD-NEXT: cset w22, ne1115; CHECK-SD-NEXT: tst w8, w221116; CHECK-SD-NEXT: csel w0, w5, w4, ne1117; CHECK-SD-NEXT: bl _callee1118; CHECK-SD-NEXT: cmp w21, w201119; CHECK-SD-NEXT: cset w8, eq1120; CHECK-SD-NEXT: tst w22, w81121; CHECK-SD-NEXT: csel w0, w0, w19, ne1122; CHECK-SD-NEXT: bl _callee1123; CHECK-SD-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload1124; CHECK-SD-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload1125; CHECK-SD-NEXT: ldp x22, x21, [sp], #48 ; 16-byte Folded Reload1126; CHECK-SD-NEXT: ret1127;1128; CHECK-GI-LABEL: multiccmp2:1129; CHECK-GI: ; %bb.0: ; %entry1130; CHECK-GI-NEXT: stp x22, x21, [sp, #-48]! ; 16-byte Folded Spill1131; CHECK-GI-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill1132; CHECK-GI-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill1133; CHECK-GI-NEXT: mov x19, x01134; CHECK-GI-NEXT: mov x20, x31135; CHECK-GI-NEXT: mov x21, x51136; CHECK-GI-NEXT: cmp w0, w11137; CHECK-GI-NEXT: cset w8, gt1138; CHECK-GI-NEXT: cmp w2, w31139; CHECK-GI-NEXT: cset w22, ne1140; CHECK-GI-NEXT: and w8, w8, w221141; CHECK-GI-NEXT: tst w8, #0x11142; CHECK-GI-NEXT: csel w0, w5, w4, ne1143; CHECK-GI-NEXT: bl _callee1144; CHECK-GI-NEXT: cmp w19, w201145; CHECK-GI-NEXT: cset w8, eq1146; CHECK-GI-NEXT: and w8, w22, w81147; CHECK-GI-NEXT: tst w8, #0x11148; CHECK-GI-NEXT: csel w0, w0, w21, ne1149; CHECK-GI-NEXT: bl _callee1150; CHECK-GI-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload1151; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload1152; CHECK-GI-NEXT: ldp x22, x21, [sp], #48 ; 16-byte Folded Reload1153; CHECK-GI-NEXT: ret1154entry:1155 %c0 = icmp sgt i32 %s0, %s11156 %c1 = icmp ne i32 %s2, %s31157 %a = and i1 %c0, %c11158 %z = zext i1 %a to i321159 %s = select i1 %a, i32 %y, i32 %x1160 %o = call i32 @callee(i32 %s)1161 1162 %c2 = icmp eq i32 %s0, %s31163 %a1 = and i1 %c1, %c21164 %z1 = select i1 %a1, i32 %o, i32 %y1165 %p = call i32 @callee(i32 %z1)1166 ret i32 %p1167}1168declare i32 @callee(i32)1169 1170define i1 @cmp_and_negative_const(i32 %0, i32 %1) {1171; CHECK-SD-LABEL: cmp_and_negative_const:1172; CHECK-SD: ; %bb.0:1173; CHECK-SD-NEXT: cmn w0, #11174; CHECK-SD-NEXT: ccmn w1, #2, #0, eq1175; CHECK-SD-NEXT: cset w0, eq1176; CHECK-SD-NEXT: ret1177;1178; CHECK-GI-LABEL: cmp_and_negative_const:1179; CHECK-GI: ; %bb.0:1180; CHECK-GI-NEXT: cmn w0, #11181; CHECK-GI-NEXT: cset w8, eq1182; CHECK-GI-NEXT: cmn w1, #21183; CHECK-GI-NEXT: cset w9, eq1184; CHECK-GI-NEXT: and w0, w8, w91185; CHECK-GI-NEXT: ret1186 %3 = icmp eq i32 %0, -11187 %4 = icmp eq i32 %1, -21188 %5 = and i1 %3, %41189 ret i1 %51190}1191 1192define i1 @cmp_or_negative_const(i32 %a, i32 %b) {1193; CHECK-SD-LABEL: cmp_or_negative_const:1194; CHECK-SD: ; %bb.0:1195; CHECK-SD-NEXT: cmn w0, #11196; CHECK-SD-NEXT: ccmn w1, #2, #4, ne1197; CHECK-SD-NEXT: cset w0, eq1198; CHECK-SD-NEXT: ret1199;1200; CHECK-GI-LABEL: cmp_or_negative_const:1201; CHECK-GI: ; %bb.0:1202; CHECK-GI-NEXT: cmn w0, #11203; CHECK-GI-NEXT: cset w8, eq1204; CHECK-GI-NEXT: cmn w1, #21205; CHECK-GI-NEXT: cset w9, eq1206; CHECK-GI-NEXT: orr w0, w8, w91207; CHECK-GI-NEXT: ret1208 %cmp = icmp eq i32 %a, -11209 %cmp1 = icmp eq i32 %b, -21210 %or.cond = or i1 %cmp, %cmp11211 ret i1 %or.cond1212}1213attributes #0 = { nounwind }1214