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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s3 4 5define <4 x i16> @fptosi_v4f64_to_v4i16(ptr %ptr) {6; CHECK-LABEL: fptosi_v4f64_to_v4i16:7; CHECK: // %bb.0:8; CHECK-NEXT: ldp q0, q1, [x0]9; CHECK-NEXT: fcvtzs v1.2d, v1.2d10; CHECK-NEXT: fcvtzs v0.2d, v0.2d11; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s12; CHECK-NEXT: xtn v0.4h, v0.4s13; CHECK-NEXT: ret14 %tmp1 = load <4 x double>, ptr %ptr15 %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16>16 ret <4 x i16> %tmp217}18 19define <8 x i8> @fptosi_v4f64_to_v4i8(ptr %ptr) {20; CHECK-LABEL: fptosi_v4f64_to_v4i8:21; CHECK: // %bb.0:22; CHECK-NEXT: ldp q1, q0, [x0, #32]23; CHECK-NEXT: ldp q2, q3, [x0]24; CHECK-NEXT: fcvtzs v0.2d, v0.2d25; CHECK-NEXT: fcvtzs v1.2d, v1.2d26; CHECK-NEXT: fcvtzs v3.2d, v3.2d27; CHECK-NEXT: fcvtzs v2.2d, v2.2d28; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s29; CHECK-NEXT: uzp1 v1.4s, v2.4s, v3.4s30; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h31; CHECK-NEXT: xtn v0.8b, v0.8h32; CHECK-NEXT: ret33 %tmp1 = load <8 x double>, ptr %ptr34 %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8>35 ret <8 x i8> %tmp236}37 38define <4 x half> @uitofp_v4i64_to_v4f16(ptr %ptr) {39; CHECK-LABEL: uitofp_v4i64_to_v4f16:40; CHECK: // %bb.0:41; CHECK-NEXT: ldp q0, q1, [x0]42; CHECK-NEXT: ucvtf v0.2d, v0.2d43; CHECK-NEXT: ucvtf v1.2d, v1.2d44; CHECK-NEXT: fcvtn v0.2s, v0.2d45; CHECK-NEXT: fcvtn2 v0.4s, v1.2d46; CHECK-NEXT: fcvtn v0.4h, v0.4s47; CHECK-NEXT: ret48 %tmp1 = load <4 x i64>, ptr %ptr49 %tmp2 = uitofp <4 x i64> %tmp1 to <4 x half>50 ret <4 x half> %tmp251}52 53define <4 x bfloat> @uitofp_v4i64_to_v4bf16(ptr %ptr) {54; CHECK-LABEL: uitofp_v4i64_to_v4bf16:55; CHECK: // %bb.0:56; CHECK-NEXT: ldp x8, x9, [x0]57; CHECK-NEXT: movi v2.4s, #127, msl #858; CHECK-NEXT: ucvtf s0, x959; CHECK-NEXT: ucvtf s1, x860; CHECK-NEXT: ldp x8, x9, [x0, #16]61; CHECK-NEXT: mov v1.s[1], v0.s[0]62; CHECK-NEXT: ucvtf s0, x863; CHECK-NEXT: mov v1.s[2], v0.s[0]64; CHECK-NEXT: ucvtf s0, x965; CHECK-NEXT: mov v1.s[3], v0.s[0]66; CHECK-NEXT: movi v0.4s, #167; CHECK-NEXT: ushr v3.4s, v1.4s, #1668; CHECK-NEXT: add v2.4s, v1.4s, v2.4s69; CHECK-NEXT: and v0.16b, v3.16b, v0.16b70; CHECK-NEXT: fcmeq v3.4s, v1.4s, v1.4s71; CHECK-NEXT: orr v1.4s, #64, lsl #1672; CHECK-NEXT: add v0.4s, v0.4s, v2.4s73; CHECK-NEXT: bif v0.16b, v1.16b, v3.16b74; CHECK-NEXT: shrn v0.4h, v0.4s, #1675; CHECK-NEXT: ret76 %tmp1 = load <4 x i64>, ptr %ptr77 %tmp2 = uitofp <4 x i64> %tmp1 to <4 x bfloat>78 ret <4 x bfloat> %tmp279}80 81define <4 x i16> @trunc_v4i64_to_v4i16(ptr %ptr) {82; CHECK-LABEL: trunc_v4i64_to_v4i16:83; CHECK: // %bb.0:84; CHECK-NEXT: ldp q1, q0, [x0]85; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s86; CHECK-NEXT: xtn v0.4h, v0.4s87; CHECK-NEXT: ret88 %tmp1 = load <4 x i64>, ptr %ptr89 %tmp2 = trunc <4 x i64> %tmp1 to <4 x i16>90 ret <4 x i16> %tmp291}92 93define <4 x i16> @fptoui_v4f64_to_v4i16(ptr %ptr) {94; CHECK-LABEL: fptoui_v4f64_to_v4i16:95; CHECK: // %bb.0:96; CHECK-NEXT: ldp q0, q1, [x0]97; CHECK-NEXT: fcvtzs v1.2d, v1.2d98; CHECK-NEXT: fcvtzs v0.2d, v0.2d99; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s100; CHECK-NEXT: xtn v0.4h, v0.4s101; CHECK-NEXT: ret102 %tmp1 = load <4 x double>, ptr %ptr103 %tmp2 = fptoui <4 x double> %tmp1 to <4 x i16>104 ret <4 x i16> %tmp2105}106