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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT3; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK4; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK5 6; CHECK-GI: warning: Instruction selection used fallback path for fptosi_i32_f16_simd7; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f16_simd8; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f32_simd9; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f64_simd10; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f64_simd11; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f32_simd12; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f16_simd13; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f16_simd14; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f32_simd15; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f64_simd16; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f64_simd17; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f32_simd18 19;20; FPTOI21;22 23define float @test_fptosi_f16_i32_simd(half %a) {24; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i32_simd:25; CHECK-NOFPRCVT: // %bb.0:26; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h027; CHECK-NOFPRCVT-NEXT: fmov s0, w828; CHECK-NOFPRCVT-NEXT: ret29;30; CHECK-LABEL: test_fptosi_f16_i32_simd:31; CHECK: // %bb.0:32; CHECK-NEXT: fcvtzs s0, h033; CHECK-NEXT: ret34 %r = fptosi half %a to i3235 %bc = bitcast i32 %r to float36 ret float %bc37}38 39define double @test_fptosi_f16_i64_simd(half %a) {40; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i64_simd:41; CHECK-NOFPRCVT: // %bb.0:42; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h043; CHECK-NOFPRCVT-NEXT: fmov d0, x844; CHECK-NOFPRCVT-NEXT: ret45;46; CHECK-LABEL: test_fptosi_f16_i64_simd:47; CHECK: // %bb.0:48; CHECK-NEXT: fcvtzs d0, h049; CHECK-NEXT: ret50 %r = fptosi half %a to i6451 %bc = bitcast i64 %r to double52 ret double %bc53}54 55define float @test_fptosi_f64_i32_simd(double %a) {56; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i32_simd:57; CHECK-NOFPRCVT: // %bb.0:58; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d059; CHECK-NOFPRCVT-NEXT: fmov s0, w860; CHECK-NOFPRCVT-NEXT: ret61;62; CHECK-LABEL: test_fptosi_f64_i32_simd:63; CHECK: // %bb.0:64; CHECK-NEXT: fcvtzs s0, d065; CHECK-NEXT: ret66 %r = fptosi double %a to i3267 %bc = bitcast i32 %r to float68 ret float %bc69}70 71define double @test_fptosi_f32_i64_simd(float %a) {72; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i64_simd:73; CHECK-NOFPRCVT: // %bb.0:74; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s075; CHECK-NOFPRCVT-NEXT: fmov d0, x876; CHECK-NOFPRCVT-NEXT: ret77;78; CHECK-LABEL: test_fptosi_f32_i64_simd:79; CHECK: // %bb.0:80; CHECK-NEXT: fcvtzs d0, s081; CHECK-NEXT: ret82 %r = fptosi float %a to i6483 %bc = bitcast i64 %r to double84 ret double %bc85}86 87define double @test_fptosi_f64_i64_simd(double %a) {88; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i64_simd:89; CHECK-NOFPRCVT: // %bb.0:90; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d091; CHECK-NOFPRCVT-NEXT: ret92;93; CHECK-LABEL: test_fptosi_f64_i64_simd:94; CHECK: // %bb.0:95; CHECK-NEXT: fcvtzs d0, d096; CHECK-NEXT: ret97 %r = fptosi double %a to i6498 %bc = bitcast i64 %r to double99 ret double %bc100}101 102 103define float @test_fptosi_f32_i32_simd(float %a) {104; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i32_simd:105; CHECK-NOFPRCVT: // %bb.0:106; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0107; CHECK-NOFPRCVT-NEXT: ret108;109; CHECK-LABEL: test_fptosi_f32_i32_simd:110; CHECK: // %bb.0:111; CHECK-NEXT: fcvtzs s0, s0112; CHECK-NEXT: ret113 %r = fptosi float %a to i32114 %bc = bitcast i32 %r to float115 ret float %bc116}117 118define float @test_fptoui_f16_i32_simd(half %a) {119; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i32_simd:120; CHECK-NOFPRCVT: // %bb.0:121; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h0122; CHECK-NOFPRCVT-NEXT: fmov s0, w8123; CHECK-NOFPRCVT-NEXT: ret124;125; CHECK-LABEL: test_fptoui_f16_i32_simd:126; CHECK: // %bb.0:127; CHECK-NEXT: fcvtzu s0, h0128; CHECK-NEXT: ret129 %r = fptoui half %a to i32130 %bc = bitcast i32 %r to float131 ret float %bc132}133 134define double @test_fptoui_f16_i64_simd(half %a) {135; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i64_simd:136; CHECK-NOFPRCVT: // %bb.0:137; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0138; CHECK-NOFPRCVT-NEXT: fmov d0, x8139; CHECK-NOFPRCVT-NEXT: ret140;141; CHECK-LABEL: test_fptoui_f16_i64_simd:142; CHECK: // %bb.0:143; CHECK-NEXT: fcvtzu d0, h0144; CHECK-NEXT: ret145 %r = fptoui half %a to i64146 %bc = bitcast i64 %r to double147 ret double %bc148}149 150define float @test_fptoui_f64_i32_simd(double %a) {151; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i32_simd:152; CHECK-NOFPRCVT: // %bb.0:153; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0154; CHECK-NOFPRCVT-NEXT: fmov s0, w8155; CHECK-NOFPRCVT-NEXT: ret156;157; CHECK-LABEL: test_fptoui_f64_i32_simd:158; CHECK: // %bb.0:159; CHECK-NEXT: fcvtzu s0, d0160; CHECK-NEXT: ret161 %r = fptoui double %a to i32162 %bc = bitcast i32 %r to float163 ret float %bc164}165 166define double @test_fptoui_f32_i64_simd(float %a) {167; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i64_simd:168; CHECK-NOFPRCVT: // %bb.0:169; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0170; CHECK-NOFPRCVT-NEXT: fmov d0, x8171; CHECK-NOFPRCVT-NEXT: ret172;173; CHECK-LABEL: test_fptoui_f32_i64_simd:174; CHECK: // %bb.0:175; CHECK-NEXT: fcvtzu d0, s0176; CHECK-NEXT: ret177 %r = fptoui float %a to i64178 %bc = bitcast i64 %r to double179 ret double %bc180}181 182define double @test_fptoui_f64_i64_simd(double %a) {183; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i64_simd:184; CHECK-NOFPRCVT: // %bb.0:185; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0186; CHECK-NOFPRCVT-NEXT: ret187;188; CHECK-LABEL: test_fptoui_f64_i64_simd:189; CHECK: // %bb.0:190; CHECK-NEXT: fcvtzu d0, d0191; CHECK-NEXT: ret192 %r = fptoui double %a to i64193 %bc = bitcast i64 %r to double194 ret double %bc195}196 197 198define float @test_fptoui_f32_i32_simd(float %a) {199; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i32_simd:200; CHECK-NOFPRCVT: // %bb.0:201; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0202; CHECK-NOFPRCVT-NEXT: ret203;204; CHECK-LABEL: test_fptoui_f32_i32_simd:205; CHECK: // %bb.0:206; CHECK-NEXT: fcvtzu s0, s0207; CHECK-NEXT: ret208 %r = fptoui float %a to i32209 %bc = bitcast i32 %r to float210 ret float %bc211}212 213 214;215; FPTOI strictfp216;217 218define float @fptosi_i32_f16_simd(half %x) {219; CHECK-NOFPRCVT-LABEL: fptosi_i32_f16_simd:220; CHECK-NOFPRCVT: // %bb.0:221; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0222; CHECK-NOFPRCVT-NEXT: fmov s0, w8223; CHECK-NOFPRCVT-NEXT: ret224;225; CHECK-LABEL: fptosi_i32_f16_simd:226; CHECK: // %bb.0:227; CHECK-NEXT: fcvtzs s0, h0228; CHECK-NEXT: ret229 %val = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %x, metadata !"fpexcept.strict")230 %sum = bitcast i32 %val to float231 ret float %sum232}233 234define double @fptosi_i64_f16_simd(half %x) {235; CHECK-NOFPRCVT-LABEL: fptosi_i64_f16_simd:236; CHECK-NOFPRCVT: // %bb.0:237; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0238; CHECK-NOFPRCVT-NEXT: fmov d0, x8239; CHECK-NOFPRCVT-NEXT: ret240;241; CHECK-LABEL: fptosi_i64_f16_simd:242; CHECK: // %bb.0:243; CHECK-NEXT: fcvtzs d0, h0244; CHECK-NEXT: ret245 %val = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %x, metadata !"fpexcept.strict")246 %sum = bitcast i64 %val to double247 ret double %sum248}249 250define double @fptosi_i64_f32_simd(float %x) {251; CHECK-NOFPRCVT-LABEL: fptosi_i64_f32_simd:252; CHECK-NOFPRCVT: // %bb.0:253; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0254; CHECK-NOFPRCVT-NEXT: fmov d0, x8255; CHECK-NOFPRCVT-NEXT: ret256;257; CHECK-LABEL: fptosi_i64_f32_simd:258; CHECK: // %bb.0:259; CHECK-NEXT: fcvtzs d0, s0260; CHECK-NEXT: ret261 %val = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %x, metadata !"fpexcept.strict")262 %bc = bitcast i64 %val to double263 ret double %bc264}265 266define float @fptosi_i32_f64_simd(double %x) {267; CHECK-NOFPRCVT-LABEL: fptosi_i32_f64_simd:268; CHECK-NOFPRCVT: // %bb.0:269; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0270; CHECK-NOFPRCVT-NEXT: fmov s0, w8271; CHECK-NOFPRCVT-NEXT: ret272;273; CHECK-LABEL: fptosi_i32_f64_simd:274; CHECK: // %bb.0:275; CHECK-NEXT: fcvtzs s0, d0276; CHECK-NEXT: ret277 %val = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %x, metadata !"fpexcept.strict")278 %bc = bitcast i32 %val to float279 ret float %bc280}281 282define double @fptosi_i64_f64_simd(double %x) {283; CHECK-NOFPRCVT-LABEL: fptosi_i64_f64_simd:284; CHECK-NOFPRCVT: // %bb.0:285; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0286; CHECK-NOFPRCVT-NEXT: ret287;288; CHECK-LABEL: fptosi_i64_f64_simd:289; CHECK: // %bb.0:290; CHECK-NEXT: fcvtzs d0, d0291; CHECK-NEXT: ret292 %val = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %x, metadata !"fpexcept.strict")293 %bc = bitcast i64 %val to double294 ret double %bc295}296 297define float @fptosi_i32_f32_simd(float %x) {298; CHECK-NOFPRCVT-LABEL: fptosi_i32_f32_simd:299; CHECK-NOFPRCVT: // %bb.0:300; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0301; CHECK-NOFPRCVT-NEXT: ret302;303; CHECK-LABEL: fptosi_i32_f32_simd:304; CHECK: // %bb.0:305; CHECK-NEXT: fcvtzs s0, s0306; CHECK-NEXT: ret307 %val = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %x, metadata !"fpexcept.strict")308 %bc = bitcast i32 %val to float309 ret float %bc310}311 312 313 314define float @fptoui_i32_f16_simd(half %x) {315; CHECK-NOFPRCVT-LABEL: fptoui_i32_f16_simd:316; CHECK-NOFPRCVT: // %bb.0:317; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h0318; CHECK-NOFPRCVT-NEXT: fmov s0, w8319; CHECK-NOFPRCVT-NEXT: ret320;321; CHECK-LABEL: fptoui_i32_f16_simd:322; CHECK: // %bb.0:323; CHECK-NEXT: fcvtzu s0, h0324; CHECK-NEXT: ret325 %val = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict")326 %sum = bitcast i32 %val to float327 ret float %sum328}329 330define double @fptoui_i64_f16_simd(half %x) {331; CHECK-NOFPRCVT-LABEL: fptoui_i64_f16_simd:332; CHECK-NOFPRCVT: // %bb.0:333; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0334; CHECK-NOFPRCVT-NEXT: fmov d0, x8335; CHECK-NOFPRCVT-NEXT: ret336;337; CHECK-LABEL: fptoui_i64_f16_simd:338; CHECK: // %bb.0:339; CHECK-NEXT: fcvtzu d0, h0340; CHECK-NEXT: ret341 %val = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %x, metadata !"fpexcept.strict")342 %sum = bitcast i64 %val to double343 ret double %sum344}345 346define double @fptoui_i64_f32_simd(float %x) {347; CHECK-NOFPRCVT-LABEL: fptoui_i64_f32_simd:348; CHECK-NOFPRCVT: // %bb.0:349; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0350; CHECK-NOFPRCVT-NEXT: fmov d0, x8351; CHECK-NOFPRCVT-NEXT: ret352;353; CHECK-LABEL: fptoui_i64_f32_simd:354; CHECK: // %bb.0:355; CHECK-NEXT: fcvtzu d0, s0356; CHECK-NEXT: ret357 %val = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %x, metadata !"fpexcept.strict")358 %bc = bitcast i64 %val to double359 ret double %bc360}361 362define float @fptoui_i32_f64_simd(double %x) {363; CHECK-NOFPRCVT-LABEL: fptoui_i32_f64_simd:364; CHECK-NOFPRCVT: // %bb.0:365; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0366; CHECK-NOFPRCVT-NEXT: fmov s0, w8367; CHECK-NOFPRCVT-NEXT: ret368;369; CHECK-LABEL: fptoui_i32_f64_simd:370; CHECK: // %bb.0:371; CHECK-NEXT: fcvtzu s0, d0372; CHECK-NEXT: ret373 %val = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict")374 %bc = bitcast i32 %val to float375 ret float %bc376}377 378define double @fptoui_i64_f64_simd(double %x) {379; CHECK-NOFPRCVT-LABEL: fptoui_i64_f64_simd:380; CHECK-NOFPRCVT: // %bb.0:381; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0382; CHECK-NOFPRCVT-NEXT: ret383;384; CHECK-LABEL: fptoui_i64_f64_simd:385; CHECK: // %bb.0:386; CHECK-NEXT: fcvtzu d0, d0387; CHECK-NEXT: ret388 %val = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %x, metadata !"fpexcept.strict")389 %bc = bitcast i64 %val to double390 ret double %bc391}392 393define float @fptoui_i32_f32_simd(float %x) {394; CHECK-NOFPRCVT-LABEL: fptoui_i32_f32_simd:395; CHECK-NOFPRCVT: // %bb.0:396; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0397; CHECK-NOFPRCVT-NEXT: ret398;399; CHECK-LABEL: fptoui_i32_f32_simd:400; CHECK: // %bb.0:401; CHECK-NEXT: fcvtzu s0, s0402; CHECK-NEXT: ret403 %val = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict")404 %bc = bitcast i32 %val to float405 ret float %bc406}407 408;409; FPTOI rounding410;411 412 413define double @fcvtas_ds_round_simd(float %a) {414; CHECK-NOFPRCVT-LABEL: fcvtas_ds_round_simd:415; CHECK-NOFPRCVT: // %bb.0:416; CHECK-NOFPRCVT-NEXT: fcvtas x8, s0417; CHECK-NOFPRCVT-NEXT: fmov d0, x8418; CHECK-NOFPRCVT-NEXT: ret419;420; CHECK-LABEL: fcvtas_ds_round_simd:421; CHECK: // %bb.0:422; CHECK-NEXT: fcvtas d0, s0423; CHECK-NEXT: ret424 %r = call float @llvm.round.f32(float %a)425 %i = fptosi float %r to i64426 %bc = bitcast i64 %i to double427 ret double %bc428}429 430define float @fcvtas_sd_round_simd(double %a) {431; CHECK-NOFPRCVT-LABEL: fcvtas_sd_round_simd:432; CHECK-NOFPRCVT: // %bb.0:433; CHECK-NOFPRCVT-NEXT: fcvtas w8, d0434; CHECK-NOFPRCVT-NEXT: fmov s0, w8435; CHECK-NOFPRCVT-NEXT: ret436;437; CHECK-LABEL: fcvtas_sd_round_simd:438; CHECK: // %bb.0:439; CHECK-NEXT: fcvtas s0, d0440; CHECK-NEXT: ret441 %r = call double @llvm.round.f64(double %a)442 %i = fptosi double %r to i32443 %bc = bitcast i32 %i to float444 ret float %bc445}446 447define float @fcvtas_ss_round_simd(float %a) {448; CHECK-NOFPRCVT-LABEL: fcvtas_ss_round_simd:449; CHECK-NOFPRCVT: // %bb.0:450; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0451; CHECK-NOFPRCVT-NEXT: ret452;453; CHECK-LABEL: fcvtas_ss_round_simd:454; CHECK: // %bb.0:455; CHECK-NEXT: fcvtas s0, s0456; CHECK-NEXT: ret457 %r = call float @llvm.round.f32(float %a)458 %i = fptosi float %r to i32459 %bc = bitcast i32 %i to float460 ret float %bc461}462 463define double @fcvtas_dd_round_simd(double %a) {464; CHECK-NOFPRCVT-LABEL: fcvtas_dd_round_simd:465; CHECK-NOFPRCVT: // %bb.0:466; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0467; CHECK-NOFPRCVT-NEXT: ret468;469; CHECK-LABEL: fcvtas_dd_round_simd:470; CHECK: // %bb.0:471; CHECK-NEXT: fcvtas d0, d0472; CHECK-NEXT: ret473 %r = call double @llvm.round.f64(double %a)474 %i = fptosi double %r to i64475 %bc = bitcast i64 %i to double476 ret double %bc477}478 479 480define double @fcvtau_ds_round_simd(float %a) {481; CHECK-NOFPRCVT-LABEL: fcvtau_ds_round_simd:482; CHECK-NOFPRCVT: // %bb.0:483; CHECK-NOFPRCVT-NEXT: fcvtau x8, s0484; CHECK-NOFPRCVT-NEXT: fmov d0, x8485; CHECK-NOFPRCVT-NEXT: ret486;487; CHECK-LABEL: fcvtau_ds_round_simd:488; CHECK: // %bb.0:489; CHECK-NEXT: fcvtau d0, s0490; CHECK-NEXT: ret491 %r = call float @llvm.round.f32(float %a)492 %i = fptoui float %r to i64493 %bc = bitcast i64 %i to double494 ret double %bc495}496 497define float @fcvtau_sd_round_simd(double %a) {498; CHECK-NOFPRCVT-LABEL: fcvtau_sd_round_simd:499; CHECK-NOFPRCVT: // %bb.0:500; CHECK-NOFPRCVT-NEXT: fcvtau w8, d0501; CHECK-NOFPRCVT-NEXT: fmov s0, w8502; CHECK-NOFPRCVT-NEXT: ret503;504; CHECK-LABEL: fcvtau_sd_round_simd:505; CHECK: // %bb.0:506; CHECK-NEXT: fcvtau s0, d0507; CHECK-NEXT: ret508 %r = call double @llvm.round.f64(double %a)509 %i = fptoui double %r to i32510 %bc = bitcast i32 %i to float511 ret float %bc512}513 514define float @fcvtau_ss_round_simd(float %a) {515; CHECK-NOFPRCVT-LABEL: fcvtau_ss_round_simd:516; CHECK-NOFPRCVT: // %bb.0:517; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0518; CHECK-NOFPRCVT-NEXT: ret519;520; CHECK-LABEL: fcvtau_ss_round_simd:521; CHECK: // %bb.0:522; CHECK-NEXT: fcvtas s0, s0523; CHECK-NEXT: ret524 %r = call float @llvm.round.f32(float %a)525 %i = fptosi float %r to i32526 %bc = bitcast i32 %i to float527 ret float %bc528}529 530define double @fcvtau_dd_round_simd(double %a) {531; CHECK-NOFPRCVT-LABEL: fcvtau_dd_round_simd:532; CHECK-NOFPRCVT: // %bb.0:533; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0534; CHECK-NOFPRCVT-NEXT: ret535;536; CHECK-LABEL: fcvtau_dd_round_simd:537; CHECK: // %bb.0:538; CHECK-NEXT: fcvtas d0, d0539; CHECK-NEXT: ret540 %r = call double @llvm.round.f64(double %a)541 %i = fptosi double %r to i64542 %bc = bitcast i64 %i to double543 ret double %bc544}545 546 547define double @fcvtms_ds_round_simd(float %a) {548; CHECK-NOFPRCVT-LABEL: fcvtms_ds_round_simd:549; CHECK-NOFPRCVT: // %bb.0:550; CHECK-NOFPRCVT-NEXT: fcvtms x8, s0551; CHECK-NOFPRCVT-NEXT: fmov d0, x8552; CHECK-NOFPRCVT-NEXT: ret553;554; CHECK-LABEL: fcvtms_ds_round_simd:555; CHECK: // %bb.0:556; CHECK-NEXT: fcvtms d0, s0557; CHECK-NEXT: ret558 %r = call float @llvm.floor.f32(float %a)559 %i = fptosi float %r to i64560 %bc = bitcast i64 %i to double561 ret double %bc562}563 564define float @fcvtms_sd_round_simd(double %a) {565; CHECK-NOFPRCVT-LABEL: fcvtms_sd_round_simd:566; CHECK-NOFPRCVT: // %bb.0:567; CHECK-NOFPRCVT-NEXT: fcvtms w8, d0568; CHECK-NOFPRCVT-NEXT: fmov s0, w8569; CHECK-NOFPRCVT-NEXT: ret570;571; CHECK-LABEL: fcvtms_sd_round_simd:572; CHECK: // %bb.0:573; CHECK-NEXT: fcvtms s0, d0574; CHECK-NEXT: ret575 %r = call double @llvm.floor.f64(double %a)576 %i = fptosi double %r to i32577 %bc = bitcast i32 %i to float578 ret float %bc579}580 581define float @fcvtms_ss_round_simd(float %a) {582; CHECK-NOFPRCVT-LABEL: fcvtms_ss_round_simd:583; CHECK-NOFPRCVT: // %bb.0:584; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0585; CHECK-NOFPRCVT-NEXT: ret586;587; CHECK-LABEL: fcvtms_ss_round_simd:588; CHECK: // %bb.0:589; CHECK-NEXT: fcvtms s0, s0590; CHECK-NEXT: ret591 %r = call float @llvm.floor.f32(float %a)592 %i = fptosi float %r to i32593 %bc = bitcast i32 %i to float594 ret float %bc595}596 597define double @fcvtms_dd_round_simd(double %a) {598; CHECK-NOFPRCVT-LABEL: fcvtms_dd_round_simd:599; CHECK-NOFPRCVT: // %bb.0:600; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0601; CHECK-NOFPRCVT-NEXT: ret602;603; CHECK-LABEL: fcvtms_dd_round_simd:604; CHECK: // %bb.0:605; CHECK-NEXT: fcvtms d0, d0606; CHECK-NEXT: ret607 %r = call double @llvm.floor.f64(double %a)608 %i = fptosi double %r to i64609 %bc = bitcast i64 %i to double610 ret double %bc611}612 613 614 615define double @fcvtmu_ds_round_simd(float %a) {616; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_round_simd:617; CHECK-NOFPRCVT: // %bb.0:618; CHECK-NOFPRCVT-NEXT: fcvtmu x8, s0619; CHECK-NOFPRCVT-NEXT: fmov d0, x8620; CHECK-NOFPRCVT-NEXT: ret621;622; CHECK-LABEL: fcvtmu_ds_round_simd:623; CHECK: // %bb.0:624; CHECK-NEXT: fcvtmu d0, s0625; CHECK-NEXT: ret626 %r = call float @llvm.floor.f32(float %a)627 %i = fptoui float %r to i64628 %bc = bitcast i64 %i to double629 ret double %bc630}631 632define float @fcvtmu_sd_round_simd(double %a) {633; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_round_simd:634; CHECK-NOFPRCVT: // %bb.0:635; CHECK-NOFPRCVT-NEXT: fcvtmu w8, d0636; CHECK-NOFPRCVT-NEXT: fmov s0, w8637; CHECK-NOFPRCVT-NEXT: ret638;639; CHECK-LABEL: fcvtmu_sd_round_simd:640; CHECK: // %bb.0:641; CHECK-NEXT: fcvtmu s0, d0642; CHECK-NEXT: ret643 %r = call double @llvm.floor.f64(double %a)644 %i = fptoui double %r to i32645 %bc = bitcast i32 %i to float646 ret float %bc647}648 649define float @fcvtmu_ss_round_simd(float %a) {650; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_round_simd:651; CHECK-NOFPRCVT: // %bb.0:652; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0653; CHECK-NOFPRCVT-NEXT: ret654;655; CHECK-LABEL: fcvtmu_ss_round_simd:656; CHECK: // %bb.0:657; CHECK-NEXT: fcvtms s0, s0658; CHECK-NEXT: ret659 %r = call float @llvm.floor.f32(float %a)660 %i = fptosi float %r to i32661 %bc = bitcast i32 %i to float662 ret float %bc663}664 665define double @fcvtmu_dd_round_simd(double %a) {666; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_round_simd:667; CHECK-NOFPRCVT: // %bb.0:668; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0669; CHECK-NOFPRCVT-NEXT: ret670;671; CHECK-LABEL: fcvtmu_dd_round_simd:672; CHECK: // %bb.0:673; CHECK-NEXT: fcvtms d0, d0674; CHECK-NEXT: ret675 %r = call double @llvm.floor.f64(double %a)676 %i = fptosi double %r to i64677 %bc = bitcast i64 %i to double678 ret double %bc679}680 681 682define double @fcvtps_ds_round_simd(float %a) {683; CHECK-NOFPRCVT-LABEL: fcvtps_ds_round_simd:684; CHECK-NOFPRCVT: // %bb.0:685; CHECK-NOFPRCVT-NEXT: fcvtps x8, s0686; CHECK-NOFPRCVT-NEXT: fmov d0, x8687; CHECK-NOFPRCVT-NEXT: ret688;689; CHECK-LABEL: fcvtps_ds_round_simd:690; CHECK: // %bb.0:691; CHECK-NEXT: fcvtps d0, s0692; CHECK-NEXT: ret693 %r = call float @llvm.ceil.f32(float %a)694 %i = fptosi float %r to i64695 %bc = bitcast i64 %i to double696 ret double %bc697}698 699define float @fcvtps_sd_round_simd(double %a) {700; CHECK-NOFPRCVT-LABEL: fcvtps_sd_round_simd:701; CHECK-NOFPRCVT: // %bb.0:702; CHECK-NOFPRCVT-NEXT: fcvtps w8, d0703; CHECK-NOFPRCVT-NEXT: fmov s0, w8704; CHECK-NOFPRCVT-NEXT: ret705;706; CHECK-LABEL: fcvtps_sd_round_simd:707; CHECK: // %bb.0:708; CHECK-NEXT: fcvtps s0, d0709; CHECK-NEXT: ret710 %r = call double @llvm.ceil.f64(double %a)711 %i = fptosi double %r to i32712 %bc = bitcast i32 %i to float713 ret float %bc714}715 716define float @fcvtps_ss_round_simd(float %a) {717; CHECK-NOFPRCVT-LABEL: fcvtps_ss_round_simd:718; CHECK-NOFPRCVT: // %bb.0:719; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0720; CHECK-NOFPRCVT-NEXT: ret721;722; CHECK-LABEL: fcvtps_ss_round_simd:723; CHECK: // %bb.0:724; CHECK-NEXT: fcvtps s0, s0725; CHECK-NEXT: ret726 %r = call float @llvm.ceil.f32(float %a)727 %i = fptosi float %r to i32728 %bc = bitcast i32 %i to float729 ret float %bc730}731 732define double @fcvtps_dd_round_simd(double %a) {733; CHECK-NOFPRCVT-LABEL: fcvtps_dd_round_simd:734; CHECK-NOFPRCVT: // %bb.0:735; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0736; CHECK-NOFPRCVT-NEXT: ret737;738; CHECK-LABEL: fcvtps_dd_round_simd:739; CHECK: // %bb.0:740; CHECK-NEXT: fcvtps d0, d0741; CHECK-NEXT: ret742 %r = call double @llvm.ceil.f64(double %a)743 %i = fptosi double %r to i64744 %bc = bitcast i64 %i to double745 ret double %bc746}747 748 749define double @fcvtpu_ds_round_simd(float %a) {750; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_round_simd:751; CHECK-NOFPRCVT: // %bb.0:752; CHECK-NOFPRCVT-NEXT: fcvtpu x8, s0753; CHECK-NOFPRCVT-NEXT: fmov d0, x8754; CHECK-NOFPRCVT-NEXT: ret755;756; CHECK-LABEL: fcvtpu_ds_round_simd:757; CHECK: // %bb.0:758; CHECK-NEXT: fcvtpu d0, s0759; CHECK-NEXT: ret760 %r = call float @llvm.ceil.f32(float %a)761 %i = fptoui float %r to i64762 %bc = bitcast i64 %i to double763 ret double %bc764}765 766define float @fcvtpu_sd_round_simd(double %a) {767; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_round_simd:768; CHECK-NOFPRCVT: // %bb.0:769; CHECK-NOFPRCVT-NEXT: fcvtpu w8, d0770; CHECK-NOFPRCVT-NEXT: fmov s0, w8771; CHECK-NOFPRCVT-NEXT: ret772;773; CHECK-LABEL: fcvtpu_sd_round_simd:774; CHECK: // %bb.0:775; CHECK-NEXT: fcvtpu s0, d0776; CHECK-NEXT: ret777 %r = call double @llvm.ceil.f64(double %a)778 %i = fptoui double %r to i32779 %bc = bitcast i32 %i to float780 ret float %bc781}782 783define float @fcvtpu_ss_round_simd(float %a) {784; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_round_simd:785; CHECK-NOFPRCVT: // %bb.0:786; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0787; CHECK-NOFPRCVT-NEXT: ret788;789; CHECK-LABEL: fcvtpu_ss_round_simd:790; CHECK: // %bb.0:791; CHECK-NEXT: fcvtps s0, s0792; CHECK-NEXT: ret793 %r = call float @llvm.ceil.f32(float %a)794 %i = fptosi float %r to i32795 %bc = bitcast i32 %i to float796 ret float %bc797}798 799define double @fcvtpu_dd_round_simd(double %a) {800; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_round_simd:801; CHECK-NOFPRCVT: // %bb.0:802; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0803; CHECK-NOFPRCVT-NEXT: ret804;805; CHECK-LABEL: fcvtpu_dd_round_simd:806; CHECK: // %bb.0:807; CHECK-NEXT: fcvtps d0, d0808; CHECK-NEXT: ret809 %r = call double @llvm.ceil.f64(double %a)810 %i = fptosi double %r to i64811 %bc = bitcast i64 %i to double812 ret double %bc813}814 815 816define double @fcvtzs_ds_round_simd(float %a) {817; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_round_simd:818; CHECK-NOFPRCVT: // %bb.0:819; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0820; CHECK-NOFPRCVT-NEXT: fmov d0, x8821; CHECK-NOFPRCVT-NEXT: ret822;823; CHECK-LABEL: fcvtzs_ds_round_simd:824; CHECK: // %bb.0:825; CHECK-NEXT: fcvtzs d0, s0826; CHECK-NEXT: ret827 %r = call float @llvm.trunc.f32(float %a)828 %i = fptosi float %r to i64829 %bc = bitcast i64 %i to double830 ret double %bc831}832 833define float @fcvtzs_sd_round_simd(double %a) {834; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_round_simd:835; CHECK-NOFPRCVT: // %bb.0:836; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0837; CHECK-NOFPRCVT-NEXT: fmov s0, w8838; CHECK-NOFPRCVT-NEXT: ret839;840; CHECK-LABEL: fcvtzs_sd_round_simd:841; CHECK: // %bb.0:842; CHECK-NEXT: fcvtzs s0, d0843; CHECK-NEXT: ret844 %r = call double @llvm.trunc.f64(double %a)845 %i = fptosi double %r to i32846 %bc = bitcast i32 %i to float847 ret float %bc848}849 850define float @fcvtzs_ss_round_simd(float %a) {851; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_round_simd:852; CHECK-NOFPRCVT: // %bb.0:853; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0854; CHECK-NOFPRCVT-NEXT: ret855;856; CHECK-LABEL: fcvtzs_ss_round_simd:857; CHECK: // %bb.0:858; CHECK-NEXT: fcvtzs s0, s0859; CHECK-NEXT: ret860 %r = call float @llvm.trunc.f32(float %a)861 %i = fptosi float %r to i32862 %bc = bitcast i32 %i to float863 ret float %bc864}865 866define double @fcvtzs_dd_round_simd(double %a) {867; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_round_simd:868; CHECK-NOFPRCVT: // %bb.0:869; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0870; CHECK-NOFPRCVT-NEXT: ret871;872; CHECK-LABEL: fcvtzs_dd_round_simd:873; CHECK: // %bb.0:874; CHECK-NEXT: fcvtzs d0, d0875; CHECK-NEXT: ret876 %r = call double @llvm.trunc.f64(double %a)877 %i = fptosi double %r to i64878 %bc = bitcast i64 %i to double879 ret double %bc880}881 882define double @fcvtzu_ds_round_simd(float %a) {883; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_round_simd:884; CHECK-NOFPRCVT: // %bb.0:885; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0886; CHECK-NOFPRCVT-NEXT: fmov d0, x8887; CHECK-NOFPRCVT-NEXT: ret888;889; CHECK-LABEL: fcvtzu_ds_round_simd:890; CHECK: // %bb.0:891; CHECK-NEXT: fcvtzu d0, s0892; CHECK-NEXT: ret893 %r = call float @llvm.trunc.f32(float %a)894 %i = fptoui float %r to i64895 %bc = bitcast i64 %i to double896 ret double %bc897}898 899define float @fcvtzu_sd_round_simd(double %a) {900; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_round_simd:901; CHECK-NOFPRCVT: // %bb.0:902; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0903; CHECK-NOFPRCVT-NEXT: fmov s0, w8904; CHECK-NOFPRCVT-NEXT: ret905;906; CHECK-LABEL: fcvtzu_sd_round_simd:907; CHECK: // %bb.0:908; CHECK-NEXT: fcvtzu s0, d0909; CHECK-NEXT: ret910 %r = call double @llvm.trunc.f64(double %a)911 %i = fptoui double %r to i32912 %bc = bitcast i32 %i to float913 ret float %bc914}915 916define float @fcvtzu_ss_round_simd(float %a) {917; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_round_simd:918; CHECK-NOFPRCVT: // %bb.0:919; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0920; CHECK-NOFPRCVT-NEXT: ret921;922; CHECK-LABEL: fcvtzu_ss_round_simd:923; CHECK: // %bb.0:924; CHECK-NEXT: fcvtzs s0, s0925; CHECK-NEXT: ret926 %r = call float @llvm.trunc.f32(float %a)927 %i = fptosi float %r to i32928 %bc = bitcast i32 %i to float929 ret float %bc930}931 932define double @fcvtzu_dd_round_simd(double %a) {933; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_round_simd:934; CHECK-NOFPRCVT: // %bb.0:935; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0936; CHECK-NOFPRCVT-NEXT: ret937;938; CHECK-LABEL: fcvtzu_dd_round_simd:939; CHECK: // %bb.0:940; CHECK-NEXT: fcvtzs d0, d0941; CHECK-NEXT: ret942 %r = call double @llvm.trunc.f64(double %a)943 %i = fptosi double %r to i64944 %bc = bitcast i64 %i to double945 ret double %bc946}947 948 949;950; FPTOI saturating951;952 953define float @fcvtzs_sh_sat_simd(half %a) {954; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_sat_simd:955; CHECK-NOFPRCVT: // %bb.0:956; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0957; CHECK-NOFPRCVT-NEXT: fmov s0, w8958; CHECK-NOFPRCVT-NEXT: ret959;960; CHECK-LABEL: fcvtzs_sh_sat_simd:961; CHECK: // %bb.0:962; CHECK-NEXT: fcvtzs s0, h0963; CHECK-NEXT: ret964 %i = call i32 @llvm.fptosi.sat.i32.f16(half %a)965 %bc = bitcast i32 %i to float966 ret float %bc967}968 969define double @fcvtzs_dh_sat_simd(half %a) {970; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_sat_simd:971; CHECK-NOFPRCVT: // %bb.0:972; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0973; CHECK-NOFPRCVT-NEXT: fmov d0, x8974; CHECK-NOFPRCVT-NEXT: ret975;976; CHECK-LABEL: fcvtzs_dh_sat_simd:977; CHECK: // %bb.0:978; CHECK-NEXT: fcvtzs d0, h0979; CHECK-NEXT: ret980 %i = call i64 @llvm.fptosi.sat.i64.f16(half %a)981 %bc = bitcast i64 %i to double982 ret double %bc983}984 985define double @fcvtzs_ds_sat_simd(float %a) {986; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_sat_simd:987; CHECK-NOFPRCVT: // %bb.0:988; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0989; CHECK-NOFPRCVT-NEXT: fmov d0, x8990; CHECK-NOFPRCVT-NEXT: ret991;992; CHECK-LABEL: fcvtzs_ds_sat_simd:993; CHECK: // %bb.0:994; CHECK-NEXT: fcvtzs d0, s0995; CHECK-NEXT: ret996 %i = call i64 @llvm.fptosi.sat.i64.f32(float %a)997 %bc = bitcast i64 %i to double998 ret double %bc999}1000 1001define float @fcvtzs_sd_sat_simd(double %a) {1002; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_sat_simd:1003; CHECK-NOFPRCVT: // %bb.0:1004; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d01005; CHECK-NOFPRCVT-NEXT: fmov s0, w81006; CHECK-NOFPRCVT-NEXT: ret1007;1008; CHECK-LABEL: fcvtzs_sd_sat_simd:1009; CHECK: // %bb.0:1010; CHECK-NEXT: fcvtzs s0, d01011; CHECK-NEXT: ret1012 %i = call i32 @llvm.fptosi.sat.i32.f64(double %a)1013 %bc = bitcast i32 %i to float1014 ret float %bc1015}1016 1017define float @fcvtzs_ss_sat_simd(float %a) {1018; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_sat_simd:1019; CHECK-NOFPRCVT: // %bb.0:1020; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s01021; CHECK-NOFPRCVT-NEXT: ret1022;1023; CHECK-LABEL: fcvtzs_ss_sat_simd:1024; CHECK: // %bb.0:1025; CHECK-NEXT: fcvtzs s0, s01026; CHECK-NEXT: ret1027 %i = call i32 @llvm.fptosi.sat.i32.f32(float %a)1028 %bc = bitcast i32 %i to float1029 ret float %bc1030}1031 1032define double @fcvtzs_dd_sat_simd(double %a) {1033; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_sat_simd:1034; CHECK-NOFPRCVT: // %bb.0:1035; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d01036; CHECK-NOFPRCVT-NEXT: ret1037;1038; CHECK-LABEL: fcvtzs_dd_sat_simd:1039; CHECK: // %bb.0:1040; CHECK-NEXT: fcvtzs d0, d01041; CHECK-NEXT: ret1042 %i = call i64 @llvm.fptosi.sat.i64.f64(double %a)1043 %bc = bitcast i64 %i to double1044 ret double %bc1045}1046 1047define float @fcvtzu_sh_sat_simd(half %a) {1048; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_sat_simd:1049; CHECK-NOFPRCVT: // %bb.0:1050; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h01051; CHECK-NOFPRCVT-NEXT: fmov s0, w81052; CHECK-NOFPRCVT-NEXT: ret1053;1054; CHECK-LABEL: fcvtzu_sh_sat_simd:1055; CHECK: // %bb.0:1056; CHECK-NEXT: fcvtzu s0, h01057; CHECK-NEXT: ret1058 %i = call i32 @llvm.fptoui.sat.i32.f16(half %a)1059 %bc = bitcast i32 %i to float1060 ret float %bc1061}1062 1063define double @fcvtzu_dh_sat_simd(half %a) {1064; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_sat_simd:1065; CHECK-NOFPRCVT: // %bb.0:1066; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h01067; CHECK-NOFPRCVT-NEXT: fmov d0, x81068; CHECK-NOFPRCVT-NEXT: ret1069;1070; CHECK-LABEL: fcvtzu_dh_sat_simd:1071; CHECK: // %bb.0:1072; CHECK-NEXT: fcvtzu d0, h01073; CHECK-NEXT: ret1074 %i = call i64 @llvm.fptoui.sat.i64.f16(half %a)1075 %bc = bitcast i64 %i to double1076 ret double %bc1077}1078 1079define double @fcvtzu_ds_sat_simd(float %a) {1080; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_sat_simd:1081; CHECK-NOFPRCVT: // %bb.0:1082; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s01083; CHECK-NOFPRCVT-NEXT: fmov d0, x81084; CHECK-NOFPRCVT-NEXT: ret1085;1086; CHECK-LABEL: fcvtzu_ds_sat_simd:1087; CHECK: // %bb.0:1088; CHECK-NEXT: fcvtzu d0, s01089; CHECK-NEXT: ret1090 %i = call i64 @llvm.fptoui.sat.i64.f32(float %a)1091 %bc = bitcast i64 %i to double1092 ret double %bc1093}1094 1095define float @fcvtzu_sd_sat_simd(double %a) {1096; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_sat_simd:1097; CHECK-NOFPRCVT: // %bb.0:1098; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d01099; CHECK-NOFPRCVT-NEXT: fmov s0, w81100; CHECK-NOFPRCVT-NEXT: ret1101;1102; CHECK-LABEL: fcvtzu_sd_sat_simd:1103; CHECK: // %bb.0:1104; CHECK-NEXT: fcvtzu s0, d01105; CHECK-NEXT: ret1106 %i = call i32 @llvm.fptoui.sat.i32.f64(double %a)1107 %bc = bitcast i32 %i to float1108 ret float %bc1109}1110 1111define float @fcvtzu_ss_sat_simd(float %a) {1112; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_sat_simd:1113; CHECK-NOFPRCVT: // %bb.0:1114; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s01115; CHECK-NOFPRCVT-NEXT: ret1116;1117; CHECK-LABEL: fcvtzu_ss_sat_simd:1118; CHECK: // %bb.0:1119; CHECK-NEXT: fcvtzs s0, s01120; CHECK-NEXT: ret1121 %i = call i32 @llvm.fptosi.sat.i32.f32(float %a)1122 %bc = bitcast i32 %i to float1123 ret float %bc1124}1125 1126define double @fcvtzu_dd_sat_simd(double %a) {1127; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_sat_simd:1128; CHECK-NOFPRCVT: // %bb.0:1129; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d01130; CHECK-NOFPRCVT-NEXT: ret1131;1132; CHECK-LABEL: fcvtzu_dd_sat_simd:1133; CHECK: // %bb.0:1134; CHECK-NEXT: fcvtzs d0, d01135; CHECK-NEXT: ret1136 %i = call i64 @llvm.fptosi.sat.i64.f64(double %a)1137 %bc = bitcast i64 %i to double1138 ret double %bc1139}1140 1141;1142; FPTOI saturating with rounding1143;1144 1145define float @fcvtas_sh_simd(half %a) {1146; CHECK-NOFPRCVT-LABEL: fcvtas_sh_simd:1147; CHECK-NOFPRCVT: // %bb.0:1148; CHECK-NOFPRCVT-NEXT: fcvtas w8, h01149; CHECK-NOFPRCVT-NEXT: fmov s0, w81150; CHECK-NOFPRCVT-NEXT: ret1151;1152; CHECK-LABEL: fcvtas_sh_simd:1153; CHECK: // %bb.0:1154; CHECK-NEXT: fcvtas s0, h01155; CHECK-NEXT: ret1156 %r = call half @llvm.round.f16(half %a) nounwind readnone1157 %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)1158 %bc = bitcast i32 %i to float1159 ret float %bc1160}1161 1162define double @fcvtas_dh_simd(half %a) {1163; CHECK-NOFPRCVT-LABEL: fcvtas_dh_simd:1164; CHECK-NOFPRCVT: // %bb.0:1165; CHECK-NOFPRCVT-NEXT: fcvtas x8, h01166; CHECK-NOFPRCVT-NEXT: fmov d0, x81167; CHECK-NOFPRCVT-NEXT: ret1168;1169; CHECK-LABEL: fcvtas_dh_simd:1170; CHECK: // %bb.0:1171; CHECK-NEXT: fcvtas d0, h01172; CHECK-NEXT: ret1173 %r = call half @llvm.round.f16(half %a) nounwind readnone1174 %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)1175 %bc = bitcast i64 %i to double1176 ret double %bc1177}1178 1179define double @fcvtas_ds_simd(float %a) {1180; CHECK-NOFPRCVT-LABEL: fcvtas_ds_simd:1181; CHECK-NOFPRCVT: // %bb.0:1182; CHECK-NOFPRCVT-NEXT: fcvtas x8, s01183; CHECK-NOFPRCVT-NEXT: fmov d0, x81184; CHECK-NOFPRCVT-NEXT: ret1185;1186; CHECK-LABEL: fcvtas_ds_simd:1187; CHECK: // %bb.0:1188; CHECK-NEXT: fcvtas d0, s01189; CHECK-NEXT: ret1190 %r = call float @llvm.round.f32(float %a)1191 %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)1192 %bc = bitcast i64 %i to double1193 ret double %bc1194}1195 1196define float @fcvtas_sd_simd(double %a) {1197; CHECK-NOFPRCVT-LABEL: fcvtas_sd_simd:1198; CHECK-NOFPRCVT: // %bb.0:1199; CHECK-NOFPRCVT-NEXT: fcvtas w8, d01200; CHECK-NOFPRCVT-NEXT: fmov s0, w81201; CHECK-NOFPRCVT-NEXT: ret1202;1203; CHECK-LABEL: fcvtas_sd_simd:1204; CHECK: // %bb.0:1205; CHECK-NEXT: fcvtas s0, d01206; CHECK-NEXT: ret1207 %r = call double @llvm.round.f64(double %a)1208 %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)1209 %bc = bitcast i32 %i to float1210 ret float %bc1211}1212 1213define float @fcvtas_ss_simd(float %a) {1214; CHECK-NOFPRCVT-LABEL: fcvtas_ss_simd:1215; CHECK-NOFPRCVT: // %bb.0:1216; CHECK-NOFPRCVT-NEXT: fcvtas s0, s01217; CHECK-NOFPRCVT-NEXT: ret1218;1219; CHECK-LABEL: fcvtas_ss_simd:1220; CHECK: // %bb.0:1221; CHECK-NEXT: fcvtas s0, s01222; CHECK-NEXT: ret1223 %r = call float @llvm.round.f32(float %a)1224 %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)1225 %bc = bitcast i32 %i to float1226 ret float %bc1227}1228 1229define double @fcvtas_dd_simd(double %a) {1230; CHECK-NOFPRCVT-LABEL: fcvtas_dd_simd:1231; CHECK-NOFPRCVT: // %bb.0:1232; CHECK-NOFPRCVT-NEXT: fcvtas d0, d01233; CHECK-NOFPRCVT-NEXT: ret1234;1235; CHECK-LABEL: fcvtas_dd_simd:1236; CHECK: // %bb.0:1237; CHECK-NEXT: fcvtas d0, d01238; CHECK-NEXT: ret1239 %r = call double @llvm.round.f64(double %a)1240 %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)1241 %bc = bitcast i64 %i to double1242 ret double %bc1243}1244 1245define float @fcvtau_sh_simd(half %a) {1246; CHECK-NOFPRCVT-LABEL: fcvtau_sh_simd:1247; CHECK-NOFPRCVT: // %bb.0:1248; CHECK-NOFPRCVT-NEXT: fcvtau w8, h01249; CHECK-NOFPRCVT-NEXT: fmov s0, w81250; CHECK-NOFPRCVT-NEXT: ret1251;1252; CHECK-LABEL: fcvtau_sh_simd:1253; CHECK: // %bb.0:1254; CHECK-NEXT: fcvtau s0, h01255; CHECK-NEXT: ret1256 %r = call half @llvm.round.f16(half %a) nounwind readnone1257 %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)1258 %bc = bitcast i32 %i to float1259 ret float %bc1260}1261 1262define double @fcvtau_dh_simd(half %a) {1263; CHECK-NOFPRCVT-LABEL: fcvtau_dh_simd:1264; CHECK-NOFPRCVT: // %bb.0:1265; CHECK-NOFPRCVT-NEXT: fcvtau x8, h01266; CHECK-NOFPRCVT-NEXT: fmov d0, x81267; CHECK-NOFPRCVT-NEXT: ret1268;1269; CHECK-LABEL: fcvtau_dh_simd:1270; CHECK: // %bb.0:1271; CHECK-NEXT: fcvtau d0, h01272; CHECK-NEXT: ret1273 %r = call half @llvm.round.f16(half %a) nounwind readnone1274 %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)1275 %bc = bitcast i64 %i to double1276 ret double %bc1277}1278 1279define double @fcvtau_ds_simd(float %a) {1280; CHECK-NOFPRCVT-LABEL: fcvtau_ds_simd:1281; CHECK-NOFPRCVT: // %bb.0:1282; CHECK-NOFPRCVT-NEXT: fcvtau x8, s01283; CHECK-NOFPRCVT-NEXT: fmov d0, x81284; CHECK-NOFPRCVT-NEXT: ret1285;1286; CHECK-LABEL: fcvtau_ds_simd:1287; CHECK: // %bb.0:1288; CHECK-NEXT: fcvtau d0, s01289; CHECK-NEXT: ret1290 %r = call float @llvm.round.f32(float %a)1291 %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)1292 %bc = bitcast i64 %i to double1293 ret double %bc1294}1295 1296define float @fcvtau_sd_simd(double %a) {1297; CHECK-NOFPRCVT-LABEL: fcvtau_sd_simd:1298; CHECK-NOFPRCVT: // %bb.0:1299; CHECK-NOFPRCVT-NEXT: fcvtau w8, d01300; CHECK-NOFPRCVT-NEXT: fmov s0, w81301; CHECK-NOFPRCVT-NEXT: ret1302;1303; CHECK-LABEL: fcvtau_sd_simd:1304; CHECK: // %bb.0:1305; CHECK-NEXT: fcvtau s0, d01306; CHECK-NEXT: ret1307 %r = call double @llvm.round.f64(double %a)1308 %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)1309 %bc = bitcast i32 %i to float1310 ret float %bc1311}1312 1313define float @fcvtau_ss_simd(float %a) {1314; CHECK-NOFPRCVT-LABEL: fcvtau_ss_simd:1315; CHECK-NOFPRCVT: // %bb.0:1316; CHECK-NOFPRCVT-NEXT: fcvtas s0, s01317; CHECK-NOFPRCVT-NEXT: ret1318;1319; CHECK-LABEL: fcvtau_ss_simd:1320; CHECK: // %bb.0:1321; CHECK-NEXT: fcvtas s0, s01322; CHECK-NEXT: ret1323 %r = call float @llvm.round.f32(float %a)1324 %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)1325 %bc = bitcast i32 %i to float1326 ret float %bc1327}1328 1329define double @fcvtau_dd_simd(double %a) {1330; CHECK-NOFPRCVT-LABEL: fcvtau_dd_simd:1331; CHECK-NOFPRCVT: // %bb.0:1332; CHECK-NOFPRCVT-NEXT: fcvtas d0, d01333; CHECK-NOFPRCVT-NEXT: ret1334;1335; CHECK-LABEL: fcvtau_dd_simd:1336; CHECK: // %bb.0:1337; CHECK-NEXT: fcvtas d0, d01338; CHECK-NEXT: ret1339 %r = call double @llvm.round.f64(double %a)1340 %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)1341 %bc = bitcast i64 %i to double1342 ret double %bc1343}1344 1345define float @fcvtms_sh_simd(half %a) {1346; CHECK-NOFPRCVT-LABEL: fcvtms_sh_simd:1347; CHECK-NOFPRCVT: // %bb.0:1348; CHECK-NOFPRCVT-NEXT: fcvtms w8, h01349; CHECK-NOFPRCVT-NEXT: fmov s0, w81350; CHECK-NOFPRCVT-NEXT: ret1351;1352; CHECK-LABEL: fcvtms_sh_simd:1353; CHECK: // %bb.0:1354; CHECK-NEXT: fcvtms s0, h01355; CHECK-NEXT: ret1356 %r = call half @llvm.floor.f16(half %a) nounwind readnone1357 %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)1358 %bc = bitcast i32 %i to float1359 ret float %bc1360}1361 1362define double @fcvtms_dh_simd(half %a) {1363; CHECK-NOFPRCVT-LABEL: fcvtms_dh_simd:1364; CHECK-NOFPRCVT: // %bb.0:1365; CHECK-NOFPRCVT-NEXT: fcvtms x8, h01366; CHECK-NOFPRCVT-NEXT: fmov d0, x81367; CHECK-NOFPRCVT-NEXT: ret1368;1369; CHECK-LABEL: fcvtms_dh_simd:1370; CHECK: // %bb.0:1371; CHECK-NEXT: fcvtms d0, h01372; CHECK-NEXT: ret1373 %r = call half @llvm.floor.f16(half %a) nounwind readnone1374 %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)1375 %bc = bitcast i64 %i to double1376 ret double %bc1377}1378 1379define double @fcvtms_ds_simd(float %a) {1380; CHECK-NOFPRCVT-LABEL: fcvtms_ds_simd:1381; CHECK-NOFPRCVT: // %bb.0:1382; CHECK-NOFPRCVT-NEXT: fcvtms x8, s01383; CHECK-NOFPRCVT-NEXT: fmov d0, x81384; CHECK-NOFPRCVT-NEXT: ret1385;1386; CHECK-LABEL: fcvtms_ds_simd:1387; CHECK: // %bb.0:1388; CHECK-NEXT: fcvtms d0, s01389; CHECK-NEXT: ret1390 %r = call float @llvm.floor.f32(float %a)1391 %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)1392 %bc = bitcast i64 %i to double1393 ret double %bc1394}1395 1396define float @fcvtms_sd_simd(double %a) {1397; CHECK-NOFPRCVT-LABEL: fcvtms_sd_simd:1398; CHECK-NOFPRCVT: // %bb.0:1399; CHECK-NOFPRCVT-NEXT: fcvtms w8, d01400; CHECK-NOFPRCVT-NEXT: fmov s0, w81401; CHECK-NOFPRCVT-NEXT: ret1402;1403; CHECK-LABEL: fcvtms_sd_simd:1404; CHECK: // %bb.0:1405; CHECK-NEXT: fcvtms s0, d01406; CHECK-NEXT: ret1407 %r = call double @llvm.floor.f64(double %a)1408 %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)1409 %bc = bitcast i32 %i to float1410 ret float %bc1411}1412 1413define float @fcvtms_ss_simd(float %a) {1414; CHECK-NOFPRCVT-LABEL: fcvtms_ss_simd:1415; CHECK-NOFPRCVT: // %bb.0:1416; CHECK-NOFPRCVT-NEXT: fcvtms s0, s01417; CHECK-NOFPRCVT-NEXT: ret1418;1419; CHECK-LABEL: fcvtms_ss_simd:1420; CHECK: // %bb.0:1421; CHECK-NEXT: fcvtms s0, s01422; CHECK-NEXT: ret1423 %r = call float @llvm.floor.f32(float %a)1424 %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)1425 %bc = bitcast i32 %i to float1426 ret float %bc1427}1428 1429define double @fcvtms_dd_simd(double %a) {1430; CHECK-NOFPRCVT-LABEL: fcvtms_dd_simd:1431; CHECK-NOFPRCVT: // %bb.0:1432; CHECK-NOFPRCVT-NEXT: fcvtms d0, d01433; CHECK-NOFPRCVT-NEXT: ret1434;1435; CHECK-LABEL: fcvtms_dd_simd:1436; CHECK: // %bb.0:1437; CHECK-NEXT: fcvtms d0, d01438; CHECK-NEXT: ret1439 %r = call double @llvm.floor.f64(double %a)1440 %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)1441 %bc = bitcast i64 %i to double1442 ret double %bc1443}1444 1445define float @fcvtmu_sh_simd(half %a) {1446; CHECK-NOFPRCVT-LABEL: fcvtmu_sh_simd:1447; CHECK-NOFPRCVT: // %bb.0:1448; CHECK-NOFPRCVT-NEXT: fcvtmu w8, h01449; CHECK-NOFPRCVT-NEXT: fmov s0, w81450; CHECK-NOFPRCVT-NEXT: ret1451;1452; CHECK-LABEL: fcvtmu_sh_simd:1453; CHECK: // %bb.0:1454; CHECK-NEXT: fcvtmu s0, h01455; CHECK-NEXT: ret1456 %r = call half @llvm.floor.f16(half %a) nounwind readnone1457 %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)1458 %bc = bitcast i32 %i to float1459 ret float %bc1460}1461 1462define double @fcvtmu_dh_simd(half %a) {1463; CHECK-NOFPRCVT-LABEL: fcvtmu_dh_simd:1464; CHECK-NOFPRCVT: // %bb.0:1465; CHECK-NOFPRCVT-NEXT: fcvtmu x8, h01466; CHECK-NOFPRCVT-NEXT: fmov d0, x81467; CHECK-NOFPRCVT-NEXT: ret1468;1469; CHECK-LABEL: fcvtmu_dh_simd:1470; CHECK: // %bb.0:1471; CHECK-NEXT: fcvtmu d0, h01472; CHECK-NEXT: ret1473 %r = call half @llvm.floor.f16(half %a) nounwind readnone1474 %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)1475 %bc = bitcast i64 %i to double1476 ret double %bc1477}1478 1479define double @fcvtmu_ds_simd(float %a) {1480; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_simd:1481; CHECK-NOFPRCVT: // %bb.0:1482; CHECK-NOFPRCVT-NEXT: fcvtmu x8, s01483; CHECK-NOFPRCVT-NEXT: fmov d0, x81484; CHECK-NOFPRCVT-NEXT: ret1485;1486; CHECK-LABEL: fcvtmu_ds_simd:1487; CHECK: // %bb.0:1488; CHECK-NEXT: fcvtmu d0, s01489; CHECK-NEXT: ret1490 %r = call float @llvm.floor.f32(float %a)1491 %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)1492 %bc = bitcast i64 %i to double1493 ret double %bc1494}1495 1496define float @fcvtmu_sd_simd(double %a) {1497; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_simd:1498; CHECK-NOFPRCVT: // %bb.0:1499; CHECK-NOFPRCVT-NEXT: fcvtmu w8, d01500; CHECK-NOFPRCVT-NEXT: fmov s0, w81501; CHECK-NOFPRCVT-NEXT: ret1502;1503; CHECK-LABEL: fcvtmu_sd_simd:1504; CHECK: // %bb.0:1505; CHECK-NEXT: fcvtmu s0, d01506; CHECK-NEXT: ret1507 %r = call double @llvm.floor.f64(double %a)1508 %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)1509 %bc = bitcast i32 %i to float1510 ret float %bc1511}1512 1513define float @fcvtmu_ss_simd(float %a) {1514; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_simd:1515; CHECK-NOFPRCVT: // %bb.0:1516; CHECK-NOFPRCVT-NEXT: fcvtms s0, s01517; CHECK-NOFPRCVT-NEXT: ret1518;1519; CHECK-LABEL: fcvtmu_ss_simd:1520; CHECK: // %bb.0:1521; CHECK-NEXT: fcvtms s0, s01522; CHECK-NEXT: ret1523 %r = call float @llvm.floor.f32(float %a)1524 %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)1525 %bc = bitcast i32 %i to float1526 ret float %bc1527}1528 1529define double @fcvtmu_dd_simd(double %a) {1530; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_simd:1531; CHECK-NOFPRCVT: // %bb.0:1532; CHECK-NOFPRCVT-NEXT: fcvtms d0, d01533; CHECK-NOFPRCVT-NEXT: ret1534;1535; CHECK-LABEL: fcvtmu_dd_simd:1536; CHECK: // %bb.0:1537; CHECK-NEXT: fcvtms d0, d01538; CHECK-NEXT: ret1539 %r = call double @llvm.floor.f64(double %a)1540 %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)1541 %bc = bitcast i64 %i to double1542 ret double %bc1543}1544 1545define float @fcvtps_sh_simd(half %a) {1546; CHECK-NOFPRCVT-LABEL: fcvtps_sh_simd:1547; CHECK-NOFPRCVT: // %bb.0:1548; CHECK-NOFPRCVT-NEXT: fcvtps w8, h01549; CHECK-NOFPRCVT-NEXT: fmov s0, w81550; CHECK-NOFPRCVT-NEXT: ret1551;1552; CHECK-LABEL: fcvtps_sh_simd:1553; CHECK: // %bb.0:1554; CHECK-NEXT: fcvtps s0, h01555; CHECK-NEXT: ret1556 %r = call half @llvm.ceil.f16(half %a) nounwind readnone1557 %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)1558 %bc = bitcast i32 %i to float1559 ret float %bc1560}1561 1562define double @fcvtps_dh_simd(half %a) {1563; CHECK-NOFPRCVT-LABEL: fcvtps_dh_simd:1564; CHECK-NOFPRCVT: // %bb.0:1565; CHECK-NOFPRCVT-NEXT: fcvtps x8, h01566; CHECK-NOFPRCVT-NEXT: fmov d0, x81567; CHECK-NOFPRCVT-NEXT: ret1568;1569; CHECK-LABEL: fcvtps_dh_simd:1570; CHECK: // %bb.0:1571; CHECK-NEXT: fcvtps d0, h01572; CHECK-NEXT: ret1573 %r = call half @llvm.ceil.f16(half %a) nounwind readnone1574 %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)1575 %bc = bitcast i64 %i to double1576 ret double %bc1577}1578 1579define double @fcvtps_ds_simd(float %a) {1580; CHECK-NOFPRCVT-LABEL: fcvtps_ds_simd:1581; CHECK-NOFPRCVT: // %bb.0:1582; CHECK-NOFPRCVT-NEXT: fcvtps x8, s01583; CHECK-NOFPRCVT-NEXT: fmov d0, x81584; CHECK-NOFPRCVT-NEXT: ret1585;1586; CHECK-LABEL: fcvtps_ds_simd:1587; CHECK: // %bb.0:1588; CHECK-NEXT: fcvtps d0, s01589; CHECK-NEXT: ret1590 %r = call float @llvm.ceil.f32(float %a)1591 %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)1592 %bc = bitcast i64 %i to double1593 ret double %bc1594}1595 1596define float @fcvtps_sd_simd(double %a) {1597; CHECK-NOFPRCVT-LABEL: fcvtps_sd_simd:1598; CHECK-NOFPRCVT: // %bb.0:1599; CHECK-NOFPRCVT-NEXT: fcvtps w8, d01600; CHECK-NOFPRCVT-NEXT: fmov s0, w81601; CHECK-NOFPRCVT-NEXT: ret1602;1603; CHECK-LABEL: fcvtps_sd_simd:1604; CHECK: // %bb.0:1605; CHECK-NEXT: fcvtps s0, d01606; CHECK-NEXT: ret1607 %r = call double @llvm.ceil.f64(double %a)1608 %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)1609 %bc = bitcast i32 %i to float1610 ret float %bc1611}1612 1613define float @fcvtps_ss_simd(float %a) {1614; CHECK-NOFPRCVT-LABEL: fcvtps_ss_simd:1615; CHECK-NOFPRCVT: // %bb.0:1616; CHECK-NOFPRCVT-NEXT: fcvtps s0, s01617; CHECK-NOFPRCVT-NEXT: ret1618;1619; CHECK-LABEL: fcvtps_ss_simd:1620; CHECK: // %bb.0:1621; CHECK-NEXT: fcvtps s0, s01622; CHECK-NEXT: ret1623 %r = call float @llvm.ceil.f32(float %a)1624 %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)1625 %bc = bitcast i32 %i to float1626 ret float %bc1627}1628 1629define double @fcvtps_dd_simd(double %a) {1630; CHECK-NOFPRCVT-LABEL: fcvtps_dd_simd:1631; CHECK-NOFPRCVT: // %bb.0:1632; CHECK-NOFPRCVT-NEXT: fcvtps d0, d01633; CHECK-NOFPRCVT-NEXT: ret1634;1635; CHECK-LABEL: fcvtps_dd_simd:1636; CHECK: // %bb.0:1637; CHECK-NEXT: fcvtps d0, d01638; CHECK-NEXT: ret1639 %r = call double @llvm.ceil.f64(double %a)1640 %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)1641 %bc = bitcast i64 %i to double1642 ret double %bc1643}1644 1645define float @fcvtpu_sh_simd(half %a) {1646; CHECK-NOFPRCVT-LABEL: fcvtpu_sh_simd:1647; CHECK-NOFPRCVT: // %bb.0:1648; CHECK-NOFPRCVT-NEXT: fcvtpu w8, h01649; CHECK-NOFPRCVT-NEXT: fmov s0, w81650; CHECK-NOFPRCVT-NEXT: ret1651;1652; CHECK-LABEL: fcvtpu_sh_simd:1653; CHECK: // %bb.0:1654; CHECK-NEXT: fcvtpu s0, h01655; CHECK-NEXT: ret1656 %r = call half @llvm.ceil.f16(half %a) nounwind readnone1657 %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)1658 %bc = bitcast i32 %i to float1659 ret float %bc1660}1661 1662define double @fcvtpu_dh_simd(half %a) {1663; CHECK-NOFPRCVT-LABEL: fcvtpu_dh_simd:1664; CHECK-NOFPRCVT: // %bb.0:1665; CHECK-NOFPRCVT-NEXT: fcvtpu x8, h01666; CHECK-NOFPRCVT-NEXT: fmov d0, x81667; CHECK-NOFPRCVT-NEXT: ret1668;1669; CHECK-LABEL: fcvtpu_dh_simd:1670; CHECK: // %bb.0:1671; CHECK-NEXT: fcvtpu d0, h01672; CHECK-NEXT: ret1673 %r = call half @llvm.ceil.f16(half %a) nounwind readnone1674 %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)1675 %bc = bitcast i64 %i to double1676 ret double %bc1677}1678 1679define double @fcvtpu_ds_simd(float %a) {1680; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_simd:1681; CHECK-NOFPRCVT: // %bb.0:1682; CHECK-NOFPRCVT-NEXT: fcvtpu x8, s01683; CHECK-NOFPRCVT-NEXT: fmov d0, x81684; CHECK-NOFPRCVT-NEXT: ret1685;1686; CHECK-LABEL: fcvtpu_ds_simd:1687; CHECK: // %bb.0:1688; CHECK-NEXT: fcvtpu d0, s01689; CHECK-NEXT: ret1690 %r = call float @llvm.ceil.f32(float %a)1691 %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)1692 %bc = bitcast i64 %i to double1693 ret double %bc1694}1695 1696define float @fcvtpu_sd_simd(double %a) {1697; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_simd:1698; CHECK-NOFPRCVT: // %bb.0:1699; CHECK-NOFPRCVT-NEXT: fcvtpu w8, d01700; CHECK-NOFPRCVT-NEXT: fmov s0, w81701; CHECK-NOFPRCVT-NEXT: ret1702;1703; CHECK-LABEL: fcvtpu_sd_simd:1704; CHECK: // %bb.0:1705; CHECK-NEXT: fcvtpu s0, d01706; CHECK-NEXT: ret1707 %r = call double @llvm.ceil.f64(double %a)1708 %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)1709 %bc = bitcast i32 %i to float1710 ret float %bc1711}1712 1713define float @fcvtpu_ss_simd(float %a) {1714; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_simd:1715; CHECK-NOFPRCVT: // %bb.0:1716; CHECK-NOFPRCVT-NEXT: fcvtps s0, s01717; CHECK-NOFPRCVT-NEXT: ret1718;1719; CHECK-LABEL: fcvtpu_ss_simd:1720; CHECK: // %bb.0:1721; CHECK-NEXT: fcvtps s0, s01722; CHECK-NEXT: ret1723 %r = call float @llvm.ceil.f32(float %a)1724 %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)1725 %bc = bitcast i32 %i to float1726 ret float %bc1727}1728 1729define double @fcvtpu_dd_simd(double %a) {1730; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_simd:1731; CHECK-NOFPRCVT: // %bb.0:1732; CHECK-NOFPRCVT-NEXT: fcvtps d0, d01733; CHECK-NOFPRCVT-NEXT: ret1734;1735; CHECK-LABEL: fcvtpu_dd_simd:1736; CHECK: // %bb.0:1737; CHECK-NEXT: fcvtps d0, d01738; CHECK-NEXT: ret1739 %r = call double @llvm.ceil.f64(double %a)1740 %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)1741 %bc = bitcast i64 %i to double1742 ret double %bc1743}1744 1745define float @fcvtzs_sh_simd(half %a) {1746; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_simd:1747; CHECK-NOFPRCVT: // %bb.0:1748; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h01749; CHECK-NOFPRCVT-NEXT: fmov s0, w81750; CHECK-NOFPRCVT-NEXT: ret1751;1752; CHECK-LABEL: fcvtzs_sh_simd:1753; CHECK: // %bb.0:1754; CHECK-NEXT: fcvtzs s0, h01755; CHECK-NEXT: ret1756 %r = call half @llvm.trunc.f16(half %a) nounwind readnone1757 %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)1758 %bc = bitcast i32 %i to float1759 ret float %bc1760}1761 1762define double @fcvtzs_dh_simd(half %a) {1763; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_simd:1764; CHECK-NOFPRCVT: // %bb.0:1765; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h01766; CHECK-NOFPRCVT-NEXT: fmov d0, x81767; CHECK-NOFPRCVT-NEXT: ret1768;1769; CHECK-LABEL: fcvtzs_dh_simd:1770; CHECK: // %bb.0:1771; CHECK-NEXT: fcvtzs d0, h01772; CHECK-NEXT: ret1773 %r = call half @llvm.trunc.f16(half %a) nounwind readnone1774 %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)1775 %bc = bitcast i64 %i to double1776 ret double %bc1777}1778 1779define double @fcvtzs_ds_simd(float %a) {1780; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_simd:1781; CHECK-NOFPRCVT: // %bb.0:1782; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s01783; CHECK-NOFPRCVT-NEXT: fmov d0, x81784; CHECK-NOFPRCVT-NEXT: ret1785;1786; CHECK-LABEL: fcvtzs_ds_simd:1787; CHECK: // %bb.0:1788; CHECK-NEXT: fcvtzs d0, s01789; CHECK-NEXT: ret1790 %r = call float @llvm.trunc.f32(float %a)1791 %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)1792 %bc = bitcast i64 %i to double1793 ret double %bc1794}1795 1796define float @fcvtzs_sd_simd(double %a) {1797; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_simd:1798; CHECK-NOFPRCVT: // %bb.0:1799; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d01800; CHECK-NOFPRCVT-NEXT: fmov s0, w81801; CHECK-NOFPRCVT-NEXT: ret1802;1803; CHECK-LABEL: fcvtzs_sd_simd:1804; CHECK: // %bb.0:1805; CHECK-NEXT: fcvtzs s0, d01806; CHECK-NEXT: ret1807 %r = call double @llvm.trunc.f64(double %a)1808 %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)1809 %bc = bitcast i32 %i to float1810 ret float %bc1811}1812 1813define float @fcvtzs_ss_simd(float %a) {1814; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_simd:1815; CHECK-NOFPRCVT: // %bb.0:1816; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s01817; CHECK-NOFPRCVT-NEXT: ret1818;1819; CHECK-LABEL: fcvtzs_ss_simd:1820; CHECK: // %bb.0:1821; CHECK-NEXT: fcvtzs s0, s01822; CHECK-NEXT: ret1823 %r = call float @llvm.trunc.f32(float %a)1824 %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)1825 %bc = bitcast i32 %i to float1826 ret float %bc1827}1828 1829define double @fcvtzs_dd_simd(double %a) {1830; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_simd:1831; CHECK-NOFPRCVT: // %bb.0:1832; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d01833; CHECK-NOFPRCVT-NEXT: ret1834;1835; CHECK-LABEL: fcvtzs_dd_simd:1836; CHECK: // %bb.0:1837; CHECK-NEXT: fcvtzs d0, d01838; CHECK-NEXT: ret1839 %r = call double @llvm.trunc.f64(double %a)1840 %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)1841 %bc = bitcast i64 %i to double1842 ret double %bc1843}1844 1845define float @fcvtzu_sh_simd(half %a) {1846; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_simd:1847; CHECK-NOFPRCVT: // %bb.0:1848; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h01849; CHECK-NOFPRCVT-NEXT: fmov s0, w81850; CHECK-NOFPRCVT-NEXT: ret1851;1852; CHECK-LABEL: fcvtzu_sh_simd:1853; CHECK: // %bb.0:1854; CHECK-NEXT: fcvtzu s0, h01855; CHECK-NEXT: ret1856 %r = call half @llvm.trunc.f16(half %a) nounwind readnone1857 %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)1858 %bc = bitcast i32 %i to float1859 ret float %bc1860}1861 1862define double @fcvtzu_dh_simd(half %a) {1863; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_simd:1864; CHECK-NOFPRCVT: // %bb.0:1865; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h01866; CHECK-NOFPRCVT-NEXT: fmov d0, x81867; CHECK-NOFPRCVT-NEXT: ret1868;1869; CHECK-LABEL: fcvtzu_dh_simd:1870; CHECK: // %bb.0:1871; CHECK-NEXT: fcvtzu d0, h01872; CHECK-NEXT: ret1873 %r = call half @llvm.trunc.f16(half %a) nounwind readnone1874 %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)1875 %bc = bitcast i64 %i to double1876 ret double %bc1877}1878 1879define double @fcvtzu_ds_simd(float %a) {1880; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_simd:1881; CHECK-NOFPRCVT: // %bb.0:1882; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s01883; CHECK-NOFPRCVT-NEXT: fmov d0, x81884; CHECK-NOFPRCVT-NEXT: ret1885;1886; CHECK-LABEL: fcvtzu_ds_simd:1887; CHECK: // %bb.0:1888; CHECK-NEXT: fcvtzu d0, s01889; CHECK-NEXT: ret1890 %r = call float @llvm.trunc.f32(float %a)1891 %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)1892 %bc = bitcast i64 %i to double1893 ret double %bc1894}1895 1896define float @fcvtzu_sd_simd(double %a) {1897; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_simd:1898; CHECK-NOFPRCVT: // %bb.0:1899; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d01900; CHECK-NOFPRCVT-NEXT: fmov s0, w81901; CHECK-NOFPRCVT-NEXT: ret1902;1903; CHECK-LABEL: fcvtzu_sd_simd:1904; CHECK: // %bb.0:1905; CHECK-NEXT: fcvtzu s0, d01906; CHECK-NEXT: ret1907 %r = call double @llvm.trunc.f64(double %a)1908 %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)1909 %bc = bitcast i32 %i to float1910 ret float %bc1911}1912 1913define float @fcvtzu_ss_simd(float %a) {1914; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_simd:1915; CHECK-NOFPRCVT: // %bb.0:1916; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s01917; CHECK-NOFPRCVT-NEXT: ret1918;1919; CHECK-LABEL: fcvtzu_ss_simd:1920; CHECK: // %bb.0:1921; CHECK-NEXT: fcvtzu s0, s01922; CHECK-NEXT: ret1923 %r = call float @llvm.trunc.f32(float %a)1924 %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)1925 %bc = bitcast i32 %i to float1926 ret float %bc1927}1928 1929define double @fcvtzu_dd_simd(double %a) {1930; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_simd:1931; CHECK-NOFPRCVT: // %bb.0:1932; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d01933; CHECK-NOFPRCVT-NEXT: ret1934;1935; CHECK-LABEL: fcvtzu_dd_simd:1936; CHECK: // %bb.0:1937; CHECK-NEXT: fcvtzu d0, d01938; CHECK-NEXT: ret1939 %r = call double @llvm.trunc.f64(double %a)1940 %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)1941 %bc = bitcast i64 %i to double1942 ret double %bc1943}1944