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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK3; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK4 5 6;7; Intriniscs8;9 10define float @fcvtas_1s1d_simd(double %A) nounwind {11; CHECK-LABEL: fcvtas_1s1d_simd:12; CHECK: // %bb.0:13; CHECK-NEXT: fcvtas s0, d014; CHECK-NEXT: ret15 %i = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)16 %f = bitcast i32 %i to float17 ret float %f18}19 20define double @fcvtas_1d1s_simd(float %A) nounwind {21; CHECK-LABEL: fcvtas_1d1s_simd:22; CHECK: // %bb.0:23; CHECK-NEXT: fcvtas d0, s024; CHECK-NEXT: ret25 %i = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)26 %d = bitcast i64 %i to double27 ret double %d28}29 30define float @fcvtas_1s1h_simd(half %a) {31; CHECK-LABEL: fcvtas_1s1h_simd:32; CHECK: // %bb.0:33; CHECK-NEXT: fcvtas s0, h034; CHECK-NEXT: ret35 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f16(half %a)36 %f = bitcast i32 %fcvt to float37 ret float %f38}39 40define double @fcvtas_1d1h_simd(half %a) {41; CHECK-LABEL: fcvtas_1d1h_simd:42; CHECK: // %bb.0:43; CHECK-NEXT: fcvtas d0, h044; CHECK-NEXT: ret45 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f16(half %a)46 %d = bitcast i64 %vcvtah_s64_f16 to double47 ret double %d48}49 50define double @fcvtas_1d1d_simd(double %a) {51; CHECK-LABEL: fcvtas_1d1d_simd:52; CHECK: // %bb.0:53; CHECK-NEXT: fcvtas d0, d054; CHECK-NEXT: ret55 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %a)56 %d = bitcast i64 %vcvtah_s64_f64 to double57 ret double %d58}59 60define float @fcvtas_1s1s_simd(float %a) {61; CHECK-LABEL: fcvtas_1s1s_simd:62; CHECK: // %bb.0:63; CHECK-NEXT: fcvtas s0, s064; CHECK-NEXT: ret65 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %a)66 %d = bitcast i32 %vcvtah_s32_f32 to float67 ret float %d68}69 70 71define float @fcvtau_1s1d_simd(double %A) nounwind {72; CHECK-LABEL: fcvtau_1s1d_simd:73; CHECK: // %bb.0:74; CHECK-NEXT: fcvtau s0, d075; CHECK-NEXT: ret76 %i = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)77 %f = bitcast i32 %i to float78 ret float %f79}80 81define double @fcvtau_1d1s_simd(float %A) nounwind {82; CHECK-LABEL: fcvtau_1d1s_simd:83; CHECK: // %bb.0:84; CHECK-NEXT: fcvtau d0, s085; CHECK-NEXT: ret86 %i = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)87 %d = bitcast i64 %i to double88 ret double %d89}90 91define float @fcvtau_1s1h_simd(half %a) {92; CHECK-LABEL: fcvtau_1s1h_simd:93; CHECK: // %bb.0:94; CHECK-NEXT: fcvtau s0, h095; CHECK-NEXT: ret96 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f16(half %a)97 %f = bitcast i32 %fcvt to float98 ret float %f99}100 101define double @fcvtau_1d1h_simd(half %a) {102; CHECK-LABEL: fcvtau_1d1h_simd:103; CHECK: // %bb.0:104; CHECK-NEXT: fcvtau d0, h0105; CHECK-NEXT: ret106 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f16(half %a)107 %d = bitcast i64 %vcvtah_s64_f16 to double108 ret double %d109}110 111define double @fcvtau_1d1d_simd(double %a) {112; CHECK-LABEL: fcvtau_1d1d_simd:113; CHECK: // %bb.0:114; CHECK-NEXT: fcvtau d0, d0115; CHECK-NEXT: ret116 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %a)117 %d = bitcast i64 %vcvtah_s64_f64 to double118 ret double %d119}120 121define float @fcvtau_1s1s_simd(float %a) {122; CHECK-LABEL: fcvtau_1s1s_simd:123; CHECK: // %bb.0:124; CHECK-NEXT: fcvtau s0, s0125; CHECK-NEXT: ret126 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %a)127 %d = bitcast i32 %vcvtah_s32_f32 to float128 ret float %d129}130 131define float @fcvtms_1s1d_simd(double %A) nounwind {132; CHECK-LABEL: fcvtms_1s1d_simd:133; CHECK: // %bb.0:134; CHECK-NEXT: fcvtms s0, d0135; CHECK-NEXT: ret136 %i = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double %A)137 %f = bitcast i32 %i to float138 ret float %f139}140 141define double @fcvtms_1d1s_simd(float %A) nounwind {142; CHECK-LABEL: fcvtms_1d1s_simd:143; CHECK: // %bb.0:144; CHECK-NEXT: fcvtms d0, s0145; CHECK-NEXT: ret146 %i = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float %A)147 %d = bitcast i64 %i to double148 ret double %d149}150 151define float @fcvtms_1s1h_simd(half %a) {152; CHECK-LABEL: fcvtms_1s1h_simd:153; CHECK: // %bb.0:154; CHECK-NEXT: fcvtms s0, h0155; CHECK-NEXT: ret156 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtms.i32.f16(half %a)157 %f = bitcast i32 %fcvt to float158 ret float %f159}160 161define double @fcvtms_1d1h_simd(half %a) {162; CHECK-LABEL: fcvtms_1d1h_simd:163; CHECK: // %bb.0:164; CHECK-NEXT: fcvtms d0, h0165; CHECK-NEXT: ret166 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f16(half %a)167 %d = bitcast i64 %vcvtah_s64_f16 to double168 ret double %d169}170 171define double @fcvtms_1d1d_simd(double %a) {172; CHECK-LABEL: fcvtms_1d1d_simd:173; CHECK: // %bb.0:174; CHECK-NEXT: fcvtms d0, d0175; CHECK-NEXT: ret176 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %a)177 %d = bitcast i64 %vcvtah_s64_f64 to double178 ret double %d179}180 181define float @fcvtms_1s1s_simd(float %a) {182; CHECK-LABEL: fcvtms_1s1s_simd:183; CHECK: // %bb.0:184; CHECK-NEXT: fcvtms s0, s0185; CHECK-NEXT: ret186 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %a)187 %d = bitcast i32 %vcvtah_s32_f32 to float188 ret float %d189}190 191define float @fcvtmu_1s1d_simd(double %A) nounwind {192; CHECK-LABEL: fcvtmu_1s1d_simd:193; CHECK: // %bb.0:194; CHECK-NEXT: fcvtmu s0, d0195; CHECK-NEXT: ret196 %i = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double %A)197 %f = bitcast i32 %i to float198 ret float %f199}200 201define double @fcvtmu_1d1s_simd(float %A) nounwind {202; CHECK-LABEL: fcvtmu_1d1s_simd:203; CHECK: // %bb.0:204; CHECK-NEXT: fcvtmu d0, s0205; CHECK-NEXT: ret206 %i = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float %A)207 %d = bitcast i64 %i to double208 ret double %d209}210 211define float @fcvtmu_1s1h_simd(half %a) {212; CHECK-LABEL: fcvtmu_1s1h_simd:213; CHECK: // %bb.0:214; CHECK-NEXT: fcvtmu s0, h0215; CHECK-NEXT: ret216 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half %a)217 %f = bitcast i32 %fcvt to float218 ret float %f219}220 221define double @fcvtmu_1d1h_simd(half %a) {222; CHECK-LABEL: fcvtmu_1d1h_simd:223; CHECK: // %bb.0:224; CHECK-NEXT: fcvtmu d0, h0225; CHECK-NEXT: ret226 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half %a)227 %d = bitcast i64 %vcvtah_s64_f16 to double228 ret double %d229}230 231define double @fcvtmu_1d1d_simd(double %a) {232; CHECK-LABEL: fcvtmu_1d1d_simd:233; CHECK: // %bb.0:234; CHECK-NEXT: fcvtmu d0, d0235; CHECK-NEXT: ret236 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %a)237 %d = bitcast i64 %vcvtah_s64_f64 to double238 ret double %d239}240 241define float @fcvtmu_1s1s_simd(float %a) {242; CHECK-LABEL: fcvtmu_1s1s_simd:243; CHECK: // %bb.0:244; CHECK-NEXT: fcvtmu s0, s0245; CHECK-NEXT: ret246 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %a)247 %d = bitcast i32 %vcvtah_s32_f32 to float248 ret float %d249}250 251define float @fcvtns_1s1d_simd(double %A) nounwind {252; CHECK-LABEL: fcvtns_1s1d_simd:253; CHECK: // %bb.0:254; CHECK-NEXT: fcvtns s0, d0255; CHECK-NEXT: ret256 %i = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double %A)257 %f = bitcast i32 %i to float258 ret float %f259}260 261define double @fcvtns_1d1s_simd(float %A) nounwind {262; CHECK-LABEL: fcvtns_1d1s_simd:263; CHECK: // %bb.0:264; CHECK-NEXT: fcvtns d0, s0265; CHECK-NEXT: ret266 %i = call i64 @llvm.aarch64.neon.fcvtns.i64.f32(float %A)267 %d = bitcast i64 %i to double268 ret double %d269}270 271define float @fcvtns_1s1h_simd(half %a) {272; CHECK-LABEL: fcvtns_1s1h_simd:273; CHECK: // %bb.0:274; CHECK-NEXT: fcvtns s0, h0275; CHECK-NEXT: ret276 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtns.i32.f16(half %a)277 %f = bitcast i32 %fcvt to float278 ret float %f279}280 281define double @fcvtns_1d1h_simd(half %a) {282; CHECK-LABEL: fcvtns_1d1h_simd:283; CHECK: // %bb.0:284; CHECK-NEXT: fcvtns d0, h0285; CHECK-NEXT: ret286 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f16(half %a)287 %d = bitcast i64 %vcvtah_s64_f16 to double288 ret double %d289}290 291define double @fcvtns_1d1d_simd(double %a) {292; CHECK-LABEL: fcvtns_1d1d_simd:293; CHECK: // %bb.0:294; CHECK-NEXT: fcvtns d0, d0295; CHECK-NEXT: ret296 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %a)297 %d = bitcast i64 %vcvtah_s64_f64 to double298 ret double %d299}300 301define float @fcvtns_1s1s_simd(float %a) {302; CHECK-LABEL: fcvtns_1s1s_simd:303; CHECK: // %bb.0:304; CHECK-NEXT: fcvtns s0, s0305; CHECK-NEXT: ret306 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float %a)307 %d = bitcast i32 %vcvtah_s32_f32 to float308 ret float %d309}310 311define float @fcvtnu_1s1d_simd(double %A) nounwind {312; CHECK-LABEL: fcvtnu_1s1d_simd:313; CHECK: // %bb.0:314; CHECK-NEXT: fcvtnu s0, d0315; CHECK-NEXT: ret316 %i = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double %A)317 %f = bitcast i32 %i to float318 ret float %f319}320 321define double @fcvtnu_1d1s_simd(float %A) nounwind {322; CHECK-LABEL: fcvtnu_1d1s_simd:323; CHECK: // %bb.0:324; CHECK-NEXT: fcvtnu d0, s0325; CHECK-NEXT: ret326 %i = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A)327 %d = bitcast i64 %i to double328 ret double %d329}330 331define float @fcvtnu_1s1h_simd(half %a) {332; CHECK-LABEL: fcvtnu_1s1h_simd:333; CHECK: // %bb.0:334; CHECK-NEXT: fcvtnu s0, h0335; CHECK-NEXT: ret336 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half %a)337 %f = bitcast i32 %fcvt to float338 ret float %f339}340 341define double @fcvtnu_1d1h_simd(half %a) {342; CHECK-LABEL: fcvtnu_1d1h_simd:343; CHECK: // %bb.0:344; CHECK-NEXT: fcvtnu d0, h0345; CHECK-NEXT: ret346 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half %a)347 %d = bitcast i64 %vcvtah_s64_f16 to double348 ret double %d349}350 351define double @fcvtnu_1d1d_simd(double %a) {352; CHECK-LABEL: fcvtnu_1d1d_simd:353; CHECK: // %bb.0:354; CHECK-NEXT: fcvtnu d0, d0355; CHECK-NEXT: ret356 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %a)357 %d = bitcast i64 %vcvtah_s64_f64 to double358 ret double %d359}360 361define float @fcvtnu_1s1s_simd(float %a) {362; CHECK-LABEL: fcvtnu_1s1s_simd:363; CHECK: // %bb.0:364; CHECK-NEXT: fcvtnu s0, s0365; CHECK-NEXT: ret366 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %a)367 %d = bitcast i32 %vcvtah_s32_f32 to float368 ret float %d369}370 371define float @fcvtps_1s1d_simd(double %A) nounwind {372; CHECK-LABEL: fcvtps_1s1d_simd:373; CHECK: // %bb.0:374; CHECK-NEXT: fcvtps s0, d0375; CHECK-NEXT: ret376 %i = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double %A)377 %f = bitcast i32 %i to float378 ret float %f379}380 381define double @fcvtps_1d1s_simd(float %A) nounwind {382; CHECK-LABEL: fcvtps_1d1s_simd:383; CHECK: // %bb.0:384; CHECK-NEXT: fcvtps d0, s0385; CHECK-NEXT: ret386 %i = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float %A)387 %d = bitcast i64 %i to double388 ret double %d389}390 391define float @fcvtps_1s1h_simd(half %a) {392; CHECK-LABEL: fcvtps_1s1h_simd:393; CHECK: // %bb.0:394; CHECK-NEXT: fcvtps s0, h0395; CHECK-NEXT: ret396 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtps.i32.f16(half %a)397 %f = bitcast i32 %fcvt to float398 ret float %f399}400 401define double @fcvtps_1d1h_simd(half %a) {402; CHECK-LABEL: fcvtps_1d1h_simd:403; CHECK: // %bb.0:404; CHECK-NEXT: fcvtps d0, h0405; CHECK-NEXT: ret406 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f16(half %a)407 %d = bitcast i64 %vcvtah_s64_f16 to double408 ret double %d409}410 411define double @fcvtps_1d1d_simd(double %a) {412; CHECK-LABEL: fcvtps_1d1d_simd:413; CHECK: // %bb.0:414; CHECK-NEXT: fcvtps d0, d0415; CHECK-NEXT: ret416 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %a)417 %d = bitcast i64 %vcvtah_s64_f64 to double418 ret double %d419}420 421define float @fcvtps_1s1s_simd(float %a) {422; CHECK-LABEL: fcvtps_1s1s_simd:423; CHECK: // %bb.0:424; CHECK-NEXT: fcvtps s0, s0425; CHECK-NEXT: ret426 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %a)427 %d = bitcast i32 %vcvtah_s32_f32 to float428 ret float %d429}430 431define float @fcvtpu_1s1d_simd(double %A) nounwind {432; CHECK-LABEL: fcvtpu_1s1d_simd:433; CHECK: // %bb.0:434; CHECK-NEXT: fcvtpu s0, d0435; CHECK-NEXT: ret436 %i = call i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double %A)437 %f = bitcast i32 %i to float438 ret float %f439}440 441define double @fcvtpu_1d1s_simd(float %A) nounwind {442; CHECK-LABEL: fcvtpu_1d1s_simd:443; CHECK: // %bb.0:444; CHECK-NEXT: fcvtpu d0, s0445; CHECK-NEXT: ret446 %i = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float %A)447 %d = bitcast i64 %i to double448 ret double %d449}450 451define float @fcvtpu_1s1h_simd(half %a) {452; CHECK-LABEL: fcvtpu_1s1h_simd:453; CHECK: // %bb.0:454; CHECK-NEXT: fcvtpu s0, h0455; CHECK-NEXT: ret456 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half %a)457 %f = bitcast i32 %fcvt to float458 ret float %f459}460 461define double @fcvtpu_1d1h_simd(half %a) {462; CHECK-LABEL: fcvtpu_1d1h_simd:463; CHECK: // %bb.0:464; CHECK-NEXT: fcvtpu d0, h0465; CHECK-NEXT: ret466 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half %a)467 %d = bitcast i64 %vcvtah_s64_f16 to double468 ret double %d469}470 471define double @fcvtpu_1d1d_simd(double %a) {472; CHECK-LABEL: fcvtpu_1d1d_simd:473; CHECK: // %bb.0:474; CHECK-NEXT: fcvtpu d0, d0475; CHECK-NEXT: ret476 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %a)477 %d = bitcast i64 %vcvtah_s64_f64 to double478 ret double %d479}480 481define float @fcvtpu_1s1s_simd(float %a) {482; CHECK-LABEL: fcvtpu_1s1s_simd:483; CHECK: // %bb.0:484; CHECK-NEXT: fcvtpu s0, s0485; CHECK-NEXT: ret486 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float %a)487 %d = bitcast i32 %vcvtah_s32_f32 to float488 ret float %d489}490 491define float @fcvtzs_1s1d_simd(double %A) nounwind {492; CHECK-LABEL: fcvtzs_1s1d_simd:493; CHECK: // %bb.0:494; CHECK-NEXT: fcvtzs s0, d0495; CHECK-NEXT: ret496 %i = call i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double %A)497 %f = bitcast i32 %i to float498 ret float %f499}500 501define double @fcvtzs_1d1s_simd(float %A) nounwind {502; CHECK-LABEL: fcvtzs_1d1s_simd:503; CHECK: // %bb.0:504; CHECK-NEXT: fcvtzs d0, s0505; CHECK-NEXT: ret506 %i = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %A)507 %d = bitcast i64 %i to double508 ret double %d509}510 511define float @fcvtzs_1s1h_simd(half %a) {512; CHECK-LABEL: fcvtzs_1s1h_simd:513; CHECK: // %bb.0:514; CHECK-NEXT: fcvtzs s0, h0515; CHECK-NEXT: ret516 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half %a)517 %f = bitcast i32 %fcvt to float518 ret float %f519}520 521define double @fcvtzs_1d1h_simd(half %a) {522; CHECK-LABEL: fcvtzs_1d1h_simd:523; CHECK: // %bb.0:524; CHECK-NEXT: fcvtzs d0, h0525; CHECK-NEXT: ret526 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)527 %d = bitcast i64 %vcvtah_s64_f16 to double528 ret double %d529}530 531define double @fcvtzs_1d1d_simd(double %a) {532; CHECK-LABEL: fcvtzs_1d1d_simd:533; CHECK: // %bb.0:534; CHECK-NEXT: fcvtzs d0, d0535; CHECK-NEXT: ret536 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %a)537 %d = bitcast i64 %vcvtah_s64_f64 to double538 ret double %d539}540 541define float @fcvtzs_1s1s_simd(float %a) {542; CHECK-LABEL: fcvtzs_1s1s_simd:543; CHECK: // %bb.0:544; CHECK-NEXT: fcvtzs s0, s0545; CHECK-NEXT: ret546 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)547 %d = bitcast i32 %vcvtah_s32_f32 to float548 ret float %d549}550 551define float @fcvtzu_1s1d_simd(double %A) nounwind {552; CHECK-LABEL: fcvtzu_1s1d_simd:553; CHECK: // %bb.0:554; CHECK-NEXT: fcvtzu s0, d0555; CHECK-NEXT: ret556 %i = call i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double %A)557 %f = bitcast i32 %i to float558 ret float %f559}560 561define double @fcvtzu_1d1s_simd(float %A) nounwind {562; CHECK-LABEL: fcvtzu_1d1s_simd:563; CHECK: // %bb.0:564; CHECK-NEXT: fcvtzu d0, s0565; CHECK-NEXT: ret566 %i = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float %A)567 %d = bitcast i64 %i to double568 ret double %d569}570 571define float @fcvtzu_1s1h_simd(half %a) {572; CHECK-LABEL: fcvtzu_1s1h_simd:573; CHECK: // %bb.0:574; CHECK-NEXT: fcvtzu s0, h0575; CHECK-NEXT: ret576 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half %a)577 %f = bitcast i32 %fcvt to float578 ret float %f579}580 581define double @fcvtzu_1d1h_simd(half %a) {582; CHECK-LABEL: fcvtzu_1d1h_simd:583; CHECK: // %bb.0:584; CHECK-NEXT: fcvtzu d0, h0585; CHECK-NEXT: ret586 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtzu.i64.f16(half %a)587 %d = bitcast i64 %vcvtah_s64_f16 to double588 ret double %d589}590 591define double @fcvtzu_1d1d_simd(double %a) {592; CHECK-LABEL: fcvtzu_1d1d_simd:593; CHECK: // %bb.0:594; CHECK-NEXT: fcvtzu d0, d0595; CHECK-NEXT: ret596 %vcvtah_s64_f64 = tail call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %a)597 %d = bitcast i64 %vcvtah_s64_f64 to double598 ret double %d599}600 601define float @fcvtzu_1s1s_simd(float %a) {602; CHECK-LABEL: fcvtzu_1s1s_simd:603; CHECK: // %bb.0:604; CHECK-NEXT: fcvtzu s0, s0605; CHECK-NEXT: ret606 %vcvtah_s32_f32 = tail call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %a)607 %d = bitcast i32 %vcvtah_s32_f32 to float608 ret float %d609}610