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1; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s2 3define void @branch1() nounwind uwtable ssp {4 %x = alloca i32, align 45 store i32 0, ptr %x, align 46 %1 = load i32, ptr %x, align 47 %2 = icmp ne i32 %1, 08 br i1 %2, label %3, label %49 10; <label>:3 ; preds = %011 br label %412 13; <label>:4 ; preds = %3, %014 ret void15}16 17define void @branch2() nounwind uwtable ssp {18 %1 = alloca i32, align 419 %x = alloca i32, align 420 %y = alloca i32, align 421 %z = alloca i32, align 422 store i32 0, ptr %123 store i32 1, ptr %y, align 424 store i32 1, ptr %x, align 425 store i32 0, ptr %z, align 426 %2 = load i32, ptr %x, align 427 %3 = icmp ne i32 %2, 028 br i1 %3, label %4, label %529 30; <label>:4 ; preds = %031 store i32 0, ptr %132 br label %1433 34; <label>:5 ; preds = %035 %6 = load i32, ptr %y, align 436 %7 = icmp ne i32 %6, 037 br i1 %7, label %8, label %1338 39; <label>:8 ; preds = %540 %9 = load i32, ptr %z, align 441 %10 = icmp ne i32 %9, 042 br i1 %10, label %11, label %1243 44; <label>:11 ; preds = %845 store i32 1, ptr %146 br label %1447 48; <label>:12 ; preds = %849 store i32 0, ptr %150 br label %1451 52; <label>:13 ; preds = %553 br label %1454 55; <label>:14 ; preds = %4, %11, %12, %1356 %15 = load i32, ptr %157 ret void58}59 60define void @true_() nounwind uwtable ssp {61; CHECK: @true_62; CHECK: b LBB2_163 br i1 true, label %1, label %264 65; <label>:166; CHECK: LBB2_167 br label %268 69; <label>:270 ret void71}72 73define void @false_() nounwind uwtable ssp {74; CHECK: @false_75; CHECK: b LBB3_276 br i1 false, label %1, label %277 78; <label>:179 br label %280 81; <label>:282; CHECK: LBB3_283 ret void84}85 86define zeroext i8 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) {87entry:88 %a.addr = alloca i8, align 189 %b.addr = alloca i16, align 290 %c.addr = alloca i32, align 491 %d.addr = alloca i64, align 892 store i8 %a, ptr %a.addr, align 193 store i16 %b, ptr %b.addr, align 294 store i32 %c, ptr %c.addr, align 495 store i64 %d, ptr %d.addr, align 896 %0 = load i16, ptr %b.addr, align 297; CHECK: tbz {{w[0-9]+}}, #0, LBB4_298 %conv = trunc i16 %0 to i199 br i1 %conv, label %if.then, label %if.end100 101if.then: ; preds = %entry102 call void @foo1()103 br label %if.end104 105if.end: ; preds = %if.then, %entry106 %1 = load i32, ptr %c.addr, align 4107; CHECK: tbz w{{[0-9]+}}, #0, LBB4_4108 %conv1 = trunc i32 %1 to i1109 br i1 %conv1, label %if.then3, label %if.end4110 111if.then3: ; preds = %if.end112 call void @foo1()113 br label %if.end4114 115if.end4: ; preds = %if.then3, %if.end116 %2 = load i64, ptr %d.addr, align 8117; CHECK: tbz w{{[0-9]+}}, #0, LBB4_6118 %conv5 = trunc i64 %2 to i1119 br i1 %conv5, label %if.then7, label %if.end8120 121if.then7: ; preds = %if.end4122 call void @foo1()123 br label %if.end8124 125if.end8: ; preds = %if.then7, %if.end4126 %3 = load i8, ptr %a.addr, align 1127 ret i8 %3128}129 130declare void @foo1()131 132; rdar://15174028133define i32 @trunc64(i64 %foo) nounwind {134; CHECK: trunc64135; CHECK: and x[[REG1:[0-9]+]], x0, #0x1136; CHECK: tbz w[[REG1]], #0, LBB5_2137 %a = and i64 %foo, 1138 %b = trunc i64 %a to i1139 br i1 %b, label %if.then, label %if.else140 141if.then:142 ret i32 1143 144if.else:145 ret i32 0146}147