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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function icmp_i8_shift_and_cmp --version 42; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s3 4define i32 @icmp_eq_imm(i32 %a) nounwind ssp {5entry:6; CHECK-LABEL: icmp_eq_imm7; CHECK: cmp w0, #318; CHECK-NEXT: cset [[REG:w[0-9]+]], eq9; CHECK-NEXT: and w0, [[REG]], #0x110 %cmp = icmp eq i32 %a, 3111 %conv = zext i1 %cmp to i3212 ret i32 %conv13}14 15define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp {16entry:17; CHECK-LABEL: icmp_eq_neg_imm18; CHECK: cmn w0, #719; CHECK-NEXT: cset [[REG:w[0-9]+]], eq20; CHECK-NEXT: and w0, [[REG]], #0x121 %cmp = icmp eq i32 %a, -722 %conv = zext i1 %cmp to i3223 ret i32 %conv24}25 26define i32 @icmp_eq_i32(i32 %a, i32 %b) nounwind ssp {27entry:28; CHECK-LABEL: icmp_eq_i3229; CHECK: cmp w0, w130; CHECK-NEXT: cset [[REG:w[0-9]+]], eq31; CHECK-NEXT: and w0, [[REG]], #0x132 %cmp = icmp eq i32 %a, %b33 %conv = zext i1 %cmp to i3234 ret i32 %conv35}36 37define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp {38entry:39; CHECK-LABEL: icmp_ne40; CHECK: cmp w0, w141; CHECK-NEXT: cset [[REG:w[0-9]+]], ne42; CHECK-NEXT: and w0, [[REG]], #0x143 %cmp = icmp ne i32 %a, %b44 %conv = zext i1 %cmp to i3245 ret i32 %conv46}47 48define i32 @icmp_eq_ptr(ptr %a) {49entry:50; CHECK-LABEL: icmp_eq_ptr51; CHECK: cmp x0, #052; CHECK-NEXT: cset {{.+}}, eq53 %cmp = icmp eq ptr %a, null54 %conv = zext i1 %cmp to i3255 ret i32 %conv56}57 58define i32 @icmp_ne_ptr(ptr %a) {59entry:60; CHECK-LABEL: icmp_ne_ptr61; CHECK: cmp x0, #062; CHECK-NEXT: cset {{.+}}, ne63 %cmp = icmp ne ptr %a, null64 %conv = zext i1 %cmp to i3265 ret i32 %conv66}67 68define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp {69entry:70; CHECK-LABEL: icmp_ugt71; CHECK: cmp w0, w172; CHECK-NEXT: cset [[REG:w[0-9]+]], hi73; CHECK-NEXT: and w0, [[REG]], #0x174 %cmp = icmp ugt i32 %a, %b75 %conv = zext i1 %cmp to i3276 ret i32 %conv77}78 79define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp {80entry:81; CHECK-LABEL: icmp_uge82; CHECK: cmp w0, w183; CHECK-NEXT: cset [[REG:w[0-9]+]], hs84; CHECK-NEXT: and w0, [[REG]], #0x185 %cmp = icmp uge i32 %a, %b86 %conv = zext i1 %cmp to i3287 ret i32 %conv88}89 90define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp {91entry:92; CHECK-LABEL: icmp_ult93; CHECK: cmp w0, w194; CHECK-NEXT: cset [[REG:w[0-9]+]], lo95; CHECK-NEXT: and w0, [[REG]], #0x196 %cmp = icmp ult i32 %a, %b97 %conv = zext i1 %cmp to i3298 ret i32 %conv99}100 101define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp {102entry:103; CHECK-LABEL: icmp_ule104; CHECK: cmp w0, w1105; CHECK-NEXT: cset [[REG:w[0-9]+]], ls106; CHECK-NEXT: and w0, [[REG]], #0x1107 %cmp = icmp ule i32 %a, %b108 %conv = zext i1 %cmp to i32109 ret i32 %conv110}111 112define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp {113entry:114; CHECK-LABEL: icmp_sgt115; CHECK: cmp w0, w1116; CHECK-NEXT: cset [[REG:w[0-9]+]], gt117; CHECK-NEXT: and w0, [[REG]], #0x1118 %cmp = icmp sgt i32 %a, %b119 %conv = zext i1 %cmp to i32120 ret i32 %conv121}122 123define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp {124entry:125; CHECK-LABEL: icmp_sge126; CHECK: cmp w0, w1127; CHECK-NEXT: cset [[REG:w[0-9]+]], ge128; CHECK-NEXT: and w0, [[REG]], #0x1129 %cmp = icmp sge i32 %a, %b130 %conv = zext i1 %cmp to i32131 ret i32 %conv132}133 134define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp {135entry:136; CHECK-LABEL: icmp_slt137; CHECK: cmp w0, w1138; CHECK-NEXT: cset [[REG:w[0-9]+]], lt139; CHECK-NEXT: and w0, [[REG]], #0x1140 %cmp = icmp slt i32 %a, %b141 %conv = zext i1 %cmp to i32142 ret i32 %conv143}144 145define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp {146entry:147; CHECK-LABEL: icmp_sle148; CHECK: cmp w0, w1149; CHECK-NEXT: cset [[REG:w[0-9]+]], le150; CHECK-NEXT: and w0, [[REG]], #0x1151 %cmp = icmp sle i32 %a, %b152 %conv = zext i1 %cmp to i32153 ret i32 %conv154}155 156define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp {157entry:158; CHECK-LABEL: icmp_i64159; CHECK: cmp x0, x1160; CHECK-NEXT: cset [[REG:w[0-9]+]], le161; CHECK-NEXT: and w0, [[REG]], #0x1162 %cmp = icmp sle i64 %a, %b163 %conv = zext i1 %cmp to i32164 ret i32 %conv165}166 167define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp {168entry:169; CHECK-LABEL: icmp_eq_i16170; CHECK: sxth [[REG0:w[0-9]+]], w0171; CHECK: cmp [[REG0]], w1, sxth172; CHECK-NEXT: cset [[REG:w[0-9]+]], eq173; CHECK-NEXT: and w0, [[REG]], #0x1174 %cmp = icmp eq i16 %a, %b175 ret i1 %cmp176}177 178define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp {179entry:180; CHECK-LABEL: icmp_eq_i8181; CHECK: sxtb [[REG0:w[0-9]+]], w0182; CHECK-NEXT: cmp [[REG0]], w1, sxtb183; CHECK-NEXT: cset [[REG:w[0-9]+]], eq184; CHECK-NEXT: and w0, [[REG]], #0x1185 %cmp = icmp eq i8 %a, %b186 ret i1 %cmp187}188 189define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind {190entry:191; CHECK-LABEL: icmp_i16_unsigned192; CHECK: uxth [[REG0:w[0-9]+]], w0193; CHECK-NEXT: cmp [[REG0]], w1, uxth194; CHECK-NEXT: cset [[REG:w[0-9]+]], lo195; CHECK-NEXT: and w0, [[REG]], #0x1196 %cmp = icmp ult i16 %a, %b197 %conv2 = zext i1 %cmp to i32198 ret i32 %conv2199}200 201define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind {202entry:203; CHECK-LABEL: icmp_i8_signed204; CHECK: sxtb [[REG0:w[0-9]+]], w0205; CHECK-NEXT: cmp [[REG0]], w1, sxtb206; CHECK-NEXT: cset [[REG:w[0-9]+]], gt207; CHECK-NEXT: and w0, [[REG]], #0x1208 %cmp = icmp sgt i8 %a, %b209 %conv2 = zext i1 %cmp to i32210 ret i32 %conv2211}212 213define i32 @icmp_i1_signed(i1 %a, i1 %b) nounwind {214entry:215; CHECK-LABEL: icmp_i1_signed216; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1217; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1218; CHECK-NEXT: cmp [[REG1]], [[REG2]]219; CHECK-NEXT: cset [[REG:w[0-9]+]], gt220; CHECK-NEXT: and w0, [[REG]], #0x1221 %cmp = icmp sgt i1 %a, %b222 %conv2 = zext i1 %cmp to i32223 ret i32 %conv2224}225 226define i32 @icmp_i16_signed_const(i16 %a) nounwind {227entry:228; CHECK-LABEL: icmp_i16_signed_const229; CHECK: sxth [[REG0:w[0-9]+]], w0230; CHECK-NEXT: cmn [[REG0]], #233231; CHECK-NEXT: cset [[REG:w[0-9]+]], lt232; CHECK-NEXT: and w0, [[REG]], #0x1233 %cmp = icmp slt i16 %a, -233234 %conv2 = zext i1 %cmp to i32235 ret i32 %conv2236}237 238define i32 @icmp_i8_signed_const(i8 %a) nounwind {239entry:240; CHECK-LABEL: icmp_i8_signed_const241; CHECK: sxtb [[REG0:w[0-9]+]], w0242; CHECK-NEXT: cmp [[REG0]], #124243; CHECK-NEXT: cset [[REG:w[0-9]+]], gt244; CHECK-NEXT: and w0, [[REG]], #0x1245 %cmp = icmp sgt i8 %a, 124246 %conv2 = zext i1 %cmp to i32247 ret i32 %conv2248}249 250define i32 @icmp_i1_unsigned_const(i1 %a) nounwind {251entry:252; CHECK-LABEL: icmp_i1_unsigned_const253; CHECK: and [[REG0:w[0-9]+]], w0, #0x1254; CHECK-NEXT: cmp [[REG0]], #0255; CHECK-NEXT: cset [[REG:w[0-9]+]], lo256; CHECK-NEXT: and w0, [[REG]], #0x1257 %cmp = icmp ult i1 %a, 0258 %conv2 = zext i1 %cmp to i32259 ret i32 %conv2260}261 262define i32 @icmp_i8_shift_and_cmp(i8 %a, i8 %b) {263entry:264; CHECK-LABEL: icmp_i8_shift_and_cmp:265; CHECK: ubfiz [[REG1:w[0-9]+]], w0, #3, #5266; CHECK-NEXT: sxtb [[REG0:w[0-9]+]], w1267; CHECK-NEXT: cmp [[REG0]], [[REG1]], sxtb268; CHECK-NEXT: cset [[REG:w[0-9]+]], eq269; CHECK-NEXT: and w0, [[REG]], #0x1270 %op = shl i8 %a, 3271 %cmp = icmp eq i8 %b, %op272 %conv = zext i1 %cmp to i32273 ret i32 %conv274}275 276