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1; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s2 3define void @t0(i32 %a) nounwind {4entry:5; CHECK-LABEL: t0:6; CHECK: str {{w[0-9]+}}, [sp, #12]7; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]8; CHECK-NEXT: str [[REGISTER]], [sp, #12]9; CHECK: ret10 %a.addr = alloca i32, align 411 store i32 %a, ptr %a.addr12 %tmp = load i32, ptr %a.addr13 store i32 %tmp, ptr %a.addr14 ret void15}16 17define void @t1(i64 %a) nounwind {18; CHECK-LABEL: t1:19; CHECK: str {{x[0-9]+}}, [sp, #8]20; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]21; CHECK-NEXT: str [[REGISTER]], [sp, #8]22; CHECK: ret23 %a.addr = alloca i64, align 424 store i64 %a, ptr %a.addr25 %tmp = load i64, ptr %a.addr26 store i64 %tmp, ptr %a.addr27 ret void28}29 30define zeroext i1 @i1(i1 %a) nounwind {31entry:32; CHECK-LABEL: i1:33; CHECK: and [[REG:w[0-9]+]], w0, #0x134; CHECK: strb [[REG]], [sp, #15]35; CHECK: ldrb [[REG1:w[0-9]+]], [sp, #15]36; CHECK: and [[REG2:w[0-9]+]], [[REG1]], #0x137; CHECK: and w0, [[REG2]], #0x138; CHECK: add sp, sp, #1639; CHECK: ret40 %a.addr = alloca i1, align 141 store i1 %a, ptr %a.addr, align 142 %0 = load i1, ptr %a.addr, align 143 ret i1 %044}45 46define i32 @t2(ptr %ptr) nounwind {47entry:48; CHECK-LABEL: t2:49; CHECK: ldur w0, [x0, #-4]50; CHECK: ret51 %0 = getelementptr i32, ptr %ptr, i32 -152 %1 = load i32, ptr %0, align 453 ret i32 %154}55 56define i32 @t3(ptr %ptr) nounwind {57entry:58; CHECK-LABEL: t3:59; CHECK: ldur w0, [x0, #-256]60; CHECK: ret61 %0 = getelementptr i32, ptr %ptr, i32 -6462 %1 = load i32, ptr %0, align 463 ret i32 %164}65 66define void @t4(ptr %ptr) nounwind {67entry:68; CHECK-LABEL: t4:69; CHECK: stur wzr, [x0, #-4]70; CHECK: ret71 %0 = getelementptr i32, ptr %ptr, i32 -172 store i32 0, ptr %0, align 473 ret void74}75 76define void @t5(ptr %ptr) nounwind {77entry:78; CHECK-LABEL: t5:79; CHECK: stur wzr, [x0, #-256]80; CHECK: ret81 %0 = getelementptr i32, ptr %ptr, i32 -6482 store i32 0, ptr %0, align 483 ret void84}85 86define void @t6() nounwind {87; CHECK-LABEL: t6:88; CHECK: brk #0x189 tail call void @llvm.trap()90 ret void91}92 93declare void @llvm.trap() nounwind94 95define void @ands(ptr %addr) {96; FIXME: 'select i1 undef' makes this unreliable (ub?).97; COM: CHECK-LABEL: ands:98; COM: CHECK: tst [[COND:w[0-9]+]], #0x199; COM: CHECK-NEXT: mov w{{[0-9]+}}, #2100; COM: CHECK-NEXT: mov w{{[0-9]+}}, #1101; COM: CHECK-NEXT: csel [[COND]],102entry:103 %cond91 = select i1 undef, i32 1, i32 2104 store i32 %cond91, ptr %addr, align 4105 ret void106}107 108define i64 @mul_umul(i64 %arg) {109; CHECK-LABEL: mul_umul:110; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]111; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]112entry:113 %sub.ptr.div = sdiv exact i64 %arg, 8114 %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)115 %tmp1 = extractvalue { i64, i1 } %tmp, 0116 ret i64 %tmp1117}118 119declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)120 121define void @logicalReg(i1 %arg) {122; Make sure we generate a logical reg = reg, reg instruction without any123; machine verifier errors.124; CHECK-LABEL: logicalReg:125; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}126; CHECK: ret127entry:128 br i1 %arg, label %cond.end, label %cond.false129 130cond.false:131 %cond = select i1 undef, i1 true, i1 false132 br label %cond.end133 134cond.end:135 %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]136 ret void137}138 139