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1; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s2; rdar://102638243 4define i1 @fcmp_float1(float %a) nounwind ssp {5entry:6; CHECK-LABEL: @fcmp_float17; CHECK: fcmp s0, #0.08; CHECK: cset w0, ne9 %cmp = fcmp une float %a, 0.000000e+0010 ret i1 %cmp11}12 13define i1 @fcmp_float2(float %a, float %b) nounwind ssp {14entry:15; CHECK-LABEL: @fcmp_float216; CHECK: fcmp s0, s117; CHECK: cset w0, ne18 %cmp = fcmp une float %a, %b19 ret i1 %cmp20}21 22define i1 @fcmp_double1(double %a) nounwind ssp {23entry:24; CHECK-LABEL: @fcmp_double125; CHECK: fcmp d0, #0.026; CHECK: cset w0, ne27 %cmp = fcmp une double %a, 0.000000e+0028 ret i1 %cmp29}30 31define i1 @fcmp_double2(double %a, double %b) nounwind ssp {32entry:33; CHECK-LABEL: @fcmp_double234; CHECK: fcmp d0, d135; CHECK: cset w0, ne36 %cmp = fcmp une double %a, %b37 ret i1 %cmp38}39 40; Check each fcmp condition41define float @fcmp_oeq(float %a, float %b) nounwind ssp {42; CHECK-LABEL: @fcmp_oeq43; CHECK: fcmp s0, s144; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr45; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.046; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq47 48 %cmp = fcmp oeq float %a, %b49 %conv = uitofp i1 %cmp to float50 ret float %conv51}52 53define float @fcmp_ogt(float %a, float %b) nounwind ssp {54; CHECK-LABEL: @fcmp_ogt55; CHECK: fcmp s0, s156; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr57; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.058; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt59 60 %cmp = fcmp ogt float %a, %b61 %conv = uitofp i1 %cmp to float62 ret float %conv63}64 65define float @fcmp_oge(float %a, float %b) nounwind ssp {66; CHECK-LABEL: @fcmp_oge67; CHECK: fcmp s0, s168; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr69; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.070; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge71 72 %cmp = fcmp oge float %a, %b73 %conv = uitofp i1 %cmp to float74 ret float %conv75}76 77define float @fcmp_olt(float %a, float %b) nounwind ssp {78; CHECK-LABEL: @fcmp_olt79; CHECK: fcmp s0, s180; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr81; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.082; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi83 84 %cmp = fcmp olt float %a, %b85 %conv = uitofp i1 %cmp to float86 ret float %conv87}88 89define float @fcmp_ole(float %a, float %b) nounwind ssp {90; CHECK-LABEL: @fcmp_ole91; CHECK: fcmp s0, s192; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr93; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.094; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls95 96 %cmp = fcmp ole float %a, %b97 %conv = uitofp i1 %cmp to float98 ret float %conv99}100 101define float @fcmp_ord(float %a, float %b) nounwind ssp {102; CHECK-LABEL: @fcmp_ord103; CHECK: fcmp s0, s1104; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr105; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0106; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc107 %cmp = fcmp ord float %a, %b108 %conv = uitofp i1 %cmp to float109 ret float %conv110}111 112define float @fcmp_uno(float %a, float %b) nounwind ssp {113; CHECK-LABEL: @fcmp_uno114; CHECK: fcmp s0, s1115; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr116; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0117; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs118 %cmp = fcmp uno float %a, %b119 %conv = uitofp i1 %cmp to float120 ret float %conv121}122 123define float @fcmp_ugt(float %a, float %b) nounwind ssp {124; CHECK-LABEL: @fcmp_ugt125; CHECK: fcmp s0, s1126; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr127; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0128; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi129 %cmp = fcmp ugt float %a, %b130 %conv = uitofp i1 %cmp to float131 ret float %conv132}133 134define float @fcmp_uge(float %a, float %b) nounwind ssp {135; CHECK-LABEL: @fcmp_uge136; CHECK: fcmp s0, s1137; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr138; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0139; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl140 %cmp = fcmp uge float %a, %b141 %conv = uitofp i1 %cmp to float142 ret float %conv143}144 145define float @fcmp_ult(float %a, float %b) nounwind ssp {146; CHECK-LABEL: @fcmp_ult147; CHECK: fcmp s0, s1148; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr149; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0150; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt151 %cmp = fcmp ult float %a, %b152 %conv = uitofp i1 %cmp to float153 ret float %conv154}155 156define float @fcmp_ule(float %a, float %b) nounwind ssp {157; CHECK-LABEL: @fcmp_ule158; CHECK: fcmp s0, s1159; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr160; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0161; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], le162 %cmp = fcmp ule float %a, %b163 %conv = uitofp i1 %cmp to float164 ret float %conv165}166 167define float @fcmp_une(float %a, float %b) nounwind ssp {168; CHECK-LABEL: @fcmp_une169; CHECK: fcmp s0, s1170; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr171; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0172; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ne173 %cmp = fcmp une float %a, %b174 %conv = uitofp i1 %cmp to float175 ret float %conv176}177 178; Possible opportunity for improvement. See comment in179; ARM64TargetLowering::LowerSETCC()180define float @fcmp_one(float %a, float %b) nounwind ssp {181; CHECK-LABEL: @fcmp_one182; fcmp s0, s1183; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr184; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0185; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], mi186; CHECK: fcsel s0, s[[ONE]], [[TMP]], gt187 %cmp = fcmp one float %a, %b188 %conv = uitofp i1 %cmp to float189 ret float %conv190}191 192; Possible opportunity for improvement. See comment in193; ARM64TargetLowering::LowerSETCC()194define float @fcmp_ueq(float %a, float %b) nounwind ssp {195; CHECK-LABEL: @fcmp_ueq196; CHECK: fcmp s0, s1197; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr198; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0199; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], eq200; CHECK: fcsel s0, s[[ONE]], [[TMP]], vs201 %cmp = fcmp ueq float %a, %b202 %conv = uitofp i1 %cmp to float203 ret float %conv204}205