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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s3 4define float @t1(i1 %a, float %b, float %c) nounwind {5; CHECK-LABEL: t1:6; CHECK: // %bb.0:7; CHECK-NEXT: tst w0, #0x18; CHECK-NEXT: fcsel s0, s0, s1, ne9; CHECK-NEXT: ret10 %sel = select i1 %a, float %b, float %c11 ret float %sel12}13 14; This may infinite loop if isNegatibleForFree and getNegatedExpression are conflicted.15 16define double @negation_propagation(ptr %arg, double %arg1, double %arg2) {17; CHECK-LABEL: negation_propagation:18; CHECK: // %bb.0:19; CHECK-NEXT: fmov d2, #1.0000000020; CHECK-NEXT: fdiv d0, d2, d021; CHECK-NEXT: fmul d2, d0, d022; CHECK-NEXT: fmul d1, d0, d123; CHECK-NEXT: fmul d0, d0, d224; CHECK-NEXT: fsub d0, d1, d025; CHECK-NEXT: ret26 %t = fdiv double 1.0, %arg127 %t7 = fmul double %t, %arg228 %t10 = fneg double %t729 %t11 = fmul double %t, %t30 %t13 = fsub double %t11, %t31 %t14 = fneg double %t32 %t15 = fmul double %t, %t1433 %t16 = fmul double %t, %t1534 %t18 = fadd double %t16, %t735 ret double %t1836}37 38define { double, double } @testfn(double %x, double %y) #0 {39; CHECK-LABEL: testfn:40; CHECK: // %bb.0:41; CHECK-NEXT: fsub d0, d0, d142; CHECK-NEXT: fneg d1, d043; CHECK-NEXT: ret44 %sub = fsub fast double %x, %y45 %neg = fneg fast double %sub46 %r0 = insertvalue { double, double } undef, double %sub, 047 %r1 = insertvalue { double, double } %r0, double %neg, 148 ret { double, double } %r149}50 51define <2 x float> @fake_fneg_splat_extract(<4 x float> %rhs) {52; CHECK-LABEL: fake_fneg_splat_extract:53; CHECK: // %bb.0:54; CHECK-NEXT: fneg v0.4s, v0.4s55; CHECK-NEXT: dup v0.2s, v0.s[3]56; CHECK-NEXT: ret57 %rhs_neg = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %rhs58 %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <2 x i32> <i32 3, i32 3>59 ret <2 x float> %splat60}61 62define <2 x float> @fake_fneg_splat_extract_undef(<4 x float> %rhs) {63; CHECK-LABEL: fake_fneg_splat_extract_undef:64; CHECK: // %bb.0:65; CHECK-NEXT: fneg v0.4s, v0.4s66; CHECK-NEXT: dup v0.2s, v0.s[3]67; CHECK-NEXT: ret68 %rhs_neg = fsub <4 x float> <float undef, float -0.0, float -0.0, float -0.0>, %rhs69 %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <2 x i32> <i32 3, i32 3>70 ret <2 x float> %splat71}72 73attributes #0 = { "no-signed-zeros-fp-math"="true" }74