94 lines · plain
1; RUN: llc < %s2 3target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"4target triple = "arm64-apple-ios7.0.0"5 6; This used to assert with "Overran sorted position" in AssignTopologicalOrder7; due to a cycle created in performPostLD1Combine.8 9; Function Attrs: nounwind ssp10define void @f(ptr %P1) #0 {11entry:12 %arrayidx4 = getelementptr inbounds double, ptr %P1, i64 113 %0 = load double, ptr %arrayidx4, align 8, !tbaa !114 %1 = load double, ptr %P1, align 8, !tbaa !115 %2 = insertelement <2 x double> undef, double %0, i32 016 %3 = insertelement <2 x double> %2, double %1, i32 117 %4 = fsub <2 x double> zeroinitializer, %318 %5 = fmul <2 x double> undef, %419 %6 = extractelement <2 x double> %5, i32 020 %cmp168 = fcmp olt double %6, undef21 br i1 %cmp168, label %if.then172, label %return22 23if.then172: ; preds = %cond.end9024 %7 = tail call i64 @llvm.objectsize.i64.p0(ptr undef, i1 false)25 br label %return26 27return: ; preds = %if.then172, %cond.end90, %entry28 ret void29}30 31; Avoid an assert/bad codegen in LD1LANEPOST lowering by not forming32; LD1LANEPOST ISD nodes with a non-constant lane index.33define <4 x i32> @f2(ptr %p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2, i32 %idx) {34 %L0 = load i32, ptr %p35 %p1 = getelementptr i32, ptr %p, i64 136 %L1 = load i32, ptr %p137 %v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v238 %vret = insertelement <4 x i32> %v, i32 %L0, i32 %idx39 store i32 %L1, ptr %p40 ret <4 x i32> %vret41}42 43; Check that a cycle is avoided during isel between the LD1LANEPOST instruction and the load of %L1.44define <4 x i32> @f3(ptr %p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2) {45 %L0 = load i32, ptr %p46 %p1 = getelementptr i32, ptr %p, i64 147 %L1 = load i32, ptr %p148 %v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v249 %vret = insertelement <4 x i32> %v, i32 %L0, i32 %L150 ret <4 x i32> %vret51}52 53; This test used to crash in performPostLD1Combine when the combine attempted to54; replace a load that already had index writeback, resulting in an incorrect55; CombineTo, which would have changed the number of SDValue results of the56; instruction.57define i32 @rdar138004275(ptr %arg, i1 %arg1) {58bb:59 br label %bb360 61bb2: ; preds = %bb362 store volatile <8 x half> %shufflevector10, ptr null, align 1663 ret i32 064 65bb3: ; preds = %bb3, %bb66 %phi = phi ptr [ null, %bb ], [ %getelementptr11, %bb3 ]67 %load = load <2 x half>, ptr %phi, align 468 %shufflevector = shufflevector <2 x half> %load, <2 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>69 %getelementptr = getelementptr i8, ptr %phi, i64 470 %load4 = load half, ptr %getelementptr, align 271 %insertelement = insertelement <2 x half> zeroinitializer, half %load4, i64 072 %shufflevector5 = shufflevector <2 x half> %insertelement, <2 x half> zeroinitializer, <8 x i32> <i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>73 %shufflevector6 = shufflevector <8 x half> %shufflevector, <8 x half> %shufflevector5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7>74 store <8 x half> %shufflevector6, ptr %arg, align 1675 %getelementptr7 = getelementptr i8, ptr %phi, i64 676 %load8 = load <2 x half>, ptr %getelementptr7, align 477 %shufflevector9 = shufflevector <2 x half> %load8, <2 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>78 %shufflevector10 = shufflevector <8 x half> %shufflevector9, <8 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 poison, i32 poison, i32 14, i32 15>79 %getelementptr11 = getelementptr i8, ptr %phi, i64 680 br i1 %arg1, label %bb2, label %bb381}82 83 84; Function Attrs: nounwind readnone85declare i64 @llvm.objectsize.i64.p0(ptr, i1) #186 87attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" }88attributes #1 = { nounwind readnone }89 90!1 = !{!2, !2, i64 0}91!2 = !{!"double", !3, i64 0}92!3 = !{!"omnipotent char", !4, i64 0}93!4 = !{!"Simple C/C++ TBAA"}94