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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-neon-syntax=apple -no-integrated-as | FileCheck %s3 4; rdar://91672755 6define i32 @t1() nounwind ssp {7; CHECK-LABEL: t1:8; CHECK: ; %bb.0: ; %entry9; CHECK-NEXT: ; InlineAsm Start10; CHECK-NEXT: mov w0, 711; CHECK-NEXT: ; InlineAsm End12; CHECK-NEXT: ret13entry:14 %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind15 ret i32 %016}17 18define i64 @t2() nounwind ssp {19; CHECK-LABEL: t2:20; CHECK: ; %bb.0: ; %entry21; CHECK-NEXT: ; InlineAsm Start22; CHECK-NEXT: mov x0, 723; CHECK-NEXT: ; InlineAsm End24; CHECK-NEXT: ret25entry:26 %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind27 ret i64 %028}29 30define i64 @t3() nounwind ssp {31; CHECK-LABEL: t3:32; CHECK: ; %bb.0: ; %entry33; CHECK-NEXT: ; InlineAsm Start34; CHECK-NEXT: mov w0, 735; CHECK-NEXT: ; InlineAsm End36; CHECK-NEXT: ret37entry:38 %0 = tail call i64 asm "mov ${0:w}, 7", "=r"() nounwind39 ret i64 %040}41 42; rdar://928120643 44define void @t4(i64 %op) nounwind {45; CHECK-LABEL: t4:46; CHECK: ; %bb.0: ; %entry47; CHECK-NEXT: mov x8, x048; CHECK-NEXT: ; InlineAsm Start49; CHECK-NEXT: mov x0, x8; svc #0;50; CHECK-NEXT: ; InlineAsm End51; CHECK-NEXT: ret52entry:53 %0 = tail call i64 asm sideeffect "mov x0, $1; svc #0;", "=r,r,r,~{x0}"(i64 %op, i64 undef) nounwind54 ret void55}56 57; rdar://939429058 59define float @t5(float %x) nounwind {60; CHECK-LABEL: t5:61; CHECK: ; %bb.0: ; %entry62; CHECK-NEXT: ; InlineAsm Start63; CHECK-NEXT: fadd s0, s0, s064; CHECK-NEXT: ; InlineAsm End65; CHECK-NEXT: ret66entry:67 %0 = tail call float asm "fadd ${0:s}, ${0:s}, ${0:s}", "=w,0"(float %x) nounwind68 ret float %069}70 71; rdar://955359972 73define zeroext i8 @t6(ptr %src) nounwind {74; CHECK-LABEL: t6:75; CHECK: ; %bb.0: ; %entry76; CHECK-NEXT: ; InlineAsm Start77; CHECK-NEXT: ldtrb w8, [x0]78; CHECK-NEXT: ; InlineAsm End79; CHECK-NEXT: and w0, w8, #0xff80; CHECK-NEXT: ret81entry:82 %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(ptr %src) nounwind83 ret i8 %084}85 86define void @t7(ptr %f, i32 %g) nounwind {87; CHECK-LABEL: t7:88; CHECK: ; %bb.0: ; %entry89; CHECK-NEXT: sub sp, sp, #1690; CHECK-NEXT: add x8, sp, #891; CHECK-NEXT: str x0, [sp, #8]92; CHECK-NEXT: ; InlineAsm Start93; CHECK-NEXT: str w1, [x8]94; CHECK-NEXT: ; InlineAsm End95; CHECK-NEXT: add sp, sp, #1696; CHECK-NEXT: ret97entry:98 %f.addr = alloca ptr, align 899 store ptr %f, ptr %f.addr, align 8100 call void asm "str ${1:w}, $0", "=*Q,r"(ptr elementtype(ptr) %f.addr, i32 %g) nounwind101 ret void102}103 104; rdar://10258229105; ARM64TargetLowering::getRegForInlineAsmConstraint() should recognize 'v'106; registers.107define void @t8() nounwind ssp {108; CHECK-LABEL: t8:109; CHECK: ; %bb.0: ; %entry110; CHECK-NEXT: stp d9, d8, [sp, #-16]! ; 16-byte Folded Spill111; CHECK-NEXT: ; InlineAsm Start112; CHECK-NEXT: nop113; CHECK-NEXT: ; InlineAsm End114; CHECK-NEXT: ldp d9, d8, [sp], #16 ; 16-byte Folded Reload115; CHECK-NEXT: ret116entry:117 tail call void asm sideeffect "nop", "~{v8}"() nounwind118 ret void119}120 121define i32 @constraint_I(i32 %i, i32 %j) nounwind {122; CHECK-LABEL: constraint_I:123; CHECK: ; %bb.0: ; %entry124; CHECK-NEXT: ; InlineAsm Start125; CHECK-NEXT: add w8, w0, 16773120126; CHECK-NEXT: ; InlineAsm End127; CHECK-NEXT: ; InlineAsm Start128; CHECK-NEXT: add w0, w0, 4096129; CHECK-NEXT: ; InlineAsm End130; CHECK-NEXT: ret131entry:132 %0 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 16773120) nounwind133 %1 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 4096) nounwind134 ret i32 %1135}136 137define i32 @constraint_J(i32 %i, i32 %j, i64 %k) nounwind {138; CHECK-LABEL: constraint_J:139; CHECK: ; %bb.0: ; %entry140; CHECK-NEXT: ; InlineAsm Start141; CHECK-NEXT: sub w8, w0, -16773120142; CHECK-NEXT: ; InlineAsm End143; CHECK-NEXT: ; InlineAsm Start144; CHECK-NEXT: sub w0, w0, -1145; CHECK-NEXT: ; InlineAsm End146; CHECK-NEXT: ; InlineAsm Start147; CHECK-NEXT: sub x8, x2, -1148; CHECK-NEXT: ; InlineAsm End149; CHECK-NEXT: ; InlineAsm Start150; CHECK-NEXT: sub x8, x2, -1151; CHECK-NEXT: ; InlineAsm End152; CHECK-NEXT: ret153entry:154 %0 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -16773120) nounwind155 %1 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -1) nounwind156 %2 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i32 -1) nounwind157 %3 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i64 -1) nounwind158 ret i32 %1159}160 161define i32 @constraint_KL(i32 %i, i32 %j) nounwind {162; CHECK-LABEL: constraint_KL:163; CHECK: ; %bb.0: ; %entry164; CHECK-NEXT: ; InlineAsm Start165; CHECK-NEXT: eor w8, w0, 255166; CHECK-NEXT: ; InlineAsm End167; CHECK-NEXT: ; InlineAsm Start168; CHECK-NEXT: eor w0, w0, 16711680169; CHECK-NEXT: ; InlineAsm End170; CHECK-NEXT: ret171entry:172 %0 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,K"(i32 %i, i32 255) nounwind173 %1 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,L"(i32 %i, i64 16711680) nounwind174 ret i32 %1175}176 177define i32 @constraint_MN(i32 %i, i32 %j) nounwind {178; CHECK-LABEL: constraint_MN:179; CHECK: ; %bb.0: ; %entry180; CHECK-NEXT: ; InlineAsm Start181; CHECK-NEXT: movk w8, 65535182; CHECK-NEXT: ; InlineAsm End183; CHECK-NEXT: ; InlineAsm Start184; CHECK-NEXT: movz w0, 0185; CHECK-NEXT: ; InlineAsm End186; CHECK-NEXT: ret187entry:188 %0 = tail call i32 asm sideeffect "movk ${0:w}, $1", "=r,M"(i32 65535) nounwind189 %1 = tail call i32 asm sideeffect "movz ${0:w}, $1", "=r,N"(i64 0) nounwind190 ret i32 %1191}192 193define void @t9() nounwind {194; CHECK-LABEL: t9:195; CHECK: ; %bb.0: ; %entry196; CHECK-NEXT: sub sp, sp, #16197; CHECK-NEXT: ldr q0, [sp], #16198; CHECK-NEXT: ; InlineAsm Start199; CHECK-NEXT: mov.2d v4, v0200; CHECK-EMPTY:201; CHECK-NEXT: ; InlineAsm End202; CHECK-NEXT: ret203entry:204 %data = alloca <2 x double>, align 16205 %0 = load <2 x double>, ptr %data, align 16206 call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind207 ret void208}209 210define void @t10() nounwind {211; CHECK-LABEL: t10:212; CHECK: ; %bb.0: ; %entry213; CHECK-NEXT: sub sp, sp, #16214; CHECK-NEXT: ldr d0, [sp, #8]215; CHECK-NEXT: mov x8, sp216; CHECK-NEXT: ; InlineAsm Start217; CHECK-NEXT: ldr z0, [x8]218; CHECK-EMPTY:219; CHECK-NEXT: ; InlineAsm End220; CHECK-NEXT: ; InlineAsm Start221; CHECK-NEXT: ldr q0, [x8]222; CHECK-EMPTY:223; CHECK-NEXT: ; InlineAsm End224; CHECK-NEXT: ; InlineAsm Start225; CHECK-NEXT: ldr d0, [x8]226; CHECK-EMPTY:227; CHECK-NEXT: ; InlineAsm End228; CHECK-NEXT: ; InlineAsm Start229; CHECK-NEXT: ldr s0, [x8]230; CHECK-EMPTY:231; CHECK-NEXT: ; InlineAsm End232; CHECK-NEXT: ; InlineAsm Start233; CHECK-NEXT: ldr h0, [x8]234; CHECK-EMPTY:235; CHECK-NEXT: ; InlineAsm End236; CHECK-NEXT: ; InlineAsm Start237; CHECK-NEXT: ldr b0, [x8]238; CHECK-EMPTY:239; CHECK-NEXT: ; InlineAsm End240; CHECK-NEXT: add sp, sp, #16241; CHECK-NEXT: ret242entry:243 %data = alloca <2 x float>, align 8244 %a = alloca [2 x float], align 4245 %0 = load <2 x float>, ptr %data, align 8246 call void asm sideeffect "ldr ${1:z}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind247 call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind248 call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind249 call void asm sideeffect "ldr ${1:s}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind250 call void asm sideeffect "ldr ${1:h}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind251 call void asm sideeffect "ldr ${1:b}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind252 ret void253}254 255define void @t11() nounwind {256; CHECK-LABEL: t11:257; CHECK: ; %bb.0: ; %entry258; CHECK-NEXT: sub sp, sp, #16259; CHECK-NEXT: ldr w8, [sp, #12]260; CHECK-NEXT: ; InlineAsm Start261; CHECK-NEXT: mov xzr, x8262; CHECK-EMPTY:263; CHECK-NEXT: ; InlineAsm End264; CHECK-NEXT: ldr w8, [sp, #12]265; CHECK-NEXT: ; InlineAsm Start266; CHECK-NEXT: mov wzr, w8267; CHECK-EMPTY:268; CHECK-NEXT: ; InlineAsm End269; CHECK-NEXT: add sp, sp, #16270; CHECK-NEXT: ret271entry:272 %a = alloca i32, align 4273 %0 = load i32, ptr %a, align 4274 call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind275 %1 = load i32, ptr %a, align 4276 call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind277 ret void278}279 280define void @t12() nounwind {281; CHECK-LABEL: t12:282; CHECK: ; %bb.0: ; %entry283; CHECK-NEXT: sub sp, sp, #16284; CHECK-NEXT: ldr q0, [sp], #16285; CHECK-NEXT: ; InlineAsm Start286; CHECK-NEXT: mov.2d v4, v0287; CHECK-EMPTY:288; CHECK-NEXT: ; InlineAsm End289; CHECK-NEXT: ret290entry:291 %data = alloca <4 x float>, align 16292 %0 = load <4 x float>, ptr %data, align 16293 call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind294 ret void295}296 297define void @t13() nounwind {298; CHECK-LABEL: t13:299; CHECK: ; %bb.0: ; %entry300; CHECK-NEXT: ; InlineAsm Start301; CHECK-NEXT: mov x4, 1311673391471656960302; CHECK-EMPTY:303; CHECK-NEXT: ; InlineAsm End304; CHECK-NEXT: ; InlineAsm Start305; CHECK-NEXT: mov x4, -4662306; CHECK-EMPTY:307; CHECK-NEXT: ; InlineAsm End308; CHECK-NEXT: ; InlineAsm Start309; CHECK-NEXT: mov x4, 4660310; CHECK-EMPTY:311; CHECK-NEXT: ; InlineAsm End312; CHECK-NEXT: ; InlineAsm Start313; CHECK-NEXT: mov x4, -71777214294589696314; CHECK-EMPTY:315; CHECK-NEXT: ; InlineAsm End316; CHECK-NEXT: ret317entry:318 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 1311673391471656960) nounwind319 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 -4662) nounwind320 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 4660) nounwind321 call void asm sideeffect "mov x4, $0\0A", "N"(i64 -71777214294589696) nounwind322 ret void323}324 325define void @t14() nounwind {326; CHECK-LABEL: t14:327; CHECK: ; %bb.0: ; %entry328; CHECK-NEXT: ; InlineAsm Start329; CHECK-NEXT: mov w4, 305397760330; CHECK-EMPTY:331; CHECK-NEXT: ; InlineAsm End332; CHECK-NEXT: ; InlineAsm Start333; CHECK-NEXT: mov w4, 4294962634334; CHECK-EMPTY:335; CHECK-NEXT: ; InlineAsm End336; CHECK-NEXT: ; InlineAsm Start337; CHECK-NEXT: mov w4, 4660338; CHECK-EMPTY:339; CHECK-NEXT: ; InlineAsm End340; CHECK-NEXT: ; InlineAsm Start341; CHECK-NEXT: mov w4, 4278255360342; CHECK-EMPTY:343; CHECK-NEXT: ; InlineAsm End344; CHECK-NEXT: ret345entry:346 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 305397760) nounwind347 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 -4662) nounwind348 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 4660) nounwind349 call void asm sideeffect "mov w4, $0\0A", "M"(i32 -16711936) nounwind350 ret void351}352 353define void @t15() nounwind {354; CHECK-LABEL: t15:355; CHECK: ; %bb.0: ; %entry356; CHECK-NEXT: ; InlineAsm Start357; CHECK-NEXT: fmov x8, d8358; CHECK-NEXT: ; InlineAsm End359; CHECK-NEXT: ret360entry:361 %0 = tail call double asm sideeffect "fmov $0, d8", "=r"() nounwind362 ret void363}364 365; rdar://problem/14285178366 367define void @test_zero_reg(ptr %addr) {368; CHECK-LABEL: test_zero_reg:369; CHECK: ; %bb.0:370; CHECK-NEXT: ; InlineAsm Start371; CHECK-NEXT: USE(xzr)372; CHECK-NEXT: ; InlineAsm End373; CHECK-NEXT: ; InlineAsm Start374; CHECK-NEXT: USE(wzr)375; CHECK-NEXT: ; InlineAsm End376; CHECK-NEXT: mov w8, #1 ; =0x1377; CHECK-NEXT: ; InlineAsm Start378; CHECK-NEXT: USE(w8)379; CHECK-NEXT: ; InlineAsm End380; CHECK-NEXT: ; InlineAsm Start381; CHECK-NEXT: USE(xzr), USE(xzr)382; CHECK-NEXT: ; InlineAsm End383; CHECK-NEXT: ; InlineAsm Start384; CHECK-NEXT: USE(xzr), USE(wzr)385; CHECK-NEXT: ; InlineAsm End386; CHECK-NEXT: ret387 388 tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind389 390 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 0)391 392 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1)393 394 tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind395 396 tail call void asm sideeffect "USE($0), USE(${1:w})", "z,z"(i32 0, i32 0) nounwind397 398 ret void399}400 401define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind {402; CHECK-LABEL: test_vreg_64bit:403; CHECK: ; %bb.0:404; CHECK-NEXT: stp d15, d14, [sp, #-16]! ; 16-byte Folded Spill405; CHECK-NEXT: ; InlineAsm Start406; CHECK-NEXT: fadd v14.2s, v0.2s, v0.2s407; CHECK-NEXT: ; InlineAsm End408; CHECK-NEXT: fmov d0, d14409; CHECK-NEXT: ldp d15, d14, [sp], #16 ; 16-byte Folded Reload410; CHECK-NEXT: ret411 %1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind412 ret <2 x float> %1413}414 415define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind {416; CHECK-LABEL: test_vreg_128bit:417; CHECK: ; %bb.0:418; CHECK-NEXT: stp d15, d14, [sp, #-16]! ; 16-byte Folded Spill419; CHECK-NEXT: ; InlineAsm Start420; CHECK-NEXT: fadd v14.4s, v0.4s, v0.4s421; CHECK-NEXT: ; InlineAsm End422; CHECK-NEXT: mov.16b v0, v14423; CHECK-NEXT: ldp d15, d14, [sp], #16 ; 16-byte Folded Reload424; CHECK-NEXT: ret425 %1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind426 ret <4 x float> %1427}428 429define void @test_constraint_w(i32 %a) {430; CHECK-LABEL: test_constraint_w:431; CHECK: ; %bb.0:432; CHECK-NEXT: fmov s0, w0433; CHECK-NEXT: ; InlineAsm Start434; CHECK-NEXT: sqxtn h0, s0435; CHECK-EMPTY:436; CHECK-NEXT: ; InlineAsm End437; CHECK-NEXT: ret438 439 tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a)440 ret void441}442 443define void @test_inline_modifier_a(ptr %ptr) nounwind {444; CHECK-LABEL: test_inline_modifier_a:445; CHECK: ; %bb.0:446; CHECK-NEXT: ; InlineAsm Start447; CHECK-NEXT: prfm pldl1keep, [x0]448; CHECK-EMPTY:449; CHECK-NEXT: ; InlineAsm End450; CHECK-NEXT: ret451 tail call void asm sideeffect "prfm pldl1keep, ${0:a}\0A", "r"(ptr %ptr)452 ret void453}454 455; PR33134456define void @test_zero_address() {457; CHECK-LABEL: test_zero_address:458; CHECK: ; %bb.0: ; %entry459; CHECK-NEXT: mov x8, xzr460; CHECK-NEXT: ; InlineAsm Start461; CHECK-NEXT: ldr x8, [x8]462; CHECK-EMPTY:463; CHECK-NEXT: ; InlineAsm End464; CHECK-NEXT: ret465entry:466 tail call i32 asm sideeffect "ldr $0, $1 \0A", "=r,*Q"(ptr elementtype(i32) null)467 ret void468}469 470; No '#' in lane specifier471define void @test_no_hash_in_lane_specifier() {472; CHECK-LABEL: test_no_hash_in_lane_specifier:473; CHECK: ; %bb.0:474; CHECK-NEXT: ; InlineAsm Start475; CHECK-NEXT: fmla v2.4s, v0.4s, v1.s[1]476; CHECK-NEXT: ; InlineAsm End477; CHECK-NEXT: ret478 tail call void asm sideeffect "fmla v2.4s, v0.4s, v1.s[$0]", "I"(i32 1) #1479 ret void480}481 482define void @test_vector_too_large_r_m(ptr nocapture readonly %0) {483; CHECK-LABEL: test_vector_too_large_r_m:484; CHECK: ; %bb.0: ; %entry485; CHECK-NEXT: sub sp, sp, #64486; CHECK-NEXT: .cfi_def_cfa_offset 64487; CHECK-NEXT: ldp q2, q1, [x0]488; CHECK-NEXT: mov x8, sp489; CHECK-NEXT: ldr s0, [x0, #32]490; CHECK-NEXT: str s0, [sp, #32]491; CHECK-NEXT: stp q2, q1, [sp]492; CHECK-NEXT: ; InlineAsm Start493; CHECK-NEXT: ; InlineAsm End494; CHECK-NEXT: add sp, sp, #64495; CHECK-NEXT: ret496entry:497 %m.addr = alloca <9 x float>, align 16498 %m = load <9 x float>, ptr %0, align 16499 store <9 x float> %m, ptr %m.addr, align 16500 call void asm sideeffect "", "=*r|m,0,~{memory}"(ptr elementtype(<9 x float>) nonnull %m.addr, <9 x float> %m)501 ret void502}503 504define void @test_o_output_constraint() {505; CHECK-LABEL: test_o_output_constraint:506; CHECK: ; %bb.0:507; CHECK-NEXT: sub sp, sp, #16508; CHECK-NEXT: .cfi_def_cfa_offset 16509; CHECK-NEXT: add x8, sp, #15510; CHECK-NEXT: ; InlineAsm Start511; CHECK-NEXT: mov [x8], 7512; CHECK-NEXT: ; InlineAsm End513; CHECK-NEXT: add sp, sp, #16514; CHECK-NEXT: ret515 %b = alloca i8, align 1516 call void asm "mov $0, 7", "=*o"(ptr elementtype(i8) %b)517 ret void518}519