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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefixes=CHECK,CHECK-A573; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m3 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s4 5; Test ldr clustering.6; CHECK: ********** MI Scheduling **********7; CHECK-LABEL: ldr_int:%bb.08; CHECK: Cluster ld/st SU(1) - SU(2)9; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui10; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui11define i32 @ldr_int(ptr %a) nounwind {12 %p1 = getelementptr inbounds i32, ptr %a, i32 113 %tmp1 = load i32, ptr %p1, align 214 %p2 = getelementptr inbounds i32, ptr %a, i32 215 %tmp2 = load i32, ptr %p2, align 216 %tmp3 = add i32 %tmp1, %tmp217 ret i32 %tmp318}19 20; Test ldpsw clustering21; CHECK: ********** MI Scheduling **********22; CHECK-LABEL: ldp_sext_int:%bb.023; CHECK: Cluster ld/st SU(1) - SU(2)24; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui25; CHECK: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui26define i64 @ldp_sext_int(ptr %p) nounwind {27 %tmp = load i32, ptr %p, align 428 %add.ptr = getelementptr inbounds i32, ptr %p, i64 129 %tmp1 = load i32, ptr %add.ptr, align 430 %sexttmp = sext i32 %tmp to i6431 %sexttmp1 = sext i32 %tmp1 to i6432 %add = add nsw i64 %sexttmp1, %sexttmp33 ret i64 %add34}35 36; Test ldur clustering.37; CHECK: ********** MI Scheduling **********38; CHECK-LABEL: ldur_int:%bb.039; CHECK: Cluster ld/st SU(1) - SU(2)40; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi41; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDURWi42define i32 @ldur_int(ptr %a) nounwind {43 %p1 = getelementptr inbounds i32, ptr %a, i32 -144 %tmp1 = load i32, ptr %p1, align 245 %p2 = getelementptr inbounds i32, ptr %a, i32 -246 %tmp2 = load i32, ptr %p2, align 247 %tmp3 = add i32 %tmp1, %tmp248 ret i32 %tmp349}50 51; Test sext + zext clustering.52; CHECK: ********** MI Scheduling **********53; CHECK-LABEL: ldp_half_sext_zext_int:%bb.054; CHECK: Cluster ld/st SU(3) - SU(4)55; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui56; CHECK: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui57define i64 @ldp_half_sext_zext_int(ptr %q, ptr %p) nounwind {58 %tmp0 = load i64, ptr %q, align 459 %tmp = load i32, ptr %p, align 460 %add.ptr = getelementptr inbounds i32, ptr %p, i64 161 %tmp1 = load i32, ptr %add.ptr, align 462 %sexttmp = sext i32 %tmp to i6463 %sexttmp1 = zext i32 %tmp1 to i6464 %add = add nsw i64 %sexttmp1, %sexttmp65 %add1 = add nsw i64 %add, %tmp066 ret i64 %add167}68 69; Test zext + sext clustering.70; CHECK: ********** MI Scheduling **********71; CHECK-LABEL: ldp_half_zext_sext_int:%bb.072; CHECK: Cluster ld/st SU(3) - SU(4)73; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui74; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui75define i64 @ldp_half_zext_sext_int(ptr %q, ptr %p) nounwind {76 %tmp0 = load i64, ptr %q, align 477 %tmp = load i32, ptr %p, align 478 %add.ptr = getelementptr inbounds i32, ptr %p, i64 179 %tmp1 = load i32, ptr %add.ptr, align 480 %sexttmp = zext i32 %tmp to i6481 %sexttmp1 = sext i32 %tmp1 to i6482 %add = add nsw i64 %sexttmp1, %sexttmp83 %add1 = add nsw i64 %add, %tmp084 ret i64 %add185}86 87; Verify we don't cluster volatile loads.88; CHECK: ********** MI Scheduling **********89; CHECK-LABEL: ldr_int_volatile:%bb.090; CHECK-NOT: Cluster ld/st91; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui92; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui93define i32 @ldr_int_volatile(ptr %a) nounwind {94 %p1 = getelementptr inbounds i32, ptr %a, i32 195 %tmp1 = load volatile i32, ptr %p1, align 296 %p2 = getelementptr inbounds i32, ptr %a, i32 297 %tmp2 = load volatile i32, ptr %p2, align 298 %tmp3 = add i32 %tmp1, %tmp299 ret i32 %tmp3100}101 102; Test ldq clustering (no clustering for Exynos).103; CHECK: ********** MI Scheduling **********104; CHECK-LABEL: ldq_cluster:%bb.0105; CHECK: Cluster ld/st SU(1) - SU(3)106; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDRQui107; CHECK: SU(3): %{{[0-9]+}}:fpr128 = LDRQui108define <4 x i32> @ldq_cluster(ptr %p) {109 %tmp1 = load <4 x i32>, ptr %p, align 8110 %add.ptr2 = getelementptr inbounds i64, ptr %p, i64 2111 %tmp2 = add nsw <4 x i32> %tmp1, %tmp1112 %tmp3 = load <4 x i32>, ptr %add.ptr2, align 8113 %res = mul nsw <4 x i32> %tmp2, %tmp3114 ret <4 x i32> %res115}116 117; CHECK: ********** MI Scheduling **********118; CHECK: LDURSi_LDRSui:%bb.0 entry119; CHECK: Cluster ld/st SU(3) - SU(4)120; CHECK: SU(3): %3:fpr32 = LDURSi %0:gpr64121; CHECK: SU(4): %4:fpr32 = LDRSui %0:gpr64122;123define void @LDURSi_LDRSui(ptr nocapture readonly %arg, ptr nocapture readonly %wa, ptr nocapture readonly %wb) {124entry:125 %r51 = getelementptr i8, ptr %arg, i64 -4126 %r52 = load float, ptr %r51, align 4127 %r53 = load float, ptr %arg, align 4128 store float %r52, ptr %wa129 store float %r53, ptr %wb130 ret void131}132 133; Test LDURQi / LDRQui clustering134;135; CHECK: ********** MI Scheduling **********136; CHECK: LDURQi_LDRQui:%bb.1 vector_body137;138; CHECK: Cluster ld/st SU(0) - SU(4)139; CHECK: Cluster ld/st SU(1) - SU(5)140;141; CHECK: SU(0): %{{[0-9]+}}:fpr128 = LDURQi142; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDURQi143; CHECK: SU(4): %{{[0-9]+}}:fpr128 = LDRQui144; CHECK: SU(5): %{{[0-9]+}}:fpr128 = LDRQui145;146define void @LDURQi_LDRQui(ptr nocapture readonly %arg) {147entry:148 br label %vector_body149vector_body:150 %phi1 = phi ptr [ null, %entry ], [ %r63, %vector_body ]151 %phi2 = phi ptr [ %arg, %entry ], [ %r62, %vector_body ]152 %phi3 = phi i32 [ 0, %entry ], [ %r61, %vector_body ]153 %r51 = getelementptr i8, ptr %phi1, i64 -16154 %r52 = load <2 x double>, ptr %r51, align 8155 %r53 = getelementptr i8, ptr %phi2, i64 -16156 %r54 = load <2 x double>, ptr %r53, align 8157 %r55 = fmul fast <2 x double> %r54, <double 3.0, double 4.0>158 %r56 = fsub fast <2 x double> %r52, %r55159 store <2 x double> %r56, ptr %r51, align 1160 %r57 = load <2 x double>, ptr %phi1, align 8161 %r58 = load <2 x double>, ptr %phi2, align 8162 %r59 = fmul fast <2 x double> %r58,<double 3.0, double 4.0>163 %r60 = fsub fast <2 x double> %r57, %r59164 store <2 x double> %r60, ptr %phi1, align 1165 %r61 = add i32 %phi3, 4166 %r62 = getelementptr i8, ptr %phi2, i64 32167 %r63 = getelementptr i8, ptr %phi1, i64 32168 %r.not = icmp eq i32 %r61, 0169 br i1 %r.not, label %exit, label %vector_body170exit:171 ret void172}173 174; Test LDURDi / LDRDui clustering175;176; CHECK: ********** MI Scheduling **********177; CHECK: LDURDi_LDRDui:%bb.1 vector_body178;179; CHECK: Cluster ld/st SU(0) - SU(4)180; CHECK: Cluster ld/st SU(1) - SU(5)181;182; CHECK: SU(0): %{{[0-9]+}}:fpr64 = LDURDi183; CHECK: SU(1): %{{[0-9]+}}:fpr64 = LDURDi184; CHECK: SU(4): %{{[0-9]+}}:fpr64 = LDRDui185; CHECK: SU(5): %{{[0-9]+}}:fpr64 = LDRDui186;187define void @LDURDi_LDRDui(ptr nocapture readonly %arg) {188entry:189 br label %vector_body190vector_body:191 %phi1 = phi ptr [ null, %entry ], [ %r63, %vector_body ]192 %phi2 = phi ptr [ %arg, %entry ], [ %r62, %vector_body ]193 %phi3 = phi i32 [ 0, %entry ], [ %r61, %vector_body ]194 %r51 = getelementptr i8, ptr %phi1, i64 -8195 %r52 = load <2 x float>, ptr %r51, align 8196 %r53 = getelementptr i8, ptr %phi2, i64 -8197 %r54 = load <2 x float>, ptr %r53, align 8198 %r55 = fmul fast <2 x float> %r54, <float 3.0, float 4.0>199 %r56 = fsub fast <2 x float> %r52, %r55200 store <2 x float> %r56, ptr %r51, align 1201 %r57 = load <2 x float>, ptr %phi1, align 8202 %r58 = load <2 x float>, ptr %phi2, align 8203 %r59 = fmul fast <2 x float> %r58, <float 3.0, float 4.0>204 %r60 = fsub fast <2 x float> %r57, %r59205 store <2 x float> %r60, ptr %phi1, align 1206 %r61 = add i32 %phi3, 4207 %r62 = getelementptr i8, ptr %phi2, i64 32208 %r63 = getelementptr i8, ptr %phi1, i64 32209 %r.not = icmp eq i32 %r61, 0210 br i1 %r.not, label %exit, label %vector_body211exit:212 ret void213}214 215; CHECK: ********** MI Scheduling **********216; CHECK: LDURXi_LDRXui:%bb.0 entry217; CHECK: Cluster ld/st SU(3) - SU(4)218; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDURXi219; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRXui220;221define void @LDURXi_LDRXui(ptr nocapture readonly %arg, ptr nocapture readonly %wa, ptr nocapture readonly %wb) {222entry:223 %r51 = getelementptr i8, ptr %arg, i64 -8224 %r52 = load i64, ptr %r51, align 8225 %r53 = load i64, ptr %arg, align 8226 store i64 %r52, ptr %wa227 store i64 %r53, ptr %wb228 ret void229}230 231; CHECK: ********** MI Scheduling **********232; CHECK: STURWi_STRWui:%bb.0 entry233; CHECK: Cluster ld/st SU(3) - SU(4)234; CHECK: SU(3): STURWi %{{[0-9]+}}:gpr32235; CHECK: SU(4): STRWui %{{[0-9]+}}:gpr32236;237define void @STURWi_STRWui(ptr nocapture readonly %arg, i32 %b, i32 %c) {238entry:239 %r51 = getelementptr i8, ptr %arg, i64 -4240 store i32 %b, ptr %r51241 store i32 %c, ptr %arg242 ret void243}244 245; CHECK: ********** MI Scheduling **********246; CHECK: STURXi_STRXui:%bb.0 entry247; CHECK: Cluster ld/st SU(3) - SU(4)248; CHECK: SU(3): STURXi %{{[0-9]+}}:gpr64249; CHECK: SU(4): STRXui %{{[0-9]+}}:gpr64250;251define void @STURXi_STRXui(ptr nocapture readonly %arg, i64 %b, i64 %c) {252entry:253 %r51 = getelementptr i8, ptr %arg, i64 -8254 store i64 %b, ptr %r51255 store i64 %c, ptr %arg256 ret void257}258 259; CHECK-A57: ********** MI Scheduling **********260; CHECK-A57: STURSi_STRSui:%bb.0 entry261; CHECK-A57: Cluster ld/st SU(3) - SU(4)262; CHECK-A57: SU(3): STURSi %{{[0-9]+}}:fpr32263; CHECK-A57: SU(4): STRSui %{{[0-9]+}}:fpr32264;265define void @STURSi_STRSui(ptr nocapture readonly %arg, float %b, float %c) {266entry:267 %r51 = getelementptr i8, ptr %arg, i64 -4268 store float %b, ptr %r51269 store float %c, ptr %arg270 ret void271}272 273; CHECK-A57: ********** MI Scheduling **********274; CHECK-A57: STURDi_STRDui:%bb.0 entry275; CHECK-A57: Cluster ld/st SU(3) - SU(4)276; CHECK-A57: SU(3): STURDi %{{[0-9]+}}:fpr64277; CHECK-A57: SU(4): STRDui %{{[0-9]+}}:fpr64278;279define void @STURDi_STRDui(ptr nocapture readonly %arg, <2 x float> %b, <2 x float> %c) {280entry:281 %r51 = getelementptr i8, ptr %arg, i64 -8282 store <2 x float> %b, ptr %r51283 store <2 x float> %c, ptr %arg284 ret void285}286 287; CHECK-A57: ********** MI Scheduling **********288; CHECK-A57: STURQi_STRQui:%bb.0 entry289; CHECK-A57: Cluster ld/st SU(3) - SU(4)290; CHECK-A57: SU(3): STURQi %{{[0-9]+}}:fpr128291; CHECK-A57: SU(4): STRQui %{{[0-9]+}}:fpr128292;293define void @STURQi_STRQui(ptr nocapture readonly %arg, <2 x double> %b, <2 x double> %c) {294entry:295 %r51 = getelementptr i8, ptr %arg, i64 -16296 store <2 x double> %b, ptr %r51297 store <2 x double> %c, ptr %arg298 ret void299}300