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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -disable-machine-dce -o - 2>&1 > /dev/null | FileCheck %s3; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -disable-machine-dce -o - -misched-limit=2 2>&1 > /dev/null | FileCheck %s4;5; The Cortex-A53 machine model will cause the MADD instruction to be scheduled6; much higher than the ADD instructions in order to hide latency. When not7; specifying a subtarget, the MADD will remain near the end of the block.8;9; CHECK: ********** MI Scheduling **********10; CHECK: main11; CHECK: *** Final schedule for %bb.2 ***12; CHECK: MADDWrrr13; CHECK: ADDWri14; CHECK: ********** INTERVALS **********15@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 416@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 417 18; Function Attrs: nounwind19define i32 @main() #0 {20entry:21 %retval = alloca i32, align 422 %x = alloca [8 x i32], align 423 %y = alloca [8 x i32], align 424 %i = alloca i32, align 425 %xx = alloca i32, align 426 %yy = alloca i32, align 427 store i32 0, ptr %retval28 %0 = bitcast ptr %x to ptr29 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 @main.x, i64 32, i1 false)30 %1 = bitcast ptr %y to ptr31 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %1, ptr align 4 @main.y, i64 32, i1 false)32 store i32 0, ptr %xx, align 433 store i32 0, ptr %yy, align 434 store i32 0, ptr %i, align 435 br label %for.cond36 37for.cond: ; preds = %for.inc, %entry38 %2 = load i32, ptr %i, align 439 %cmp = icmp slt i32 %2, 840 br i1 %cmp, label %for.body, label %for.end41 42for.body: ; preds = %for.cond43 %3 = load i32, ptr %i, align 444 %idxprom = sext i32 %3 to i6445 %arrayidx = getelementptr inbounds [8 x i32], ptr %x, i32 0, i64 %idxprom46 %4 = load i32, ptr %arrayidx, align 447 %add = add nsw i32 %4, 148 store i32 %add, ptr %xx, align 449 %5 = load i32, ptr %xx, align 450 %add1 = add nsw i32 %5, 1251 store i32 %add1, ptr %xx, align 452 %6 = load i32, ptr %xx, align 453 %add2 = add nsw i32 %6, 2354 store i32 %add2, ptr %xx, align 455 %7 = load i32, ptr %xx, align 456 %add3 = add nsw i32 %7, 3457 store i32 %add3, ptr %xx, align 458 %8 = load i32, ptr %i, align 459 %idxprom4 = sext i32 %8 to i6460 %arrayidx5 = getelementptr inbounds [8 x i32], ptr %y, i32 0, i64 %idxprom461 %9 = load i32, ptr %arrayidx5, align 462 %10 = load i32, ptr %yy, align 463 %mul = mul nsw i32 %10, %964 store i32 %mul, ptr %yy, align 465 br label %for.inc66 67for.inc: ; preds = %for.body68 %11 = load i32, ptr %i, align 469 %inc = add nsw i32 %11, 170 store i32 %inc, ptr %i, align 471 br label %for.cond72 73for.end: ; preds = %for.cond74 %12 = load i32, ptr %xx, align 475 %13 = load i32, ptr %yy, align 476 %add6 = add nsw i32 %12, %1377 ret i32 %add678}79 80 81; The Cortex-A53 machine model will cause the FDIVvvv_42 to be raised to82; hide latency. Whereas normally there would only be a single FADDvvv_4s83; after it, this test checks to make sure there are more than one.84;85; CHECK: ********** MI Scheduling **********86; CHECK: neon4xfloat:%bb.087; CHECK: *** Final schedule for %bb.0 ***88; CHECK: FDIVv4f3289; CHECK: FADDv4f3290; CHECK: FADDv4f3291; CHECK: ********** INTERVALS **********92define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {93 %tmp1 = fadd <4 x float> %A, %B;94 %tmp2 = fadd <4 x float> %A, %tmp1;95 %tmp3 = fadd <4 x float> %A, %tmp2;96 %tmp4 = fadd <4 x float> %A, %tmp3;97 %tmp5 = fadd <4 x float> %A, %tmp4;98 %tmp6 = fadd <4 x float> %A, %tmp5;99 %tmp7 = fadd <4 x float> %A, %tmp6;100 %tmp8 = fadd <4 x float> %A, %tmp7;101 %tmp9 = fdiv <4 x float> %A, %B;102 %tmp10 = fadd <4 x float> %tmp8, %tmp9;103 104 ret <4 x float> %tmp10105}106 107; Function Attrs: nounwind108declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) #1109 110attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" }111attributes #1 = { nounwind }112 113 114; Regression Test for PR19761115; [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load116;117; Nothing explicit to check other than llc not crashing.118define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(ptr %A, ptr %ptr) {119 %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0(ptr %A)120 %tmp = getelementptr i8, ptr %A, i32 32121 store ptr %tmp, ptr %ptr122 ret { <16 x i8>, <16 x i8> } %ld2123}124 125declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0(ptr)126 127; Regression Test for PR20057.128;129; Cortex-A53 machine model stalls on A53UnitFPMDS contention. Instructions that130; are otherwise ready are jammed in the pending queue.131; CHECK: ********** MI Scheduling **********132; CHECK: testResourceConflict133; CHECK: *** Final schedule for %bb.0 ***134; CHECK: BRK135; CHECK: ********** INTERVALS **********136define void @testResourceConflict(ptr %ptr) {137entry:138 %add1 = fadd float undef, undef139 %mul2 = fmul float undef, undef140 %add3 = fadd float %mul2, undef141 %mul4 = fmul float undef, %add3142 %add5 = fadd float %mul4, undef143 %sub6 = fsub float 0.000000e+00, undef144 %sub7 = fsub float %add5, undef145 %div8 = fdiv float 1.000000e+00, undef146 %mul9 = fmul float %div8, %sub7147 %mul14 = fmul float %sub6, %div8148 %mul10 = fsub float -0.000000e+00, %mul14149 %mul15 = fmul float undef, %div8150 %mul11 = fsub float -0.000000e+00, %mul15151 %mul12 = fmul float 0.000000e+00, %div8152 %mul13 = fmul float %add1, %mul9153 %mul21 = fmul float %add5, %mul11154 %add22 = fadd float %mul13, %mul21155 store float %add22, ptr %ptr, align 4156 %mul28 = fmul float %add1, %mul10157 %mul33 = fmul float %add5, %mul12158 %add34 = fadd float %mul33, %mul28159 store float %add34, ptr %ptr, align 4160 %mul240 = fmul float undef, %mul9161 %add246 = fadd float %mul240, undef162 store float %add246, ptr %ptr, align 4163 %mul52 = fmul float undef, %mul10164 %mul57 = fmul float undef, %mul12165 %add58 = fadd float %mul57, %mul52166 store float %add58, ptr %ptr, align 4167 %mul27 = fmul float 0.000000e+00, %mul9168 %mul81 = fmul float undef, %mul10169 %add82 = fadd float %mul27, %mul81170 store float %add82, ptr %ptr, align 4171 call void @llvm.trap()172 unreachable173}174 175declare void @llvm.trap()176 177; Regression test for PR20057: "permanent hazard"'178; Resource contention on LDST.179; CHECK: ********** MI Scheduling **********180; CHECK: testLdStConflict181; CHECK: *** Final schedule for %bb.1 ***182; CHECK: LD4Fourv2d183; CHECK: STRQui184; CHECK: ********** INTERVALS **********185define void @testLdStConflict(<2 x i64> %v) {186entry:187 br label %loop188 189loop:190 %0 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0(ptr null)191 %ptr = bitcast ptr undef to ptr192 store <2 x i64> %v, ptr %ptr, align 4193 %ptr1 = bitcast ptr undef to ptr194 store <2 x i64> %v, ptr %ptr1, align 4195 %ptr2 = bitcast ptr undef to ptr196 store <2 x i64> %v, ptr %ptr2, align 4197 %ptr3 = bitcast ptr undef to ptr198 store <2 x i64> %v, ptr %ptr3, align 4199 %ptr4 = bitcast ptr undef to ptr200 store <2 x i64> %v, ptr %ptr4, align 4201 br label %loop202}203 204declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0(ptr)205