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1; REQUIRES: asserts2;3; The Cortext-A57 machine model will avoid scheduling load instructions in4; succession because loads on the A57 have a latency of 4 cycles and they all5; issue to the same pipeline. Instead, it will move other instructions between6; the loads to avoid unnecessary stalls. The generic machine model schedules 47; loads consecutively for this case and will cause stalls.8;9; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s10; CHECK: ********** MI Scheduling **********11; CHECK: main:%bb.212; CHECK: LDR13; CHECK: Latency : 414; CHECK: *** Final schedule for %bb.2 ***15; CHECK: LDR16; CHECK: LDR17; CHECK-NOT: LDR18; CHECK: {{.*}}19; CHECK: ********** MI Scheduling **********20 21@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 422@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 423 24; Function Attrs: nounwind25define i32 @main() #0 {26entry:27 %retval = alloca i32, align 428 %x = alloca [8 x i32], align 429 %y = alloca [8 x i32], align 430 %i = alloca i32, align 431 %xx = alloca i32, align 432 %yy = alloca i32, align 433 store i32 0, ptr %retval34 %0 = bitcast ptr %x to ptr35 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 @main.x, i64 32, i1 false)36 %1 = bitcast ptr %y to ptr37 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %1, ptr align 4 @main.y, i64 32, i1 false)38 store i32 0, ptr %xx, align 439 store i32 0, ptr %yy, align 440 store i32 0, ptr %i, align 441 br label %for.cond42 43for.cond: ; preds = %for.inc, %entry44 %2 = load i32, ptr %i, align 445 %cmp = icmp slt i32 %2, 846 br i1 %cmp, label %for.body, label %for.end47 48for.body: ; preds = %for.cond49 %3 = load i32, ptr %yy, align 450 %4 = load i32, ptr %i, align 451 %idxprom = sext i32 %4 to i6452 %arrayidx = getelementptr inbounds [8 x i32], ptr %x, i32 0, i64 %idxprom53 %5 = load i32, ptr %arrayidx, align 454 %add = add nsw i32 %5, 155 store i32 %add, ptr %xx, align 456 %6 = load i32, ptr %xx, align 457 %add1 = add nsw i32 %6, 1258 store i32 %add1, ptr %xx, align 459 %7 = load i32, ptr %xx, align 460 %add2 = add nsw i32 %7, 2361 store i32 %add2, ptr %xx, align 462 %8 = load i32, ptr %xx, align 463 %add3 = add nsw i32 %8, 3464 store i32 %add3, ptr %xx, align 465 %9 = load i32, ptr %i, align 466 %idxprom4 = sext i32 %9 to i6467 %arrayidx5 = getelementptr inbounds [8 x i32], ptr %y, i32 0, i64 %idxprom468 %10 = load i32, ptr %arrayidx5, align 469 70 %add4 = add nsw i32 %9, %add71 %add5 = add nsw i32 %10, %add172 %add6 = add nsw i32 %add4, %add573 74 %add7 = add nsw i32 %9, %add375 %add8 = add nsw i32 %10, %add476 %add9 = add nsw i32 %add7, %add877 78 %add10 = add nsw i32 %9, %add679 %add11 = add nsw i32 %10, %add780 %add12 = add nsw i32 %add10, %add1181 82 %add13 = add nsw i32 %9, %add983 %add14 = add nsw i32 %10, %add1084 %add15 = add nsw i32 %add13, %add1485 86 store i32 %add15, ptr %xx, align 487 88 %div = sdiv i32 %4, %589 90 store i32 %div, ptr %yy, align 491 92 br label %for.inc93 94for.inc: ; preds = %for.body95 %11 = load i32, ptr %i, align 496 %inc = add nsw i32 %11, 197 store i32 %inc, ptr %i, align 498 br label %for.cond99 100for.end: ; preds = %for.cond101 %12 = load i32, ptr %xx, align 4102 %13 = load i32, ptr %yy, align 4103 %add67 = add nsw i32 %12, %13104 ret i32 %add67105}106 107 108; Function Attrs: nounwind109declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) #1110 111attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" }112attributes #1 = { nounwind }113