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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3;4; For Cortex-A53, shiftable operands that are not actually shifted5; are not needed for an additional two cycles.6;7; CHECK: ********** MI Scheduling **********8; CHECK: shiftable9; CHECK: SU(2): %2:gpr64common = SUBXri %1:gpr64common, 20, 010; CHECK: Successors:11; CHECK-NEXT: SU(4): Data Latency=1 Reg=%212; CHECK-NEXT: SU(3): Data Latency=2 Reg=%213; CHECK: ********** INTERVALS **********14define i64 @shiftable(i64 %A, i64 %B) {15 %tmp0 = sub i64 %B, 2016 %tmp1 = shl i64 %tmp0, 5;17 %tmp2 = add i64 %A, %tmp1;18 %tmp3 = add i64 %A, %tmp019 %tmp4 = mul i64 %tmp2, %tmp320 21 ret i64 %tmp422}23