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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; rdar://92968086; rdar://93491377 8define i128 @t1(i64 %a, i64 %b) nounwind readnone ssp {9; CHECK-LABEL: t1:10; CHECK: // %bb.0: // %entry11; CHECK-NEXT: mul x8, x0, x112; CHECK-NEXT: umulh x1, x0, x113; CHECK-NEXT: mov x0, x814; CHECK-NEXT: ret15entry:16 %tmp1 = zext i64 %a to i12817 %tmp2 = zext i64 %b to i12818 %tmp3 = mul i128 %tmp1, %tmp219 ret i128 %tmp320}21 22define i128 @t2(i64 %a, i64 %b) nounwind readnone ssp {23; CHECK-SD-LABEL: t2:24; CHECK-SD: // %bb.0: // %entry25; CHECK-SD-NEXT: mul x8, x0, x126; CHECK-SD-NEXT: smulh x1, x0, x127; CHECK-SD-NEXT: mov x0, x828; CHECK-SD-NEXT: ret29;30; CHECK-GI-LABEL: t2:31; CHECK-GI: // %bb.0: // %entry32; CHECK-GI-NEXT: asr x9, x1, #6333; CHECK-GI-NEXT: asr x10, x0, #6334; CHECK-GI-NEXT: mul x8, x0, x135; CHECK-GI-NEXT: mul x9, x0, x936; CHECK-GI-NEXT: umulh x11, x0, x137; CHECK-GI-NEXT: mov x0, x838; CHECK-GI-NEXT: madd x9, x10, x1, x939; CHECK-GI-NEXT: add x1, x9, x1140; CHECK-GI-NEXT: ret41entry:42 %tmp1 = sext i64 %a to i12843 %tmp2 = sext i64 %b to i12844 %tmp3 = mul i128 %tmp1, %tmp245 ret i128 %tmp346}47 48define i64 @t3(i32 %a, i32 %b) nounwind {49; CHECK-LABEL: t3:50; CHECK: // %bb.0: // %entry51; CHECK-NEXT: umull x0, w0, w152; CHECK-NEXT: ret53entry:54 %tmp1 = zext i32 %a to i6455 %tmp2 = zext i32 %b to i6456 %tmp3 = mul i64 %tmp1, %tmp257 ret i64 %tmp358}59 60define i64 @t4(i32 %a, i32 %b) nounwind {61; CHECK-LABEL: t4:62; CHECK: // %bb.0: // %entry63; CHECK-NEXT: smull x0, w0, w164; CHECK-NEXT: ret65entry:66 %tmp1 = sext i32 %a to i6467 %tmp2 = sext i32 %b to i6468 %tmp3 = mul i64 %tmp1, %tmp269 ret i64 %tmp370}71 72define i64 @t5(i32 %a, i32 %b, i64 %c) nounwind {73; CHECK-LABEL: t5:74; CHECK: // %bb.0: // %entry75; CHECK-NEXT: umaddl x0, w0, w1, x276; CHECK-NEXT: ret77entry:78 %tmp1 = zext i32 %a to i6479 %tmp2 = zext i32 %b to i6480 %tmp3 = mul i64 %tmp1, %tmp281 %tmp4 = add i64 %c, %tmp382 ret i64 %tmp483}84 85define i64 @t6(i32 %a, i32 %b, i64 %c) nounwind {86; CHECK-LABEL: t6:87; CHECK: // %bb.0: // %entry88; CHECK-NEXT: smsubl x0, w0, w1, x289; CHECK-NEXT: ret90entry:91 %tmp1 = sext i32 %a to i6492 %tmp2 = sext i32 %b to i6493 %tmp3 = mul i64 %tmp1, %tmp294 %tmp4 = sub i64 %c, %tmp395 ret i64 %tmp496}97 98define i64 @t7(i32 %a, i32 %b) nounwind {99; CHECK-LABEL: t7:100; CHECK: // %bb.0: // %entry101; CHECK-NEXT: umnegl x0, w0, w1102; CHECK-NEXT: ret103entry:104 %tmp1 = zext i32 %a to i64105 %tmp2 = zext i32 %b to i64106 %tmp3 = mul i64 %tmp1, %tmp2107 %tmp4 = sub i64 0, %tmp3108 ret i64 %tmp4109}110 111define i64 @t8(i32 %a, i32 %b) nounwind {112; CHECK-LABEL: t8:113; CHECK: // %bb.0: // %entry114; CHECK-NEXT: smnegl x0, w0, w1115; CHECK-NEXT: ret116entry:117 %tmp1 = sext i32 %a to i64118 %tmp2 = sext i32 %b to i64119 %tmp3 = mul i64 %tmp1, %tmp2120 %tmp4 = sub i64 0, %tmp3121 ret i64 %tmp4122}123 124define i64 @t9(i32 %a) nounwind {125; CHECK-LABEL: t9:126; CHECK: // %bb.0: // %entry127; CHECK-NEXT: mov w8, #8896 // =0x22c0128; CHECK-NEXT: movk w8, #2, lsl #16129; CHECK-NEXT: umull x0, w0, w8130; CHECK-NEXT: ret131entry:132 %tmp1 = zext i32 %a to i64133 %tmp2 = mul i64 %tmp1, 139968134 ret i64 %tmp2135}136 137; Check 64-bit multiplication is used for constants > 32 bits.138define i64 @t10(i32 %a) nounwind {139; CHECK-LABEL: t10:140; CHECK: // %bb.0: // %entry141; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0142; CHECK-NEXT: sxtw x8, w0143; CHECK-NEXT: mov w9, #2 // =0x2144; CHECK-NEXT: movk w9, #32768, lsl #16145; CHECK-NEXT: mul x0, x8, x9146; CHECK-NEXT: ret147entry:148 %tmp1 = sext i32 %a to i64149 %tmp2 = mul i64 %tmp1, 2147483650 ; = 2^31 + 2150 ret i64 %tmp2151}152 153; Check the sext_inreg case.154define i64 @t11(i64 %a) nounwind {155; CHECK-LABEL: t11:156; CHECK: // %bb.0: // %entry157; CHECK-NEXT: mov w8, #29594 // =0x739a158; CHECK-NEXT: movk w8, #65499, lsl #16159; CHECK-NEXT: smnegl x0, w0, w8160; CHECK-NEXT: ret161entry:162 %tmp1 = trunc i64 %a to i32163 %tmp2 = sext i32 %tmp1 to i64164 %tmp3 = mul i64 %tmp2, -2395238165 %tmp4 = sub i64 0, %tmp3166 ret i64 %tmp4167}168 169define i64 @t12(i64 %a, i64 %b) nounwind {170; CHECK-LABEL: t12:171; CHECK: // %bb.0: // %entry172; CHECK-NEXT: mov w8, #35118 // =0x892e173; CHECK-NEXT: movk w8, #65008, lsl #16174; CHECK-NEXT: smaddl x0, w0, w8, x1175; CHECK-NEXT: ret176entry:177 %tmp1 = trunc i64 %a to i32178 %tmp2 = sext i32 %tmp1 to i64179 %tmp3 = mul i64 %tmp2, -34567890180 %tmp4 = add i64 %b, %tmp3181 ret i64 %tmp4182}183 184define i64 @t13(i32 %a, i64 %b) nounwind {185; CHECK-LABEL: t13:186; CHECK: // %bb.0: // %entry187; CHECK-NEXT: mov w8, #24910 // =0x614e188; CHECK-NEXT: movk w8, #188, lsl #16189; CHECK-NEXT: umsubl x0, w0, w8, x1190; CHECK-NEXT: ret191entry:192 %tmp1 = zext i32 %a to i64193 %tmp3 = mul i64 %tmp1, 12345678194 %tmp4 = sub i64 %b, %tmp3195 ret i64 %tmp4196}197 198define i64 @t14(i32 %a, i64 %b) nounwind {199; CHECK-LABEL: t14:200; CHECK: // %bb.0: // %entry201; CHECK-NEXT: mov w8, #40626 // =0x9eb2202; CHECK-NEXT: movk w8, #65347, lsl #16203; CHECK-NEXT: smsubl x0, w0, w8, x1204; CHECK-NEXT: ret205entry:206 %tmp1 = sext i32 %a to i64207 %tmp3 = mul i64 %tmp1, -12345678208 %tmp4 = sub i64 %b, %tmp3209 ret i64 %tmp4210}211