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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast \3; RUN: < %s -verify-machineinstrs | FileCheck %s4 5define <4 x i32> @test_vmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {6; CHECK-LABEL: test_vmull_high_n_s16:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: dup v1.8h, w09; CHECK-NEXT: smull2 v0.4s, v0.8h, v1.8h10; CHECK-NEXT: ret11entry:12 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>13 %vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 014 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %b, i32 115 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %b, i32 216 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %b, i32 317 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)18 ret <4 x i32> %vmull15.i.i19}20 21define <4 x i32> @test_vmull_high_n_s16_imm(<8 x i16> %a) #0 {22; CHECK-LABEL: test_vmull_high_n_s16_imm:23; CHECK: // %bb.0: // %entry24; CHECK-NEXT: movi v1.8h, #2925; CHECK-NEXT: smull2 v0.4s, v0.8h, v1.8h26; CHECK-NEXT: ret27entry:28 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>29 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)30 ret <4 x i32> %vmull15.i.i31}32 33define <2 x i64> @test_vmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {34; CHECK-LABEL: test_vmull_high_n_s32:35; CHECK: // %bb.0: // %entry36; CHECK-NEXT: dup v1.4s, w037; CHECK-NEXT: smull2 v0.2d, v0.4s, v1.4s38; CHECK-NEXT: ret39entry:40 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>41 %vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 042 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %b, i32 143 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)44 ret <2 x i64> %vmull9.i.i45}46 47define <2 x i64> @test_vmull_high_n_s32_imm(<4 x i32> %a) #0 {48; CHECK-LABEL: test_vmull_high_n_s32_imm:49; CHECK: // %bb.0: // %entry50; CHECK-NEXT: movi v1.4s, #1, msl #851; CHECK-NEXT: smull2 v0.2d, v0.4s, v1.4s52; CHECK-NEXT: ret53entry:54 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>55 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 511, i32 511>)56 ret <2 x i64> %vmull9.i.i57}58 59define <4 x i32> @test_vmull_high_n_u16(<8 x i16> %a, i16 %b) #0 {60; CHECK-LABEL: test_vmull_high_n_u16:61; CHECK: // %bb.0: // %entry62; CHECK-NEXT: dup v1.8h, w063; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h64; CHECK-NEXT: ret65entry:66 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>67 %vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 068 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %b, i32 169 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %b, i32 270 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %b, i32 371 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)72 ret <4 x i32> %vmull15.i.i73}74 75define <4 x i32> @test_vmull_high_n_u16_imm(<8 x i16> %a) #0 {76; CHECK-LABEL: test_vmull_high_n_u16_imm:77; CHECK: // %bb.0: // %entry78; CHECK-NEXT: movi v1.8h, #17, lsl #879; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h80; CHECK-NEXT: ret81entry:82 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>83 %vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 4352, i16 4352, i16 4352, i16 4352>)84 ret <4 x i32> %vmull15.i.i85}86 87define <2 x i64> @test_vmull_high_n_u32(<4 x i32> %a, i32 %b) #0 {88; CHECK-LABEL: test_vmull_high_n_u32:89; CHECK: // %bb.0: // %entry90; CHECK-NEXT: dup v1.4s, w091; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s92; CHECK-NEXT: ret93entry:94 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>95 %vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 096 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %b, i32 197 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)98 ret <2 x i64> %vmull9.i.i99}100 101define <2 x i64> @test_vmull_high_n_u32_imm(<4 x i32> %a) #0 {102; CHECK-LABEL: test_vmull_high_n_u32_imm:103; CHECK: // %bb.0: // %entry104; CHECK-NEXT: mvni v1.4s, #1, msl #8105; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s106; CHECK-NEXT: ret107entry:108 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>109 %vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 4294966784, i32 4294966784>)110 ret <2 x i64> %vmull9.i.i111}112 113define <4 x i32> @test_vqdmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {114; CHECK-LABEL: test_vqdmull_high_n_s16:115; CHECK: // %bb.0: // %entry116; CHECK-NEXT: dup v1.8h, w0117; CHECK-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h118; CHECK-NEXT: ret119entry:120 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>121 %vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0122 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %b, i32 1123 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %b, i32 2124 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %b, i32 3125 %vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)126 ret <4 x i32> %vqdmull15.i.i127}128 129define <4 x i32> @test_vqdmull_high_n_s16_imm(<8 x i16> %a) #0 {130; CHECK-LABEL: test_vqdmull_high_n_s16_imm:131; CHECK: // %bb.0: // %entry132; CHECK-NEXT: mvni v1.8h, #17, lsl #8133; CHECK-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h134; CHECK-NEXT: ret135entry:136 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>137 %vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 61183, i16 61183, i16 61183, i16 61183>)138 ret <4 x i32> %vqdmull15.i.i139}140 141define <2 x i64> @test_vqdmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {142; CHECK-LABEL: test_vqdmull_high_n_s32:143; CHECK: // %bb.0: // %entry144; CHECK-NEXT: dup v1.4s, w0145; CHECK-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s146; CHECK-NEXT: ret147entry:148 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>149 %vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0150 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %b, i32 1151 %vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)152 ret <2 x i64> %vqdmull9.i.i153}154 155define <2 x i64> @test_vqdmull_high_n_s32_imm(<4 x i32> %a) #0 {156; CHECK-LABEL: test_vqdmull_high_n_s32_imm:157; CHECK: // %bb.0: // %entry158; CHECK-NEXT: movi v1.4s, #29159; CHECK-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s160; CHECK-NEXT: ret161entry:162 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>163 %vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)164 ret <2 x i64> %vqdmull9.i.i165}166 167define <4 x i32> @test_vmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {168; CHECK-LABEL: test_vmlal_high_n_s16:169; CHECK: // %bb.0: // %entry170; CHECK-NEXT: dup v2.8h, w0171; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.8h172; CHECK-NEXT: ret173entry:174 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>175 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0176 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1177 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2178 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3179 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)180 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a181 ret <4 x i32> %add.i.i182}183 184define <4 x i32> @test_vmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {185; CHECK-LABEL: test_vmlal_high_n_s16_imm:186; CHECK: // %bb.0: // %entry187; CHECK-NEXT: movi v2.8h, #29188; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.8h189; CHECK-NEXT: ret190entry:191 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>192 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)193 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a194 ret <4 x i32> %add.i.i195}196 197define <2 x i64> @test_vmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {198; CHECK-LABEL: test_vmlal_high_n_s32:199; CHECK: // %bb.0: // %entry200; CHECK-NEXT: dup v2.4s, w0201; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s202; CHECK-NEXT: ret203entry:204 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>205 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0206 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1207 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)208 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a209 ret <2 x i64> %add.i.i210}211 212define <2 x i64> @test_vmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {213; CHECK-LABEL: test_vmlal_high_n_s32_imm:214; CHECK: // %bb.0: // %entry215; CHECK-NEXT: movi v2.4s, #29216; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s217; CHECK-NEXT: ret218entry:219 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>220 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)221 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a222 ret <2 x i64> %add.i.i223}224 225define <4 x i32> @test_vmlal_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {226; CHECK-LABEL: test_vmlal_high_n_u16:227; CHECK: // %bb.0: // %entry228; CHECK-NEXT: dup v2.8h, w0229; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.8h230; CHECK-NEXT: ret231entry:232 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>233 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0234 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1235 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2236 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3237 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)238 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a239 ret <4 x i32> %add.i.i240}241 242define <4 x i32> @test_vmlal_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {243; CHECK-LABEL: test_vmlal_high_n_u16_imm:244; CHECK: // %bb.0: // %entry245; CHECK-NEXT: movi v2.8h, #29246; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.8h247; CHECK-NEXT: ret248entry:249 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>250 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)251 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a252 ret <4 x i32> %add.i.i253}254 255define <2 x i64> @test_vmlal_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {256; CHECK-LABEL: test_vmlal_high_n_u32:257; CHECK: // %bb.0: // %entry258; CHECK-NEXT: dup v2.4s, w0259; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s260; CHECK-NEXT: ret261entry:262 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>263 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0264 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1265 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)266 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a267 ret <2 x i64> %add.i.i268}269 270define <2 x i64> @test_vmlal_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {271; CHECK-LABEL: test_vmlal_high_n_u32_imm:272; CHECK: // %bb.0: // %entry273; CHECK-NEXT: movi v2.4s, #29274; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s275; CHECK-NEXT: ret276entry:277 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>278 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)279 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a280 ret <2 x i64> %add.i.i281}282 283define <4 x i32> @test_vqdmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {284; CHECK-LABEL: test_vqdmlal_high_n_s16:285; CHECK: // %bb.0: // %entry286; CHECK-NEXT: dup v2.8h, w0287; CHECK-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h288; CHECK-NEXT: ret289entry:290 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>291 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0292 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1293 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2294 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3295 %vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)296 %vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.i.i)297 ret <4 x i32> %vqdmlal17.i.i298}299 300define <4 x i32> @test_vqdmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {301; CHECK-LABEL: test_vqdmlal_high_n_s16_imm:302; CHECK: // %bb.0: // %entry303; CHECK-NEXT: movi v2.8h, #29304; CHECK-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h305; CHECK-NEXT: ret306entry:307 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>308 %vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)309 %vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.i.i)310 ret <4 x i32> %vqdmlal17.i.i311}312 313define <2 x i64> @test_vqdmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {314; CHECK-LABEL: test_vqdmlal_high_n_s32:315; CHECK: // %bb.0: // %entry316; CHECK-NEXT: dup v2.4s, w0317; CHECK-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s318; CHECK-NEXT: ret319entry:320 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>321 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0322 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1323 %vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)324 %vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i.i)325 ret <2 x i64> %vqdmlal11.i.i326}327 328define <2 x i64> @test_vqdmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {329; CHECK-LABEL: test_vqdmlal_high_n_s32_imm:330; CHECK: // %bb.0: // %entry331; CHECK-NEXT: movi v2.4s, #29332; CHECK-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s333; CHECK-NEXT: ret334entry:335 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>336 %vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)337 %vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i.i)338 ret <2 x i64> %vqdmlal11.i.i339}340 341define <4 x i32> @test_vmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {342; CHECK-LABEL: test_vmlsl_high_n_s16:343; CHECK: // %bb.0: // %entry344; CHECK-NEXT: dup v2.8h, w0345; CHECK-NEXT: smlsl2 v0.4s, v1.8h, v2.8h346; CHECK-NEXT: ret347entry:348 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>349 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0350 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1351 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2352 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3353 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)354 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i355 ret <4 x i32> %sub.i.i356}357 358define <4 x i32> @test_vmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {359; CHECK-LABEL: test_vmlsl_high_n_s16_imm:360; CHECK: // %bb.0: // %entry361; CHECK-NEXT: movi v2.8h, #29362; CHECK-NEXT: smlsl2 v0.4s, v1.8h, v2.8h363; CHECK-NEXT: ret364entry:365 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>366 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)367 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i368 ret <4 x i32> %sub.i.i369}370 371define <2 x i64> @test_vmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {372; CHECK-LABEL: test_vmlsl_high_n_s32:373; CHECK: // %bb.0: // %entry374; CHECK-NEXT: dup v2.4s, w0375; CHECK-NEXT: smlsl2 v0.2d, v1.4s, v2.4s376; CHECK-NEXT: ret377entry:378 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>379 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0380 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1381 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)382 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i383 ret <2 x i64> %sub.i.i384}385 386define <2 x i64> @test_vmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {387; CHECK-LABEL: test_vmlsl_high_n_s32_imm:388; CHECK: // %bb.0: // %entry389; CHECK-NEXT: movi v2.4s, #29390; CHECK-NEXT: smlsl2 v0.2d, v1.4s, v2.4s391; CHECK-NEXT: ret392entry:393 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>394 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)395 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i396 ret <2 x i64> %sub.i.i397}398 399define <4 x i32> @test_vmlsl_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {400; CHECK-LABEL: test_vmlsl_high_n_u16:401; CHECK: // %bb.0: // %entry402; CHECK-NEXT: dup v2.8h, w0403; CHECK-NEXT: umlsl2 v0.4s, v1.8h, v2.8h404; CHECK-NEXT: ret405entry:406 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>407 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0408 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1409 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2410 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3411 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)412 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i413 ret <4 x i32> %sub.i.i414}415 416define <4 x i32> @test_vmlsl_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {417; CHECK-LABEL: test_vmlsl_high_n_u16_imm:418; CHECK: // %bb.0: // %entry419; CHECK-NEXT: movi v2.8h, #29420; CHECK-NEXT: umlsl2 v0.4s, v1.8h, v2.8h421; CHECK-NEXT: ret422entry:423 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>424 %vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)425 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i426 ret <4 x i32> %sub.i.i427}428 429define <2 x i64> @test_vmlsl_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {430; CHECK-LABEL: test_vmlsl_high_n_u32:431; CHECK: // %bb.0: // %entry432; CHECK-NEXT: dup v2.4s, w0433; CHECK-NEXT: umlsl2 v0.2d, v1.4s, v2.4s434; CHECK-NEXT: ret435entry:436 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>437 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0438 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1439 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)440 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i441 ret <2 x i64> %sub.i.i442}443 444define <2 x i64> @test_vmlsl_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {445; CHECK-LABEL: test_vmlsl_high_n_u32_imm:446; CHECK: // %bb.0: // %entry447; CHECK-NEXT: movi v2.4s, #29448; CHECK-NEXT: umlsl2 v0.2d, v1.4s, v2.4s449; CHECK-NEXT: ret450entry:451 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>452 %vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)453 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i454 ret <2 x i64> %sub.i.i455}456 457define <4 x i32> @test_vqdmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {458; CHECK-LABEL: test_vqdmlsl_high_n_s16:459; CHECK: // %bb.0: // %entry460; CHECK-NEXT: dup v2.8h, w0461; CHECK-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h462; CHECK-NEXT: ret463entry:464 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>465 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0466 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1467 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2468 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3469 %vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)470 %vqdmlsl17.i.i = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.i.i)471 ret <4 x i32> %vqdmlsl17.i.i472}473 474define <4 x i32> @test_vqdmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {475; CHECK-LABEL: test_vqdmlsl_high_n_s16_imm:476; CHECK: // %bb.0: // %entry477; CHECK-NEXT: movi v2.8h, #29478; CHECK-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h479; CHECK-NEXT: ret480entry:481 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>482 %vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)483 %vqdmlsl17.i.i = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.i.i)484 ret <4 x i32> %vqdmlsl17.i.i485}486 487define <2 x i64> @test_vqdmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {488; CHECK-LABEL: test_vqdmlsl_high_n_s32:489; CHECK: // %bb.0: // %entry490; CHECK-NEXT: dup v2.4s, w0491; CHECK-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s492; CHECK-NEXT: ret493entry:494 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>495 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0496 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1497 %vqdmlsl9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)498 %vqdmlsl11.i.i = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i.i)499 ret <2 x i64> %vqdmlsl11.i.i500}501 502define <2 x i64> @test_vqdmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {503; CHECK-LABEL: test_vqdmlsl_high_n_s32_imm:504; CHECK: // %bb.0: // %entry505; CHECK-NEXT: movi v2.4s, #29506; CHECK-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s507; CHECK-NEXT: ret508entry:509 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>510 %vqdmlsl9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)511 %vqdmlsl11.i.i = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i.i)512 ret <2 x i64> %vqdmlsl11.i.i513}514 515define <2 x float> @test_vmul_n_f32(<2 x float> %a, float %b) #0 {516; CHECK-LABEL: test_vmul_n_f32:517; CHECK: // %bb.0: // %entry518; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1519; CHECK-NEXT: fmul v0.2s, v0.2s, v1.s[0]520; CHECK-NEXT: ret521entry:522 %vecinit.i = insertelement <2 x float> undef, float %b, i32 0523 %vecinit1.i = insertelement <2 x float> %vecinit.i, float %b, i32 1524 %mul.i = fmul <2 x float> %vecinit1.i, %a525 ret <2 x float> %mul.i526}527 528define <4 x float> @test_vmulq_n_f32(<4 x float> %a, float %b) #0 {529; CHECK-LABEL: test_vmulq_n_f32:530; CHECK: // %bb.0: // %entry531; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1532; CHECK-NEXT: fmul v0.4s, v0.4s, v1.s[0]533; CHECK-NEXT: ret534entry:535 %vecinit.i = insertelement <4 x float> undef, float %b, i32 0536 %vecinit1.i = insertelement <4 x float> %vecinit.i, float %b, i32 1537 %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %b, i32 2538 %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %b, i32 3539 %mul.i = fmul <4 x float> %vecinit3.i, %a540 ret <4 x float> %mul.i541}542 543define <2 x double> @test_vmulq_n_f64(<2 x double> %a, double %b) #0 {544; CHECK-LABEL: test_vmulq_n_f64:545; CHECK: // %bb.0: // %entry546; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1547; CHECK-NEXT: fmul v0.2d, v0.2d, v1.d[0]548; CHECK-NEXT: ret549entry:550 %vecinit.i = insertelement <2 x double> undef, double %b, i32 0551 %vecinit1.i = insertelement <2 x double> %vecinit.i, double %b, i32 1552 %mul.i = fmul <2 x double> %vecinit1.i, %a553 ret <2 x double> %mul.i554}555 556define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {557; CHECK-LABEL: test_vfma_n_f32:558; CHECK: // %bb.0: // %entry559; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2560; CHECK-NEXT: fmla v0.2s, v1.2s, v2.s[0]561; CHECK-NEXT: ret562entry:563 %vecinit.i = insertelement <2 x float> undef, float %n, i32 0564 %vecinit1.i = insertelement <2 x float> %vecinit.i, float %n, i32 1565 %0 = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> %vecinit1.i, <2 x float> %a)566 ret <2 x float> %0567}568 569define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 {570; CHECK-LABEL: test_vfmaq_n_f32:571; CHECK: // %bb.0: // %entry572; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2573; CHECK-NEXT: fmla v0.4s, v1.4s, v2.s[0]574; CHECK-NEXT: ret575entry:576 %vecinit.i = insertelement <4 x float> undef, float %n, i32 0577 %vecinit1.i = insertelement <4 x float> %vecinit.i, float %n, i32 1578 %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %n, i32 2579 %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %n, i32 3580 %0 = call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %vecinit3.i, <4 x float> %a)581 ret <4 x float> %0582}583 584define <2 x float> @test_vfms_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {585; CHECK-LABEL: test_vfms_n_f32:586; CHECK: // %bb.0: // %entry587; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2588; CHECK-NEXT: fmls v0.2s, v1.2s, v2.s[0]589; CHECK-NEXT: ret590entry:591 %vecinit.i = insertelement <2 x float> undef, float %n, i32 0592 %vecinit1.i = insertelement <2 x float> %vecinit.i, float %n, i32 1593 %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %b594 %1 = call <2 x float> @llvm.fma.v2f32(<2 x float> %0, <2 x float> %vecinit1.i, <2 x float> %a)595 ret <2 x float> %1596}597 598define <4 x float> @test_vfmsq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 {599; CHECK-LABEL: test_vfmsq_n_f32:600; CHECK: // %bb.0: // %entry601; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2602; CHECK-NEXT: fmls v0.4s, v1.4s, v2.s[0]603; CHECK-NEXT: ret604entry:605 %vecinit.i = insertelement <4 x float> undef, float %n, i32 0606 %vecinit1.i = insertelement <4 x float> %vecinit.i, float %n, i32 1607 %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %n, i32 2608 %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %n, i32 3609 %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %b610 %1 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %vecinit3.i, <4 x float> %a)611 ret <4 x float> %1612}613 614attributes #0 = { nounwind }615 616declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)617declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)618declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>)619declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)620declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)621declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)622declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)623declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)624declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)625declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)626declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)627declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)628