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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon,+aes | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon,+aes -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)6declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) #57declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)8declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)9declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)10declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)11declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)12declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)13declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)14declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>)15declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>)16declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)17declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)18declare <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8>, <8 x i8>)19declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>)20declare <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16>, <4 x i16>)21declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)22declare <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32>, <2 x i32>)23declare <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16>, <4 x i16>)24declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>)25declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>)26declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>)27declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>)28declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)29declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)30declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)31 32define void @test_commutable_vaddl_s8(<8 x i8> %a, <8 x i8> %b, ptr %c) {33; CHECK-LABEL: test_commutable_vaddl_s8:34; CHECK: // %bb.0: // %entry35; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b36; CHECK-NEXT: stp q0, q0, [x0]37; CHECK-NEXT: ret38entry:39 %vmovl.i.i = sext <8 x i8> %a to <8 x i16>40 %vmovl.i2.i = sext <8 x i8> %b to <8 x i16>41 %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i42 store <8 x i16> %add.i, ptr %c43 %add.i2 = add <8 x i16> %vmovl.i2.i, %vmovl.i.i44 %c.gep.1 = getelementptr i8, ptr %c, i64 1645 store <8 x i16> %add.i2, ptr %c.gep.146 ret void47}48 49define void @test_commutable_vaddl_u8(<8 x i8> %a, <8 x i8> %b, ptr %c) {50; CHECK-LABEL: test_commutable_vaddl_u8:51; CHECK: // %bb.0: // %entry52; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b53; CHECK-NEXT: stp q0, q0, [x0]54; CHECK-NEXT: ret55entry:56 %vmovl.i.i = zext <8 x i8> %a to <8 x i16>57 %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>58 %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i59 store <8 x i16> %add.i, ptr %c60 %add.i2 = add <8 x i16> %vmovl.i2.i, %vmovl.i.i61 %c.gep.1 = getelementptr i8, ptr %c, i64 1662 store <8 x i16> %add.i2, ptr %c.gep.163 ret void64}65 66define <8 x i16> @test_vaddl_a8(<8 x i8> %a, <8 x i8> %b) {67; CHECK-SD-LABEL: test_vaddl_a8:68; CHECK-SD: // %bb.0: // %entry69; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b70; CHECK-SD-NEXT: bic v0.8h, #255, lsl #871; CHECK-SD-NEXT: ret72;73; CHECK-GI-LABEL: test_vaddl_a8:74; CHECK-GI: // %bb.0: // %entry75; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff76; CHECK-GI-NEXT: uaddl v0.8h, v0.8b, v1.8b77; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b78; CHECK-GI-NEXT: ret79entry:80 %vmovl.i.i = zext <8 x i8> %a to <8 x i16>81 %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>82 %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i83 %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>84 ret <8 x i16> %and85}86 87define <4 x i32> @test_vaddl_a16(<4 x i16> %a, <4 x i16> %b) {88; CHECK-LABEL: test_vaddl_a16:89; CHECK: // %bb.0: // %entry90; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff91; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h92; CHECK-NEXT: and v0.16b, v0.16b, v2.16b93; CHECK-NEXT: ret94entry:95 %vmovl.i.i = zext <4 x i16> %a to <4 x i32>96 %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>97 %add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i98 %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>99 ret <4 x i32> %and100}101 102define <2 x i64> @test_vaddl_a32(<2 x i32> %a, <2 x i32> %b) {103; CHECK-LABEL: test_vaddl_a32:104; CHECK: // %bb.0: // %entry105; CHECK-NEXT: movi v2.2d, #0x000000ffffffff106; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s107; CHECK-NEXT: and v0.16b, v0.16b, v2.16b108; CHECK-NEXT: ret109entry:110 %vmovl.i.i = zext <2 x i32> %a to <2 x i64>111 %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>112 %add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i113 %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>114 ret <2 x i64> %and115}116 117define <8 x i16> @test_vaddl_high_s8(<16 x i8> %a, <16 x i8> %b) {118; CHECK-LABEL: test_vaddl_high_s8:119; CHECK: // %bb.0: // %entry120; CHECK-NEXT: saddl2 v0.8h, v0.16b, v1.16b121; CHECK-NEXT: ret122entry:123 %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>124 %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>125 %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>126 %1 = sext <8 x i8> %shuffle.i.i2.i to <8 x i16>127 %add.i = add <8 x i16> %0, %1128 ret <8 x i16> %add.i129}130 131define <4 x i32> @test_vaddl_high_s16(<8 x i16> %a, <8 x i16> %b) {132; CHECK-LABEL: test_vaddl_high_s16:133; CHECK: // %bb.0: // %entry134; CHECK-NEXT: saddl2 v0.4s, v0.8h, v1.8h135; CHECK-NEXT: ret136entry:137 %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>138 %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>139 %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>140 %1 = sext <4 x i16> %shuffle.i.i2.i to <4 x i32>141 %add.i = add <4 x i32> %0, %1142 ret <4 x i32> %add.i143}144 145define <2 x i64> @test_vaddl_high_s32(<4 x i32> %a, <4 x i32> %b) {146; CHECK-LABEL: test_vaddl_high_s32:147; CHECK: // %bb.0: // %entry148; CHECK-NEXT: saddl2 v0.2d, v0.4s, v1.4s149; CHECK-NEXT: ret150entry:151 %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>152 %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>153 %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>154 %1 = sext <2 x i32> %shuffle.i.i2.i to <2 x i64>155 %add.i = add <2 x i64> %0, %1156 ret <2 x i64> %add.i157}158 159define <8 x i16> @test_vaddl_high_u8(<16 x i8> %a, <16 x i8> %b) {160; CHECK-LABEL: test_vaddl_high_u8:161; CHECK: // %bb.0: // %entry162; CHECK-NEXT: uaddl2 v0.8h, v0.16b, v1.16b163; CHECK-NEXT: ret164entry:165 %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>166 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>167 %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>168 %1 = zext <8 x i8> %shuffle.i.i2.i to <8 x i16>169 %add.i = add <8 x i16> %0, %1170 ret <8 x i16> %add.i171}172 173define <4 x i32> @test_vaddl_high_u16(<8 x i16> %a, <8 x i16> %b) {174; CHECK-LABEL: test_vaddl_high_u16:175; CHECK: // %bb.0: // %entry176; CHECK-NEXT: uaddl2 v0.4s, v0.8h, v1.8h177; CHECK-NEXT: ret178entry:179 %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>180 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>181 %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>182 %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>183 %add.i = add <4 x i32> %0, %1184 ret <4 x i32> %add.i185}186 187define <2 x i64> @test_vaddl_high_u32(<4 x i32> %a, <4 x i32> %b) {188; CHECK-LABEL: test_vaddl_high_u32:189; CHECK: // %bb.0: // %entry190; CHECK-NEXT: uaddl2 v0.2d, v0.4s, v1.4s191; CHECK-NEXT: ret192entry:193 %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>194 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>195 %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>196 %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>197 %add.i = add <2 x i64> %0, %1198 ret <2 x i64> %add.i199}200 201define <8 x i16> @test_vaddl_high_a8(<16 x i8> %a, <16 x i8> %b) {202; CHECK-SD-LABEL: test_vaddl_high_a8:203; CHECK-SD: // %bb.0: // %entry204; CHECK-SD-NEXT: uaddl2 v0.8h, v0.16b, v1.16b205; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8206; CHECK-SD-NEXT: ret207;208; CHECK-GI-LABEL: test_vaddl_high_a8:209; CHECK-GI: // %bb.0: // %entry210; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff211; CHECK-GI-NEXT: uaddl2 v0.8h, v0.16b, v1.16b212; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b213; CHECK-GI-NEXT: ret214entry:215 %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>216 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>217 %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>218 %1 = zext <8 x i8> %shuffle.i.i2.i to <8 x i16>219 %add.i = add <8 x i16> %0, %1220 %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>221 ret <8 x i16> %and222}223 224define <4 x i32> @test_vaddl_high_a16(<8 x i16> %a, <8 x i16> %b) {225; CHECK-LABEL: test_vaddl_high_a16:226; CHECK: // %bb.0: // %entry227; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff228; CHECK-NEXT: uaddl2 v0.4s, v0.8h, v1.8h229; CHECK-NEXT: and v0.16b, v0.16b, v2.16b230; CHECK-NEXT: ret231entry:232 %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>233 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>234 %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>235 %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>236 %add.i = add <4 x i32> %0, %1237 %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>238 ret <4 x i32> %and239}240 241define <2 x i64> @test_vaddl_high_a32(<4 x i32> %a, <4 x i32> %b) {242; CHECK-LABEL: test_vaddl_high_a32:243; CHECK: // %bb.0: // %entry244; CHECK-NEXT: movi v2.2d, #0x000000ffffffff245; CHECK-NEXT: uaddl2 v0.2d, v0.4s, v1.4s246; CHECK-NEXT: and v0.16b, v0.16b, v2.16b247; CHECK-NEXT: ret248entry:249 %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>250 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>251 %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>252 %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>253 %add.i = add <2 x i64> %0, %1254 %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>255 ret <2 x i64> %and256}257 258define <8 x i16> @test_vaddw_s8(<8 x i16> %a, <8 x i8> %b) {259; CHECK-LABEL: test_vaddw_s8:260; CHECK: // %bb.0: // %entry261; CHECK-NEXT: saddw v0.8h, v0.8h, v1.8b262; CHECK-NEXT: ret263entry:264 %vmovl.i.i = sext <8 x i8> %b to <8 x i16>265 %add.i = add <8 x i16> %vmovl.i.i, %a266 ret <8 x i16> %add.i267}268 269define <4 x i32> @test_vaddw_s16(<4 x i32> %a, <4 x i16> %b) {270; CHECK-LABEL: test_vaddw_s16:271; CHECK: // %bb.0: // %entry272; CHECK-NEXT: saddw v0.4s, v0.4s, v1.4h273; CHECK-NEXT: ret274entry:275 %vmovl.i.i = sext <4 x i16> %b to <4 x i32>276 %add.i = add <4 x i32> %vmovl.i.i, %a277 ret <4 x i32> %add.i278}279 280define <2 x i64> @test_vaddw_s32(<2 x i64> %a, <2 x i32> %b) {281; CHECK-LABEL: test_vaddw_s32:282; CHECK: // %bb.0: // %entry283; CHECK-NEXT: saddw v0.2d, v0.2d, v1.2s284; CHECK-NEXT: ret285entry:286 %vmovl.i.i = sext <2 x i32> %b to <2 x i64>287 %add.i = add <2 x i64> %vmovl.i.i, %a288 ret <2 x i64> %add.i289}290 291define <8 x i16> @test_vaddw_u8(<8 x i16> %a, <8 x i8> %b) {292; CHECK-LABEL: test_vaddw_u8:293; CHECK: // %bb.0: // %entry294; CHECK-NEXT: uaddw v0.8h, v0.8h, v1.8b295; CHECK-NEXT: ret296entry:297 %vmovl.i.i = zext <8 x i8> %b to <8 x i16>298 %add.i = add <8 x i16> %vmovl.i.i, %a299 ret <8 x i16> %add.i300}301 302define <4 x i32> @test_vaddw_u16(<4 x i32> %a, <4 x i16> %b) {303; CHECK-LABEL: test_vaddw_u16:304; CHECK: // %bb.0: // %entry305; CHECK-NEXT: uaddw v0.4s, v0.4s, v1.4h306; CHECK-NEXT: ret307entry:308 %vmovl.i.i = zext <4 x i16> %b to <4 x i32>309 %add.i = add <4 x i32> %vmovl.i.i, %a310 ret <4 x i32> %add.i311}312 313define <2 x i64> @test_vaddw_u32(<2 x i64> %a, <2 x i32> %b) {314; CHECK-LABEL: test_vaddw_u32:315; CHECK: // %bb.0: // %entry316; CHECK-NEXT: uaddw v0.2d, v0.2d, v1.2s317; CHECK-NEXT: ret318entry:319 %vmovl.i.i = zext <2 x i32> %b to <2 x i64>320 %add.i = add <2 x i64> %vmovl.i.i, %a321 ret <2 x i64> %add.i322}323 324define <8 x i16> @test_vaddw_a8(<8 x i16> %a, <8 x i8> %b) {325; CHECK-SD-LABEL: test_vaddw_a8:326; CHECK-SD: // %bb.0: // %entry327; CHECK-SD-NEXT: uaddw v0.8h, v0.8h, v1.8b328; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8329; CHECK-SD-NEXT: ret330;331; CHECK-GI-LABEL: test_vaddw_a8:332; CHECK-GI: // %bb.0: // %entry333; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff334; CHECK-GI-NEXT: uaddw v0.8h, v0.8h, v1.8b335; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b336; CHECK-GI-NEXT: ret337entry:338 %vmovl.i.i = zext <8 x i8> %b to <8 x i16>339 %add.i = add <8 x i16> %vmovl.i.i, %a340 %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>341 ret <8 x i16> %and342}343 344define <4 x i32> @test_vaddw_a16(<4 x i32> %a, <4 x i16> %b) {345; CHECK-LABEL: test_vaddw_a16:346; CHECK: // %bb.0: // %entry347; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff348; CHECK-NEXT: uaddw v0.4s, v0.4s, v1.4h349; CHECK-NEXT: and v0.16b, v0.16b, v2.16b350; CHECK-NEXT: ret351entry:352 %vmovl.i.i = zext <4 x i16> %b to <4 x i32>353 %add.i = add <4 x i32> %vmovl.i.i, %a354 %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>355 ret <4 x i32> %and356}357 358define <2 x i64> @test_vaddw_a32(<2 x i64> %a, <2 x i32> %b) {359; CHECK-LABEL: test_vaddw_a32:360; CHECK: // %bb.0: // %entry361; CHECK-NEXT: movi v2.2d, #0x000000ffffffff362; CHECK-NEXT: uaddw v0.2d, v0.2d, v1.2s363; CHECK-NEXT: and v0.16b, v0.16b, v2.16b364; CHECK-NEXT: ret365entry:366 %vmovl.i.i = zext <2 x i32> %b to <2 x i64>367 %add.i = add <2 x i64> %vmovl.i.i, %a368 %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>369 ret <2 x i64> %and370}371 372define <8 x i16> @test_vaddw_high_s8(<8 x i16> %a, <16 x i8> %b) {373; CHECK-LABEL: test_vaddw_high_s8:374; CHECK: // %bb.0: // %entry375; CHECK-NEXT: saddw2 v0.8h, v0.8h, v1.16b376; CHECK-NEXT: ret377entry:378 %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>379 %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>380 %add.i = add <8 x i16> %0, %a381 ret <8 x i16> %add.i382}383 384define <4 x i32> @test_vaddw_high_s16(<4 x i32> %a, <8 x i16> %b) {385; CHECK-LABEL: test_vaddw_high_s16:386; CHECK: // %bb.0: // %entry387; CHECK-NEXT: saddw2 v0.4s, v0.4s, v1.8h388; CHECK-NEXT: ret389entry:390 %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>391 %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>392 %add.i = add <4 x i32> %0, %a393 ret <4 x i32> %add.i394}395 396define <2 x i64> @test_vaddw_high_s32(<2 x i64> %a, <4 x i32> %b) {397; CHECK-LABEL: test_vaddw_high_s32:398; CHECK: // %bb.0: // %entry399; CHECK-NEXT: saddw2 v0.2d, v0.2d, v1.4s400; CHECK-NEXT: ret401entry:402 %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>403 %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>404 %add.i = add <2 x i64> %0, %a405 ret <2 x i64> %add.i406}407 408define <8 x i16> @test_vaddw_high_u8(<8 x i16> %a, <16 x i8> %b) {409; CHECK-LABEL: test_vaddw_high_u8:410; CHECK: // %bb.0: // %entry411; CHECK-NEXT: uaddw2 v0.8h, v0.8h, v1.16b412; CHECK-NEXT: ret413entry:414 %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>415 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>416 %add.i = add <8 x i16> %0, %a417 ret <8 x i16> %add.i418}419 420define <4 x i32> @test_vaddw_high_u16(<4 x i32> %a, <8 x i16> %b) {421; CHECK-LABEL: test_vaddw_high_u16:422; CHECK: // %bb.0: // %entry423; CHECK-NEXT: uaddw2 v0.4s, v0.4s, v1.8h424; CHECK-NEXT: ret425entry:426 %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>427 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>428 %add.i = add <4 x i32> %0, %a429 ret <4 x i32> %add.i430}431 432define <2 x i64> @test_vaddw_high_u32(<2 x i64> %a, <4 x i32> %b) {433; CHECK-LABEL: test_vaddw_high_u32:434; CHECK: // %bb.0: // %entry435; CHECK-NEXT: uaddw2 v0.2d, v0.2d, v1.4s436; CHECK-NEXT: ret437entry:438 %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>439 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>440 %add.i = add <2 x i64> %0, %a441 ret <2 x i64> %add.i442}443 444define <8 x i16> @test_vaddw_high_a8(<8 x i16> %a, <16 x i8> %b) {445; CHECK-SD-LABEL: test_vaddw_high_a8:446; CHECK-SD: // %bb.0: // %entry447; CHECK-SD-NEXT: uaddw2 v0.8h, v0.8h, v1.16b448; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8449; CHECK-SD-NEXT: ret450;451; CHECK-GI-LABEL: test_vaddw_high_a8:452; CHECK-GI: // %bb.0: // %entry453; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff454; CHECK-GI-NEXT: uaddw2 v0.8h, v0.8h, v1.16b455; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b456; CHECK-GI-NEXT: ret457entry:458 %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>459 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>460 %add.i = add <8 x i16> %0, %a461 %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>462 ret <8 x i16> %and463}464 465define <4 x i32> @test_vaddw_high_a16(<4 x i32> %a, <8 x i16> %b) {466; CHECK-LABEL: test_vaddw_high_a16:467; CHECK: // %bb.0: // %entry468; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff469; CHECK-NEXT: uaddw2 v0.4s, v0.4s, v1.8h470; CHECK-NEXT: and v0.16b, v0.16b, v2.16b471; CHECK-NEXT: ret472entry:473 %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>474 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>475 %add.i = add <4 x i32> %0, %a476 %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>477 ret <4 x i32> %and478}479 480define <2 x i64> @test_vaddw_high_a32(<2 x i64> %a, <4 x i32> %b) {481; CHECK-LABEL: test_vaddw_high_a32:482; CHECK: // %bb.0: // %entry483; CHECK-NEXT: movi v2.2d, #0x000000ffffffff484; CHECK-NEXT: uaddw2 v0.2d, v0.2d, v1.4s485; CHECK-NEXT: and v0.16b, v0.16b, v2.16b486; CHECK-NEXT: ret487entry:488 %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>489 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>490 %add.i = add <2 x i64> %0, %a491 %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>492 ret <2 x i64> %and493}494 495define <8 x i16> @test_vsubl_s8(<8 x i8> %a, <8 x i8> %b) {496; CHECK-LABEL: test_vsubl_s8:497; CHECK: // %bb.0: // %entry498; CHECK-NEXT: ssubl v0.8h, v0.8b, v1.8b499; CHECK-NEXT: ret500entry:501 %vmovl.i.i = sext <8 x i8> %a to <8 x i16>502 %vmovl.i2.i = sext <8 x i8> %b to <8 x i16>503 %sub.i = sub <8 x i16> %vmovl.i.i, %vmovl.i2.i504 ret <8 x i16> %sub.i505}506 507define <4 x i32> @test_vsubl_s16(<4 x i16> %a, <4 x i16> %b) {508; CHECK-LABEL: test_vsubl_s16:509; CHECK: // %bb.0: // %entry510; CHECK-NEXT: ssubl v0.4s, v0.4h, v1.4h511; CHECK-NEXT: ret512entry:513 %vmovl.i.i = sext <4 x i16> %a to <4 x i32>514 %vmovl.i2.i = sext <4 x i16> %b to <4 x i32>515 %sub.i = sub <4 x i32> %vmovl.i.i, %vmovl.i2.i516 ret <4 x i32> %sub.i517}518 519define <2 x i64> @test_vsubl_s32(<2 x i32> %a, <2 x i32> %b) {520; CHECK-LABEL: test_vsubl_s32:521; CHECK: // %bb.0: // %entry522; CHECK-NEXT: ssubl v0.2d, v0.2s, v1.2s523; CHECK-NEXT: ret524entry:525 %vmovl.i.i = sext <2 x i32> %a to <2 x i64>526 %vmovl.i2.i = sext <2 x i32> %b to <2 x i64>527 %sub.i = sub <2 x i64> %vmovl.i.i, %vmovl.i2.i528 ret <2 x i64> %sub.i529}530 531define <8 x i16> @test_vsubl_u8(<8 x i8> %a, <8 x i8> %b) {532; CHECK-LABEL: test_vsubl_u8:533; CHECK: // %bb.0: // %entry534; CHECK-NEXT: usubl v0.8h, v0.8b, v1.8b535; CHECK-NEXT: ret536entry:537 %vmovl.i.i = zext <8 x i8> %a to <8 x i16>538 %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>539 %sub.i = sub <8 x i16> %vmovl.i.i, %vmovl.i2.i540 ret <8 x i16> %sub.i541}542 543define <4 x i32> @test_vsubl_u16(<4 x i16> %a, <4 x i16> %b) {544; CHECK-LABEL: test_vsubl_u16:545; CHECK: // %bb.0: // %entry546; CHECK-NEXT: usubl v0.4s, v0.4h, v1.4h547; CHECK-NEXT: ret548entry:549 %vmovl.i.i = zext <4 x i16> %a to <4 x i32>550 %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>551 %sub.i = sub <4 x i32> %vmovl.i.i, %vmovl.i2.i552 ret <4 x i32> %sub.i553}554 555define <2 x i64> @test_vsubl_u32(<2 x i32> %a, <2 x i32> %b) {556; CHECK-LABEL: test_vsubl_u32:557; CHECK: // %bb.0: // %entry558; CHECK-NEXT: usubl v0.2d, v0.2s, v1.2s559; CHECK-NEXT: ret560entry:561 %vmovl.i.i = zext <2 x i32> %a to <2 x i64>562 %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>563 %sub.i = sub <2 x i64> %vmovl.i.i, %vmovl.i2.i564 ret <2 x i64> %sub.i565}566 567define <8 x i16> @test_vsubl_a8(<8 x i8> %a, <8 x i8> %b) {568; CHECK-SD-LABEL: test_vsubl_a8:569; CHECK-SD: // %bb.0: // %entry570; CHECK-SD-NEXT: usubl v0.8h, v0.8b, v1.8b571; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8572; CHECK-SD-NEXT: ret573;574; CHECK-GI-LABEL: test_vsubl_a8:575; CHECK-GI: // %bb.0: // %entry576; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff577; CHECK-GI-NEXT: usubl v0.8h, v0.8b, v1.8b578; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b579; CHECK-GI-NEXT: ret580entry:581 %vmovl.i.i = zext <8 x i8> %a to <8 x i16>582 %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>583 %sub.i = sub <8 x i16> %vmovl.i.i, %vmovl.i2.i584 %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>585 ret <8 x i16> %and586}587 588define <4 x i32> @test_vsubl_a16(<4 x i16> %a, <4 x i16> %b) {589; CHECK-LABEL: test_vsubl_a16:590; CHECK: // %bb.0: // %entry591; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff592; CHECK-NEXT: usubl v0.4s, v0.4h, v1.4h593; CHECK-NEXT: and v0.16b, v0.16b, v2.16b594; CHECK-NEXT: ret595entry:596 %vmovl.i.i = zext <4 x i16> %a to <4 x i32>597 %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>598 %sub.i = sub <4 x i32> %vmovl.i.i, %vmovl.i2.i599 %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>600 ret <4 x i32> %and601}602 603define <2 x i64> @test_vsubl_a32(<2 x i32> %a, <2 x i32> %b) {604; CHECK-LABEL: test_vsubl_a32:605; CHECK: // %bb.0: // %entry606; CHECK-NEXT: movi v2.2d, #0x000000ffffffff607; CHECK-NEXT: usubl v0.2d, v0.2s, v1.2s608; CHECK-NEXT: and v0.16b, v0.16b, v2.16b609; CHECK-NEXT: ret610entry:611 %vmovl.i.i = zext <2 x i32> %a to <2 x i64>612 %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>613 %sub.i = sub <2 x i64> %vmovl.i.i, %vmovl.i2.i614 %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>615 ret <2 x i64> %and616}617 618define <8 x i16> @test_vsubl_high_s8(<16 x i8> %a, <16 x i8> %b) {619; CHECK-LABEL: test_vsubl_high_s8:620; CHECK: // %bb.0: // %entry621; CHECK-NEXT: ssubl2 v0.8h, v0.16b, v1.16b622; CHECK-NEXT: ret623entry:624 %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>625 %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>626 %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>627 %1 = sext <8 x i8> %shuffle.i.i2.i to <8 x i16>628 %sub.i = sub <8 x i16> %0, %1629 ret <8 x i16> %sub.i630}631 632define <4 x i32> @test_vsubl_high_s16(<8 x i16> %a, <8 x i16> %b) {633; CHECK-LABEL: test_vsubl_high_s16:634; CHECK: // %bb.0: // %entry635; CHECK-NEXT: ssubl2 v0.4s, v0.8h, v1.8h636; CHECK-NEXT: ret637entry:638 %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>639 %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>640 %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>641 %1 = sext <4 x i16> %shuffle.i.i2.i to <4 x i32>642 %sub.i = sub <4 x i32> %0, %1643 ret <4 x i32> %sub.i644}645 646define <2 x i64> @test_vsubl_high_s32(<4 x i32> %a, <4 x i32> %b) {647; CHECK-LABEL: test_vsubl_high_s32:648; CHECK: // %bb.0: // %entry649; CHECK-NEXT: ssubl2 v0.2d, v0.4s, v1.4s650; CHECK-NEXT: ret651entry:652 %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>653 %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>654 %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>655 %1 = sext <2 x i32> %shuffle.i.i2.i to <2 x i64>656 %sub.i = sub <2 x i64> %0, %1657 ret <2 x i64> %sub.i658}659 660define <8 x i16> @test_vsubl_high_u8(<16 x i8> %a, <16 x i8> %b) {661; CHECK-LABEL: test_vsubl_high_u8:662; CHECK: // %bb.0: // %entry663; CHECK-NEXT: usubl2 v0.8h, v0.16b, v1.16b664; CHECK-NEXT: ret665entry:666 %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>667 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>668 %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>669 %1 = zext <8 x i8> %shuffle.i.i2.i to <8 x i16>670 %sub.i = sub <8 x i16> %0, %1671 ret <8 x i16> %sub.i672}673 674define <4 x i32> @test_vsubl_high_u16(<8 x i16> %a, <8 x i16> %b) {675; CHECK-LABEL: test_vsubl_high_u16:676; CHECK: // %bb.0: // %entry677; CHECK-NEXT: usubl2 v0.4s, v0.8h, v1.8h678; CHECK-NEXT: ret679entry:680 %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>681 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>682 %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>683 %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>684 %sub.i = sub <4 x i32> %0, %1685 ret <4 x i32> %sub.i686}687 688define <2 x i64> @test_vsubl_high_u32(<4 x i32> %a, <4 x i32> %b) {689; CHECK-LABEL: test_vsubl_high_u32:690; CHECK: // %bb.0: // %entry691; CHECK-NEXT: usubl2 v0.2d, v0.4s, v1.4s692; CHECK-NEXT: ret693entry:694 %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>695 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>696 %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>697 %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>698 %sub.i = sub <2 x i64> %0, %1699 ret <2 x i64> %sub.i700}701 702define <8 x i16> @test_vsubl_high_a8(<16 x i8> %a, <16 x i8> %b) {703; CHECK-SD-LABEL: test_vsubl_high_a8:704; CHECK-SD: // %bb.0: // %entry705; CHECK-SD-NEXT: usubl2 v0.8h, v0.16b, v1.16b706; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8707; CHECK-SD-NEXT: ret708;709; CHECK-GI-LABEL: test_vsubl_high_a8:710; CHECK-GI: // %bb.0: // %entry711; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff712; CHECK-GI-NEXT: usubl2 v0.8h, v0.16b, v1.16b713; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b714; CHECK-GI-NEXT: ret715entry:716 %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>717 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>718 %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>719 %1 = zext <8 x i8> %shuffle.i.i2.i to <8 x i16>720 %sub.i = sub <8 x i16> %0, %1721 %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>722 ret <8 x i16> %and723}724 725define <4 x i32> @test_vsubl_high_a16(<8 x i16> %a, <8 x i16> %b) {726; CHECK-LABEL: test_vsubl_high_a16:727; CHECK: // %bb.0: // %entry728; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff729; CHECK-NEXT: usubl2 v0.4s, v0.8h, v1.8h730; CHECK-NEXT: and v0.16b, v0.16b, v2.16b731; CHECK-NEXT: ret732entry:733 %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>734 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>735 %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>736 %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>737 %sub.i = sub <4 x i32> %0, %1738 %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>739 ret <4 x i32> %and740}741 742define <2 x i64> @test_vsubl_high_a32(<4 x i32> %a, <4 x i32> %b) {743; CHECK-LABEL: test_vsubl_high_a32:744; CHECK: // %bb.0: // %entry745; CHECK-NEXT: movi v2.2d, #0x000000ffffffff746; CHECK-NEXT: usubl2 v0.2d, v0.4s, v1.4s747; CHECK-NEXT: and v0.16b, v0.16b, v2.16b748; CHECK-NEXT: ret749entry:750 %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>751 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>752 %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>753 %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>754 %sub.i = sub <2 x i64> %0, %1755 %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>756 ret <2 x i64> %and757}758 759define <8 x i16> @test_vsubw_s8(<8 x i16> %a, <8 x i8> %b) {760; CHECK-LABEL: test_vsubw_s8:761; CHECK: // %bb.0: // %entry762; CHECK-NEXT: ssubw v0.8h, v0.8h, v1.8b763; CHECK-NEXT: ret764entry:765 %vmovl.i.i = sext <8 x i8> %b to <8 x i16>766 %sub.i = sub <8 x i16> %a, %vmovl.i.i767 ret <8 x i16> %sub.i768}769 770define <4 x i32> @test_vsubw_s16(<4 x i32> %a, <4 x i16> %b) {771; CHECK-LABEL: test_vsubw_s16:772; CHECK: // %bb.0: // %entry773; CHECK-NEXT: ssubw v0.4s, v0.4s, v1.4h774; CHECK-NEXT: ret775entry:776 %vmovl.i.i = sext <4 x i16> %b to <4 x i32>777 %sub.i = sub <4 x i32> %a, %vmovl.i.i778 ret <4 x i32> %sub.i779}780 781define <2 x i64> @test_vsubw_s32(<2 x i64> %a, <2 x i32> %b) {782; CHECK-LABEL: test_vsubw_s32:783; CHECK: // %bb.0: // %entry784; CHECK-NEXT: ssubw v0.2d, v0.2d, v1.2s785; CHECK-NEXT: ret786entry:787 %vmovl.i.i = sext <2 x i32> %b to <2 x i64>788 %sub.i = sub <2 x i64> %a, %vmovl.i.i789 ret <2 x i64> %sub.i790}791 792define <8 x i16> @test_vsubw_u8(<8 x i16> %a, <8 x i8> %b) {793; CHECK-LABEL: test_vsubw_u8:794; CHECK: // %bb.0: // %entry795; CHECK-NEXT: usubw v0.8h, v0.8h, v1.8b796; CHECK-NEXT: ret797entry:798 %vmovl.i.i = zext <8 x i8> %b to <8 x i16>799 %sub.i = sub <8 x i16> %a, %vmovl.i.i800 ret <8 x i16> %sub.i801}802 803define <4 x i32> @test_vsubw_u16(<4 x i32> %a, <4 x i16> %b) {804; CHECK-LABEL: test_vsubw_u16:805; CHECK: // %bb.0: // %entry806; CHECK-NEXT: usubw v0.4s, v0.4s, v1.4h807; CHECK-NEXT: ret808entry:809 %vmovl.i.i = zext <4 x i16> %b to <4 x i32>810 %sub.i = sub <4 x i32> %a, %vmovl.i.i811 ret <4 x i32> %sub.i812}813 814define <2 x i64> @test_vsubw_u32(<2 x i64> %a, <2 x i32> %b) {815; CHECK-LABEL: test_vsubw_u32:816; CHECK: // %bb.0: // %entry817; CHECK-NEXT: usubw v0.2d, v0.2d, v1.2s818; CHECK-NEXT: ret819entry:820 %vmovl.i.i = zext <2 x i32> %b to <2 x i64>821 %sub.i = sub <2 x i64> %a, %vmovl.i.i822 ret <2 x i64> %sub.i823}824 825define <8 x i16> @test_vsubw_a8(<8 x i16> %a, <8 x i8> %b) {826; CHECK-SD-LABEL: test_vsubw_a8:827; CHECK-SD: // %bb.0: // %entry828; CHECK-SD-NEXT: usubw v0.8h, v0.8h, v1.8b829; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8830; CHECK-SD-NEXT: ret831;832; CHECK-GI-LABEL: test_vsubw_a8:833; CHECK-GI: // %bb.0: // %entry834; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff835; CHECK-GI-NEXT: usubw v0.8h, v0.8h, v1.8b836; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b837; CHECK-GI-NEXT: ret838entry:839 %vmovl.i.i = zext <8 x i8> %b to <8 x i16>840 %sub.i = sub <8 x i16> %a, %vmovl.i.i841 %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>842 ret <8 x i16> %and843}844 845define <4 x i32> @test_vsubw_a16(<4 x i32> %a, <4 x i16> %b) {846; CHECK-LABEL: test_vsubw_a16:847; CHECK: // %bb.0: // %entry848; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff849; CHECK-NEXT: usubw v0.4s, v0.4s, v1.4h850; CHECK-NEXT: and v0.16b, v0.16b, v2.16b851; CHECK-NEXT: ret852entry:853 %vmovl.i.i = zext <4 x i16> %b to <4 x i32>854 %sub.i = sub <4 x i32> %a, %vmovl.i.i855 %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>856 ret <4 x i32> %and857}858 859define <2 x i64> @test_vsubw_a32(<2 x i64> %a, <2 x i32> %b) {860; CHECK-LABEL: test_vsubw_a32:861; CHECK: // %bb.0: // %entry862; CHECK-NEXT: movi v2.2d, #0x000000ffffffff863; CHECK-NEXT: usubw v0.2d, v0.2d, v1.2s864; CHECK-NEXT: and v0.16b, v0.16b, v2.16b865; CHECK-NEXT: ret866entry:867 %vmovl.i.i = zext <2 x i32> %b to <2 x i64>868 %sub.i = sub <2 x i64> %a, %vmovl.i.i869 %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>870 ret <2 x i64> %and871}872 873define <8 x i16> @test_vsubw_high_s8(<8 x i16> %a, <16 x i8> %b) {874; CHECK-LABEL: test_vsubw_high_s8:875; CHECK: // %bb.0: // %entry876; CHECK-NEXT: ssubw2 v0.8h, v0.8h, v1.16b877; CHECK-NEXT: ret878entry:879 %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>880 %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>881 %sub.i = sub <8 x i16> %a, %0882 ret <8 x i16> %sub.i883}884 885define <4 x i32> @test_vsubw_high_s16(<4 x i32> %a, <8 x i16> %b) {886; CHECK-LABEL: test_vsubw_high_s16:887; CHECK: // %bb.0: // %entry888; CHECK-NEXT: ssubw2 v0.4s, v0.4s, v1.8h889; CHECK-NEXT: ret890entry:891 %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>892 %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>893 %sub.i = sub <4 x i32> %a, %0894 ret <4 x i32> %sub.i895}896 897define <2 x i64> @test_vsubw_high_s32(<2 x i64> %a, <4 x i32> %b) {898; CHECK-LABEL: test_vsubw_high_s32:899; CHECK: // %bb.0: // %entry900; CHECK-NEXT: ssubw2 v0.2d, v0.2d, v1.4s901; CHECK-NEXT: ret902entry:903 %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>904 %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>905 %sub.i = sub <2 x i64> %a, %0906 ret <2 x i64> %sub.i907}908 909define <8 x i16> @test_vsubw_high_u8(<8 x i16> %a, <16 x i8> %b) {910; CHECK-LABEL: test_vsubw_high_u8:911; CHECK: // %bb.0: // %entry912; CHECK-NEXT: usubw2 v0.8h, v0.8h, v1.16b913; CHECK-NEXT: ret914entry:915 %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>916 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>917 %sub.i = sub <8 x i16> %a, %0918 ret <8 x i16> %sub.i919}920 921define <4 x i32> @test_vsubw_high_u16(<4 x i32> %a, <8 x i16> %b) {922; CHECK-LABEL: test_vsubw_high_u16:923; CHECK: // %bb.0: // %entry924; CHECK-NEXT: usubw2 v0.4s, v0.4s, v1.8h925; CHECK-NEXT: ret926entry:927 %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>928 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>929 %sub.i = sub <4 x i32> %a, %0930 ret <4 x i32> %sub.i931}932 933define <2 x i64> @test_vsubw_high_u32(<2 x i64> %a, <4 x i32> %b) {934; CHECK-LABEL: test_vsubw_high_u32:935; CHECK: // %bb.0: // %entry936; CHECK-NEXT: usubw2 v0.2d, v0.2d, v1.4s937; CHECK-NEXT: ret938entry:939 %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>940 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>941 %sub.i = sub <2 x i64> %a, %0942 ret <2 x i64> %sub.i943}944 945define <8 x i16> @test_vsubw_high_a8(<8 x i16> %a, <16 x i8> %b) {946; CHECK-SD-LABEL: test_vsubw_high_a8:947; CHECK-SD: // %bb.0: // %entry948; CHECK-SD-NEXT: usubw2 v0.8h, v0.8h, v1.16b949; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8950; CHECK-SD-NEXT: ret951;952; CHECK-GI-LABEL: test_vsubw_high_a8:953; CHECK-GI: // %bb.0: // %entry954; CHECK-GI-NEXT: movi v2.2d, #0xff00ff00ff00ff955; CHECK-GI-NEXT: usubw2 v0.8h, v0.8h, v1.16b956; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b957; CHECK-GI-NEXT: ret958entry:959 %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>960 %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>961 %sub.i = sub <8 x i16> %a, %0962 %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>963 ret <8 x i16> %and964}965 966define <4 x i32> @test_vsubw_high_a16(<4 x i32> %a, <8 x i16> %b) {967; CHECK-LABEL: test_vsubw_high_a16:968; CHECK: // %bb.0: // %entry969; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff970; CHECK-NEXT: usubw2 v0.4s, v0.4s, v1.8h971; CHECK-NEXT: and v0.16b, v0.16b, v2.16b972; CHECK-NEXT: ret973entry:974 %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>975 %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>976 %sub.i = sub <4 x i32> %a, %0977 %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>978 ret <4 x i32> %and979}980 981define <2 x i64> @test_vsubw_high_a32(<2 x i64> %a, <4 x i32> %b) {982; CHECK-LABEL: test_vsubw_high_a32:983; CHECK: // %bb.0: // %entry984; CHECK-NEXT: movi v2.2d, #0x000000ffffffff985; CHECK-NEXT: usubw2 v0.2d, v0.2d, v1.4s986; CHECK-NEXT: and v0.16b, v0.16b, v2.16b987; CHECK-NEXT: ret988entry:989 %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>990 %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>991 %sub.i = sub <2 x i64> %a, %0992 %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>993 ret <2 x i64> %and994}995 996define <8 x i8> @test_vaddhn_s16(<8 x i16> %a, <8 x i16> %b) {997; CHECK-LABEL: test_vaddhn_s16:998; CHECK: // %bb.0: // %entry999; CHECK-NEXT: addhn v0.8b, v0.8h, v1.8h1000; CHECK-NEXT: ret1001entry:1002 %vaddhn.i = add <8 x i16> %a, %b1003 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1004 %vaddhn2.i = trunc <8 x i16> %vaddhn1.i to <8 x i8>1005 ret <8 x i8> %vaddhn2.i1006}1007 1008define <4 x i16> @test_vaddhn_s32(<4 x i32> %a, <4 x i32> %b) {1009; CHECK-LABEL: test_vaddhn_s32:1010; CHECK: // %bb.0: // %entry1011; CHECK-NEXT: addhn v0.4h, v0.4s, v1.4s1012; CHECK-NEXT: ret1013entry:1014 %vaddhn.i = add <4 x i32> %a, %b1015 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>1016 %vaddhn2.i = trunc <4 x i32> %vaddhn1.i to <4 x i16>1017 ret <4 x i16> %vaddhn2.i1018}1019 1020define <2 x i32> @test_vaddhn_s64(<2 x i64> %a, <2 x i64> %b) {1021; CHECK-LABEL: test_vaddhn_s64:1022; CHECK: // %bb.0: // %entry1023; CHECK-NEXT: addhn v0.2s, v0.2d, v1.2d1024; CHECK-NEXT: ret1025entry:1026 %vaddhn.i = add <2 x i64> %a, %b1027 %vaddhn1.i = lshr <2 x i64> %vaddhn.i, <i64 32, i64 32>1028 %vaddhn2.i = trunc <2 x i64> %vaddhn1.i to <2 x i32>1029 ret <2 x i32> %vaddhn2.i1030}1031 1032define <8 x i8> @test_vaddhn_u16(<8 x i16> %a, <8 x i16> %b) {1033; CHECK-LABEL: test_vaddhn_u16:1034; CHECK: // %bb.0: // %entry1035; CHECK-NEXT: addhn v0.8b, v0.8h, v1.8h1036; CHECK-NEXT: ret1037entry:1038 %vaddhn.i = add <8 x i16> %a, %b1039 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1040 %vaddhn2.i = trunc <8 x i16> %vaddhn1.i to <8 x i8>1041 ret <8 x i8> %vaddhn2.i1042}1043 1044define <4 x i16> @test_vaddhn_u32(<4 x i32> %a, <4 x i32> %b) {1045; CHECK-LABEL: test_vaddhn_u32:1046; CHECK: // %bb.0: // %entry1047; CHECK-NEXT: addhn v0.4h, v0.4s, v1.4s1048; CHECK-NEXT: ret1049entry:1050 %vaddhn.i = add <4 x i32> %a, %b1051 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>1052 %vaddhn2.i = trunc <4 x i32> %vaddhn1.i to <4 x i16>1053 ret <4 x i16> %vaddhn2.i1054}1055 1056define <2 x i32> @test_vaddhn_u64(<2 x i64> %a, <2 x i64> %b) {1057; CHECK-LABEL: test_vaddhn_u64:1058; CHECK: // %bb.0: // %entry1059; CHECK-NEXT: addhn v0.2s, v0.2d, v1.2d1060; CHECK-NEXT: ret1061entry:1062 %vaddhn.i = add <2 x i64> %a, %b1063 %vaddhn1.i = lshr <2 x i64> %vaddhn.i, <i64 32, i64 32>1064 %vaddhn2.i = trunc <2 x i64> %vaddhn1.i to <2 x i32>1065 ret <2 x i32> %vaddhn2.i1066}1067 1068define <16 x i8> @test_vaddhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1069; CHECK-SD-LABEL: test_vaddhn_high_s16:1070; CHECK-SD: // %bb.0: // %entry1071; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01072; CHECK-SD-NEXT: addhn2 v0.16b, v1.8h, v2.8h1073; CHECK-SD-NEXT: ret1074;1075; CHECK-GI-LABEL: test_vaddhn_high_s16:1076; CHECK-GI: // %bb.0: // %entry1077; CHECK-GI-NEXT: addhn v1.8b, v1.8h, v2.8h1078; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01079; CHECK-GI-NEXT: fmov x8, d11080; CHECK-GI-NEXT: mov v0.d[1], x81081; CHECK-GI-NEXT: ret1082entry:1083 %vaddhn.i.i = add <8 x i16> %a, %b1084 %vaddhn1.i.i = lshr <8 x i16> %vaddhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1085 %vaddhn2.i.i = trunc <8 x i16> %vaddhn1.i.i to <8 x i8>1086 %0 = bitcast <8 x i8> %r to <1 x i64>1087 %1 = bitcast <8 x i8> %vaddhn2.i.i to <1 x i64>1088 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1089 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1090 ret <16 x i8> %21091}1092 1093define <8 x i16> @test_vaddhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1094; CHECK-SD-LABEL: test_vaddhn_high_s32:1095; CHECK-SD: // %bb.0: // %entry1096; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01097; CHECK-SD-NEXT: addhn2 v0.8h, v1.4s, v2.4s1098; CHECK-SD-NEXT: ret1099;1100; CHECK-GI-LABEL: test_vaddhn_high_s32:1101; CHECK-GI: // %bb.0: // %entry1102; CHECK-GI-NEXT: addhn v1.4h, v1.4s, v2.4s1103; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01104; CHECK-GI-NEXT: fmov x8, d11105; CHECK-GI-NEXT: mov v0.d[1], x81106; CHECK-GI-NEXT: ret1107entry:1108 %vaddhn.i.i = add <4 x i32> %a, %b1109 %vaddhn1.i.i = lshr <4 x i32> %vaddhn.i.i, <i32 16, i32 16, i32 16, i32 16>1110 %vaddhn2.i.i = trunc <4 x i32> %vaddhn1.i.i to <4 x i16>1111 %0 = bitcast <4 x i16> %r to <1 x i64>1112 %1 = bitcast <4 x i16> %vaddhn2.i.i to <1 x i64>1113 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1114 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1115 ret <8 x i16> %21116}1117 1118define <4 x i32> @test_vaddhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1119; CHECK-SD-LABEL: test_vaddhn_high_s64:1120; CHECK-SD: // %bb.0: // %entry1121; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01122; CHECK-SD-NEXT: addhn2 v0.4s, v1.2d, v2.2d1123; CHECK-SD-NEXT: ret1124;1125; CHECK-GI-LABEL: test_vaddhn_high_s64:1126; CHECK-GI: // %bb.0: // %entry1127; CHECK-GI-NEXT: addhn v1.2s, v1.2d, v2.2d1128; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01129; CHECK-GI-NEXT: fmov x8, d11130; CHECK-GI-NEXT: mov v0.d[1], x81131; CHECK-GI-NEXT: ret1132entry:1133 %vaddhn.i.i = add <2 x i64> %a, %b1134 %vaddhn1.i.i = lshr <2 x i64> %vaddhn.i.i, <i64 32, i64 32>1135 %vaddhn2.i.i = trunc <2 x i64> %vaddhn1.i.i to <2 x i32>1136 %0 = bitcast <2 x i32> %r to <1 x i64>1137 %1 = bitcast <2 x i32> %vaddhn2.i.i to <1 x i64>1138 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1139 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1140 ret <4 x i32> %21141}1142 1143define <16 x i8> @test_vaddhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1144; CHECK-SD-LABEL: test_vaddhn_high_u16:1145; CHECK-SD: // %bb.0: // %entry1146; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01147; CHECK-SD-NEXT: addhn2 v0.16b, v1.8h, v2.8h1148; CHECK-SD-NEXT: ret1149;1150; CHECK-GI-LABEL: test_vaddhn_high_u16:1151; CHECK-GI: // %bb.0: // %entry1152; CHECK-GI-NEXT: addhn v1.8b, v1.8h, v2.8h1153; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01154; CHECK-GI-NEXT: fmov x8, d11155; CHECK-GI-NEXT: mov v0.d[1], x81156; CHECK-GI-NEXT: ret1157entry:1158 %vaddhn.i.i = add <8 x i16> %a, %b1159 %vaddhn1.i.i = lshr <8 x i16> %vaddhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1160 %vaddhn2.i.i = trunc <8 x i16> %vaddhn1.i.i to <8 x i8>1161 %0 = bitcast <8 x i8> %r to <1 x i64>1162 %1 = bitcast <8 x i8> %vaddhn2.i.i to <1 x i64>1163 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1164 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1165 ret <16 x i8> %21166}1167 1168define <8 x i16> @test_vaddhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1169; CHECK-SD-LABEL: test_vaddhn_high_u32:1170; CHECK-SD: // %bb.0: // %entry1171; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01172; CHECK-SD-NEXT: addhn2 v0.8h, v1.4s, v2.4s1173; CHECK-SD-NEXT: ret1174;1175; CHECK-GI-LABEL: test_vaddhn_high_u32:1176; CHECK-GI: // %bb.0: // %entry1177; CHECK-GI-NEXT: addhn v1.4h, v1.4s, v2.4s1178; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01179; CHECK-GI-NEXT: fmov x8, d11180; CHECK-GI-NEXT: mov v0.d[1], x81181; CHECK-GI-NEXT: ret1182entry:1183 %vaddhn.i.i = add <4 x i32> %a, %b1184 %vaddhn1.i.i = lshr <4 x i32> %vaddhn.i.i, <i32 16, i32 16, i32 16, i32 16>1185 %vaddhn2.i.i = trunc <4 x i32> %vaddhn1.i.i to <4 x i16>1186 %0 = bitcast <4 x i16> %r to <1 x i64>1187 %1 = bitcast <4 x i16> %vaddhn2.i.i to <1 x i64>1188 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1189 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1190 ret <8 x i16> %21191}1192 1193define <4 x i32> @test_vaddhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1194; CHECK-SD-LABEL: test_vaddhn_high_u64:1195; CHECK-SD: // %bb.0: // %entry1196; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01197; CHECK-SD-NEXT: addhn2 v0.4s, v1.2d, v2.2d1198; CHECK-SD-NEXT: ret1199;1200; CHECK-GI-LABEL: test_vaddhn_high_u64:1201; CHECK-GI: // %bb.0: // %entry1202; CHECK-GI-NEXT: addhn v1.2s, v1.2d, v2.2d1203; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01204; CHECK-GI-NEXT: fmov x8, d11205; CHECK-GI-NEXT: mov v0.d[1], x81206; CHECK-GI-NEXT: ret1207entry:1208 %vaddhn.i.i = add <2 x i64> %a, %b1209 %vaddhn1.i.i = lshr <2 x i64> %vaddhn.i.i, <i64 32, i64 32>1210 %vaddhn2.i.i = trunc <2 x i64> %vaddhn1.i.i to <2 x i32>1211 %0 = bitcast <2 x i32> %r to <1 x i64>1212 %1 = bitcast <2 x i32> %vaddhn2.i.i to <1 x i64>1213 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1214 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1215 ret <4 x i32> %21216}1217 1218define <8 x i8> @test_vraddhn_s16(<8 x i16> %a, <8 x i16> %b) {1219; CHECK-LABEL: test_vraddhn_s16:1220; CHECK: // %bb.0: // %entry1221; CHECK-NEXT: raddhn v0.8b, v0.8h, v1.8h1222; CHECK-NEXT: ret1223entry:1224 %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)1225 ret <8 x i8> %vraddhn2.i1226}1227 1228define <4 x i16> @test_vraddhn_s32(<4 x i32> %a, <4 x i32> %b) {1229; CHECK-LABEL: test_vraddhn_s32:1230; CHECK: // %bb.0: // %entry1231; CHECK-NEXT: raddhn v0.4h, v0.4s, v1.4s1232; CHECK-NEXT: ret1233entry:1234 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)1235 ret <4 x i16> %vraddhn2.i1236}1237 1238define <2 x i32> @test_vraddhn_s64(<2 x i64> %a, <2 x i64> %b) {1239; CHECK-LABEL: test_vraddhn_s64:1240; CHECK: // %bb.0: // %entry1241; CHECK-NEXT: raddhn v0.2s, v0.2d, v1.2d1242; CHECK-NEXT: ret1243entry:1244 %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)1245 ret <2 x i32> %vraddhn2.i1246}1247 1248define <8 x i8> @test_vraddhn_u16(<8 x i16> %a, <8 x i16> %b) {1249; CHECK-LABEL: test_vraddhn_u16:1250; CHECK: // %bb.0: // %entry1251; CHECK-NEXT: raddhn v0.8b, v0.8h, v1.8h1252; CHECK-NEXT: ret1253entry:1254 %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)1255 ret <8 x i8> %vraddhn2.i1256}1257 1258define <4 x i16> @test_vraddhn_u32(<4 x i32> %a, <4 x i32> %b) {1259; CHECK-LABEL: test_vraddhn_u32:1260; CHECK: // %bb.0: // %entry1261; CHECK-NEXT: raddhn v0.4h, v0.4s, v1.4s1262; CHECK-NEXT: ret1263entry:1264 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)1265 ret <4 x i16> %vraddhn2.i1266}1267 1268define <2 x i32> @test_vraddhn_u64(<2 x i64> %a, <2 x i64> %b) {1269; CHECK-LABEL: test_vraddhn_u64:1270; CHECK: // %bb.0: // %entry1271; CHECK-NEXT: raddhn v0.2s, v0.2d, v1.2d1272; CHECK-NEXT: ret1273entry:1274 %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)1275 ret <2 x i32> %vraddhn2.i1276}1277 1278define <16 x i8> @test_vraddhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1279; CHECK-SD-LABEL: test_vraddhn_high_s16:1280; CHECK-SD: // %bb.0: // %entry1281; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01282; CHECK-SD-NEXT: raddhn2 v0.16b, v1.8h, v2.8h1283; CHECK-SD-NEXT: ret1284;1285; CHECK-GI-LABEL: test_vraddhn_high_s16:1286; CHECK-GI: // %bb.0: // %entry1287; CHECK-GI-NEXT: raddhn v1.8b, v1.8h, v2.8h1288; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01289; CHECK-GI-NEXT: fmov x8, d11290; CHECK-GI-NEXT: mov v0.d[1], x81291; CHECK-GI-NEXT: ret1292entry:1293 %vraddhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)1294 %0 = bitcast <8 x i8> %r to <1 x i64>1295 %1 = bitcast <8 x i8> %vraddhn2.i.i to <1 x i64>1296 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1297 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1298 ret <16 x i8> %21299}1300 1301define <8 x i16> @test_vraddhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1302; CHECK-SD-LABEL: test_vraddhn_high_s32:1303; CHECK-SD: // %bb.0: // %entry1304; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01305; CHECK-SD-NEXT: raddhn2 v0.8h, v1.4s, v2.4s1306; CHECK-SD-NEXT: ret1307;1308; CHECK-GI-LABEL: test_vraddhn_high_s32:1309; CHECK-GI: // %bb.0: // %entry1310; CHECK-GI-NEXT: raddhn v1.4h, v1.4s, v2.4s1311; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01312; CHECK-GI-NEXT: fmov x8, d11313; CHECK-GI-NEXT: mov v0.d[1], x81314; CHECK-GI-NEXT: ret1315entry:1316 %vraddhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)1317 %0 = bitcast <4 x i16> %r to <1 x i64>1318 %1 = bitcast <4 x i16> %vraddhn2.i.i to <1 x i64>1319 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1320 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1321 ret <8 x i16> %21322}1323 1324define <4 x i32> @test_vraddhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1325; CHECK-SD-LABEL: test_vraddhn_high_s64:1326; CHECK-SD: // %bb.0: // %entry1327; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01328; CHECK-SD-NEXT: raddhn2 v0.4s, v1.2d, v2.2d1329; CHECK-SD-NEXT: ret1330;1331; CHECK-GI-LABEL: test_vraddhn_high_s64:1332; CHECK-GI: // %bb.0: // %entry1333; CHECK-GI-NEXT: raddhn v1.2s, v1.2d, v2.2d1334; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01335; CHECK-GI-NEXT: fmov x8, d11336; CHECK-GI-NEXT: mov v0.d[1], x81337; CHECK-GI-NEXT: ret1338entry:1339 %vraddhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)1340 %0 = bitcast <2 x i32> %r to <1 x i64>1341 %1 = bitcast <2 x i32> %vraddhn2.i.i to <1 x i64>1342 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1343 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1344 ret <4 x i32> %21345}1346 1347define <16 x i8> @test_vraddhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1348; CHECK-SD-LABEL: test_vraddhn_high_u16:1349; CHECK-SD: // %bb.0: // %entry1350; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01351; CHECK-SD-NEXT: raddhn2 v0.16b, v1.8h, v2.8h1352; CHECK-SD-NEXT: ret1353;1354; CHECK-GI-LABEL: test_vraddhn_high_u16:1355; CHECK-GI: // %bb.0: // %entry1356; CHECK-GI-NEXT: raddhn v1.8b, v1.8h, v2.8h1357; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01358; CHECK-GI-NEXT: fmov x8, d11359; CHECK-GI-NEXT: mov v0.d[1], x81360; CHECK-GI-NEXT: ret1361entry:1362 %vraddhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)1363 %0 = bitcast <8 x i8> %r to <1 x i64>1364 %1 = bitcast <8 x i8> %vraddhn2.i.i to <1 x i64>1365 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1366 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1367 ret <16 x i8> %21368}1369 1370define <8 x i16> @test_vraddhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1371; CHECK-SD-LABEL: test_vraddhn_high_u32:1372; CHECK-SD: // %bb.0: // %entry1373; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01374; CHECK-SD-NEXT: raddhn2 v0.8h, v1.4s, v2.4s1375; CHECK-SD-NEXT: ret1376;1377; CHECK-GI-LABEL: test_vraddhn_high_u32:1378; CHECK-GI: // %bb.0: // %entry1379; CHECK-GI-NEXT: raddhn v1.4h, v1.4s, v2.4s1380; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01381; CHECK-GI-NEXT: fmov x8, d11382; CHECK-GI-NEXT: mov v0.d[1], x81383; CHECK-GI-NEXT: ret1384entry:1385 %vraddhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)1386 %0 = bitcast <4 x i16> %r to <1 x i64>1387 %1 = bitcast <4 x i16> %vraddhn2.i.i to <1 x i64>1388 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1389 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1390 ret <8 x i16> %21391}1392 1393define <4 x i32> @test_vraddhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1394; CHECK-SD-LABEL: test_vraddhn_high_u64:1395; CHECK-SD: // %bb.0: // %entry1396; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01397; CHECK-SD-NEXT: raddhn2 v0.4s, v1.2d, v2.2d1398; CHECK-SD-NEXT: ret1399;1400; CHECK-GI-LABEL: test_vraddhn_high_u64:1401; CHECK-GI: // %bb.0: // %entry1402; CHECK-GI-NEXT: raddhn v1.2s, v1.2d, v2.2d1403; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01404; CHECK-GI-NEXT: fmov x8, d11405; CHECK-GI-NEXT: mov v0.d[1], x81406; CHECK-GI-NEXT: ret1407entry:1408 %vraddhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)1409 %0 = bitcast <2 x i32> %r to <1 x i64>1410 %1 = bitcast <2 x i32> %vraddhn2.i.i to <1 x i64>1411 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1412 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1413 ret <4 x i32> %21414}1415 1416define <8 x i8> @test_vsubhn_s16(<8 x i16> %a, <8 x i16> %b) {1417; CHECK-LABEL: test_vsubhn_s16:1418; CHECK: // %bb.0: // %entry1419; CHECK-NEXT: subhn v0.8b, v0.8h, v1.8h1420; CHECK-NEXT: ret1421entry:1422 %vsubhn.i = sub <8 x i16> %a, %b1423 %vsubhn1.i = lshr <8 x i16> %vsubhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1424 %vsubhn2.i = trunc <8 x i16> %vsubhn1.i to <8 x i8>1425 ret <8 x i8> %vsubhn2.i1426}1427 1428define <4 x i16> @test_vsubhn_s32(<4 x i32> %a, <4 x i32> %b) {1429; CHECK-LABEL: test_vsubhn_s32:1430; CHECK: // %bb.0: // %entry1431; CHECK-NEXT: subhn v0.4h, v0.4s, v1.4s1432; CHECK-NEXT: ret1433entry:1434 %vsubhn.i = sub <4 x i32> %a, %b1435 %vsubhn1.i = lshr <4 x i32> %vsubhn.i, <i32 16, i32 16, i32 16, i32 16>1436 %vsubhn2.i = trunc <4 x i32> %vsubhn1.i to <4 x i16>1437 ret <4 x i16> %vsubhn2.i1438}1439 1440define <2 x i32> @test_vsubhn_s64(<2 x i64> %a, <2 x i64> %b) {1441; CHECK-LABEL: test_vsubhn_s64:1442; CHECK: // %bb.0: // %entry1443; CHECK-NEXT: subhn v0.2s, v0.2d, v1.2d1444; CHECK-NEXT: ret1445entry:1446 %vsubhn.i = sub <2 x i64> %a, %b1447 %vsubhn1.i = lshr <2 x i64> %vsubhn.i, <i64 32, i64 32>1448 %vsubhn2.i = trunc <2 x i64> %vsubhn1.i to <2 x i32>1449 ret <2 x i32> %vsubhn2.i1450}1451 1452define <8 x i8> @test_vsubhn_u16(<8 x i16> %a, <8 x i16> %b) {1453; CHECK-LABEL: test_vsubhn_u16:1454; CHECK: // %bb.0: // %entry1455; CHECK-NEXT: subhn v0.8b, v0.8h, v1.8h1456; CHECK-NEXT: ret1457entry:1458 %vsubhn.i = sub <8 x i16> %a, %b1459 %vsubhn1.i = lshr <8 x i16> %vsubhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1460 %vsubhn2.i = trunc <8 x i16> %vsubhn1.i to <8 x i8>1461 ret <8 x i8> %vsubhn2.i1462}1463 1464define <4 x i16> @test_vsubhn_u32(<4 x i32> %a, <4 x i32> %b) {1465; CHECK-LABEL: test_vsubhn_u32:1466; CHECK: // %bb.0: // %entry1467; CHECK-NEXT: subhn v0.4h, v0.4s, v1.4s1468; CHECK-NEXT: ret1469entry:1470 %vsubhn.i = sub <4 x i32> %a, %b1471 %vsubhn1.i = lshr <4 x i32> %vsubhn.i, <i32 16, i32 16, i32 16, i32 16>1472 %vsubhn2.i = trunc <4 x i32> %vsubhn1.i to <4 x i16>1473 ret <4 x i16> %vsubhn2.i1474}1475 1476define <2 x i32> @test_vsubhn_u64(<2 x i64> %a, <2 x i64> %b) {1477; CHECK-LABEL: test_vsubhn_u64:1478; CHECK: // %bb.0: // %entry1479; CHECK-NEXT: subhn v0.2s, v0.2d, v1.2d1480; CHECK-NEXT: ret1481entry:1482 %vsubhn.i = sub <2 x i64> %a, %b1483 %vsubhn1.i = lshr <2 x i64> %vsubhn.i, <i64 32, i64 32>1484 %vsubhn2.i = trunc <2 x i64> %vsubhn1.i to <2 x i32>1485 ret <2 x i32> %vsubhn2.i1486}1487 1488define <16 x i8> @test_vsubhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1489; CHECK-SD-LABEL: test_vsubhn_high_s16:1490; CHECK-SD: // %bb.0: // %entry1491; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01492; CHECK-SD-NEXT: subhn2 v0.16b, v1.8h, v2.8h1493; CHECK-SD-NEXT: ret1494;1495; CHECK-GI-LABEL: test_vsubhn_high_s16:1496; CHECK-GI: // %bb.0: // %entry1497; CHECK-GI-NEXT: subhn v1.8b, v1.8h, v2.8h1498; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01499; CHECK-GI-NEXT: fmov x8, d11500; CHECK-GI-NEXT: mov v0.d[1], x81501; CHECK-GI-NEXT: ret1502entry:1503 %vsubhn.i.i = sub <8 x i16> %a, %b1504 %vsubhn1.i.i = lshr <8 x i16> %vsubhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1505 %vsubhn2.i.i = trunc <8 x i16> %vsubhn1.i.i to <8 x i8>1506 %0 = bitcast <8 x i8> %r to <1 x i64>1507 %1 = bitcast <8 x i8> %vsubhn2.i.i to <1 x i64>1508 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1509 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1510 ret <16 x i8> %21511}1512 1513define <8 x i16> @test_vsubhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1514; CHECK-SD-LABEL: test_vsubhn_high_s32:1515; CHECK-SD: // %bb.0: // %entry1516; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01517; CHECK-SD-NEXT: subhn2 v0.8h, v1.4s, v2.4s1518; CHECK-SD-NEXT: ret1519;1520; CHECK-GI-LABEL: test_vsubhn_high_s32:1521; CHECK-GI: // %bb.0: // %entry1522; CHECK-GI-NEXT: subhn v1.4h, v1.4s, v2.4s1523; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01524; CHECK-GI-NEXT: fmov x8, d11525; CHECK-GI-NEXT: mov v0.d[1], x81526; CHECK-GI-NEXT: ret1527entry:1528 %vsubhn.i.i = sub <4 x i32> %a, %b1529 %vsubhn1.i.i = lshr <4 x i32> %vsubhn.i.i, <i32 16, i32 16, i32 16, i32 16>1530 %vsubhn2.i.i = trunc <4 x i32> %vsubhn1.i.i to <4 x i16>1531 %0 = bitcast <4 x i16> %r to <1 x i64>1532 %1 = bitcast <4 x i16> %vsubhn2.i.i to <1 x i64>1533 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1534 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1535 ret <8 x i16> %21536}1537 1538define <4 x i32> @test_vsubhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1539; CHECK-SD-LABEL: test_vsubhn_high_s64:1540; CHECK-SD: // %bb.0: // %entry1541; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01542; CHECK-SD-NEXT: subhn2 v0.4s, v1.2d, v2.2d1543; CHECK-SD-NEXT: ret1544;1545; CHECK-GI-LABEL: test_vsubhn_high_s64:1546; CHECK-GI: // %bb.0: // %entry1547; CHECK-GI-NEXT: subhn v1.2s, v1.2d, v2.2d1548; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01549; CHECK-GI-NEXT: fmov x8, d11550; CHECK-GI-NEXT: mov v0.d[1], x81551; CHECK-GI-NEXT: ret1552entry:1553 %vsubhn.i.i = sub <2 x i64> %a, %b1554 %vsubhn1.i.i = lshr <2 x i64> %vsubhn.i.i, <i64 32, i64 32>1555 %vsubhn2.i.i = trunc <2 x i64> %vsubhn1.i.i to <2 x i32>1556 %0 = bitcast <2 x i32> %r to <1 x i64>1557 %1 = bitcast <2 x i32> %vsubhn2.i.i to <1 x i64>1558 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1559 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1560 ret <4 x i32> %21561}1562 1563define <16 x i8> @test_vsubhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1564; CHECK-SD-LABEL: test_vsubhn_high_u16:1565; CHECK-SD: // %bb.0: // %entry1566; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01567; CHECK-SD-NEXT: subhn2 v0.16b, v1.8h, v2.8h1568; CHECK-SD-NEXT: ret1569;1570; CHECK-GI-LABEL: test_vsubhn_high_u16:1571; CHECK-GI: // %bb.0: // %entry1572; CHECK-GI-NEXT: subhn v1.8b, v1.8h, v2.8h1573; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01574; CHECK-GI-NEXT: fmov x8, d11575; CHECK-GI-NEXT: mov v0.d[1], x81576; CHECK-GI-NEXT: ret1577entry:1578 %vsubhn.i.i = sub <8 x i16> %a, %b1579 %vsubhn1.i.i = lshr <8 x i16> %vsubhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>1580 %vsubhn2.i.i = trunc <8 x i16> %vsubhn1.i.i to <8 x i8>1581 %0 = bitcast <8 x i8> %r to <1 x i64>1582 %1 = bitcast <8 x i8> %vsubhn2.i.i to <1 x i64>1583 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1584 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1585 ret <16 x i8> %21586}1587 1588define <8 x i16> @test_vsubhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1589; CHECK-SD-LABEL: test_vsubhn_high_u32:1590; CHECK-SD: // %bb.0: // %entry1591; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01592; CHECK-SD-NEXT: subhn2 v0.8h, v1.4s, v2.4s1593; CHECK-SD-NEXT: ret1594;1595; CHECK-GI-LABEL: test_vsubhn_high_u32:1596; CHECK-GI: // %bb.0: // %entry1597; CHECK-GI-NEXT: subhn v1.4h, v1.4s, v2.4s1598; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01599; CHECK-GI-NEXT: fmov x8, d11600; CHECK-GI-NEXT: mov v0.d[1], x81601; CHECK-GI-NEXT: ret1602entry:1603 %vsubhn.i.i = sub <4 x i32> %a, %b1604 %vsubhn1.i.i = lshr <4 x i32> %vsubhn.i.i, <i32 16, i32 16, i32 16, i32 16>1605 %vsubhn2.i.i = trunc <4 x i32> %vsubhn1.i.i to <4 x i16>1606 %0 = bitcast <4 x i16> %r to <1 x i64>1607 %1 = bitcast <4 x i16> %vsubhn2.i.i to <1 x i64>1608 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1609 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1610 ret <8 x i16> %21611}1612 1613define <4 x i32> @test_vsubhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1614; CHECK-SD-LABEL: test_vsubhn_high_u64:1615; CHECK-SD: // %bb.0: // %entry1616; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01617; CHECK-SD-NEXT: subhn2 v0.4s, v1.2d, v2.2d1618; CHECK-SD-NEXT: ret1619;1620; CHECK-GI-LABEL: test_vsubhn_high_u64:1621; CHECK-GI: // %bb.0: // %entry1622; CHECK-GI-NEXT: subhn v1.2s, v1.2d, v2.2d1623; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01624; CHECK-GI-NEXT: fmov x8, d11625; CHECK-GI-NEXT: mov v0.d[1], x81626; CHECK-GI-NEXT: ret1627entry:1628 %vsubhn.i.i = sub <2 x i64> %a, %b1629 %vsubhn1.i.i = lshr <2 x i64> %vsubhn.i.i, <i64 32, i64 32>1630 %vsubhn2.i.i = trunc <2 x i64> %vsubhn1.i.i to <2 x i32>1631 %0 = bitcast <2 x i32> %r to <1 x i64>1632 %1 = bitcast <2 x i32> %vsubhn2.i.i to <1 x i64>1633 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1634 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1635 ret <4 x i32> %21636}1637 1638define <8 x i8> @test_vrsubhn_s16(<8 x i16> %a, <8 x i16> %b) {1639; CHECK-LABEL: test_vrsubhn_s16:1640; CHECK: // %bb.0: // %entry1641; CHECK-NEXT: rsubhn v0.8b, v0.8h, v1.8h1642; CHECK-NEXT: ret1643entry:1644 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)1645 ret <8 x i8> %vrsubhn2.i1646}1647 1648define <4 x i16> @test_vrsubhn_s32(<4 x i32> %a, <4 x i32> %b) {1649; CHECK-LABEL: test_vrsubhn_s32:1650; CHECK: // %bb.0: // %entry1651; CHECK-NEXT: rsubhn v0.4h, v0.4s, v1.4s1652; CHECK-NEXT: ret1653entry:1654 %vrsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)1655 ret <4 x i16> %vrsubhn2.i1656}1657 1658define <2 x i32> @test_vrsubhn_s64(<2 x i64> %a, <2 x i64> %b) {1659; CHECK-LABEL: test_vrsubhn_s64:1660; CHECK: // %bb.0: // %entry1661; CHECK-NEXT: rsubhn v0.2s, v0.2d, v1.2d1662; CHECK-NEXT: ret1663entry:1664 %vrsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)1665 ret <2 x i32> %vrsubhn2.i1666}1667 1668define <8 x i8> @test_vrsubhn_u16(<8 x i16> %a, <8 x i16> %b) {1669; CHECK-LABEL: test_vrsubhn_u16:1670; CHECK: // %bb.0: // %entry1671; CHECK-NEXT: rsubhn v0.8b, v0.8h, v1.8h1672; CHECK-NEXT: ret1673entry:1674 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)1675 ret <8 x i8> %vrsubhn2.i1676}1677 1678define <4 x i16> @test_vrsubhn_u32(<4 x i32> %a, <4 x i32> %b) {1679; CHECK-LABEL: test_vrsubhn_u32:1680; CHECK: // %bb.0: // %entry1681; CHECK-NEXT: rsubhn v0.4h, v0.4s, v1.4s1682; CHECK-NEXT: ret1683entry:1684 %vrsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)1685 ret <4 x i16> %vrsubhn2.i1686}1687 1688define <2 x i32> @test_vrsubhn_u64(<2 x i64> %a, <2 x i64> %b) {1689; CHECK-LABEL: test_vrsubhn_u64:1690; CHECK: // %bb.0: // %entry1691; CHECK-NEXT: rsubhn v0.2s, v0.2d, v1.2d1692; CHECK-NEXT: ret1693entry:1694 %vrsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)1695 ret <2 x i32> %vrsubhn2.i1696}1697 1698define <16 x i8> @test_vrsubhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1699; CHECK-SD-LABEL: test_vrsubhn_high_s16:1700; CHECK-SD: // %bb.0: // %entry1701; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01702; CHECK-SD-NEXT: rsubhn2 v0.16b, v1.8h, v2.8h1703; CHECK-SD-NEXT: ret1704;1705; CHECK-GI-LABEL: test_vrsubhn_high_s16:1706; CHECK-GI: // %bb.0: // %entry1707; CHECK-GI-NEXT: rsubhn v1.8b, v1.8h, v2.8h1708; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01709; CHECK-GI-NEXT: fmov x8, d11710; CHECK-GI-NEXT: mov v0.d[1], x81711; CHECK-GI-NEXT: ret1712entry:1713 %vrsubhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)1714 %0 = bitcast <8 x i8> %r to <1 x i64>1715 %1 = bitcast <8 x i8> %vrsubhn2.i.i to <1 x i64>1716 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1717 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1718 ret <16 x i8> %21719}1720 1721define <8 x i16> @test_vrsubhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1722; CHECK-SD-LABEL: test_vrsubhn_high_s32:1723; CHECK-SD: // %bb.0: // %entry1724; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01725; CHECK-SD-NEXT: rsubhn2 v0.8h, v1.4s, v2.4s1726; CHECK-SD-NEXT: ret1727;1728; CHECK-GI-LABEL: test_vrsubhn_high_s32:1729; CHECK-GI: // %bb.0: // %entry1730; CHECK-GI-NEXT: rsubhn v1.4h, v1.4s, v2.4s1731; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01732; CHECK-GI-NEXT: fmov x8, d11733; CHECK-GI-NEXT: mov v0.d[1], x81734; CHECK-GI-NEXT: ret1735entry:1736 %vrsubhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)1737 %0 = bitcast <4 x i16> %r to <1 x i64>1738 %1 = bitcast <4 x i16> %vrsubhn2.i.i to <1 x i64>1739 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1740 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1741 ret <8 x i16> %21742}1743 1744define <4 x i32> @test_vrsubhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1745; CHECK-SD-LABEL: test_vrsubhn_high_s64:1746; CHECK-SD: // %bb.0: // %entry1747; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01748; CHECK-SD-NEXT: rsubhn2 v0.4s, v1.2d, v2.2d1749; CHECK-SD-NEXT: ret1750;1751; CHECK-GI-LABEL: test_vrsubhn_high_s64:1752; CHECK-GI: // %bb.0: // %entry1753; CHECK-GI-NEXT: rsubhn v1.2s, v1.2d, v2.2d1754; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01755; CHECK-GI-NEXT: fmov x8, d11756; CHECK-GI-NEXT: mov v0.d[1], x81757; CHECK-GI-NEXT: ret1758entry:1759 %vrsubhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)1760 %0 = bitcast <2 x i32> %r to <1 x i64>1761 %1 = bitcast <2 x i32> %vrsubhn2.i.i to <1 x i64>1762 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1763 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1764 ret <4 x i32> %21765}1766 1767define <16 x i8> @test_vrsubhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {1768; CHECK-SD-LABEL: test_vrsubhn_high_u16:1769; CHECK-SD: // %bb.0: // %entry1770; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01771; CHECK-SD-NEXT: rsubhn2 v0.16b, v1.8h, v2.8h1772; CHECK-SD-NEXT: ret1773;1774; CHECK-GI-LABEL: test_vrsubhn_high_u16:1775; CHECK-GI: // %bb.0: // %entry1776; CHECK-GI-NEXT: rsubhn v1.8b, v1.8h, v2.8h1777; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01778; CHECK-GI-NEXT: fmov x8, d11779; CHECK-GI-NEXT: mov v0.d[1], x81780; CHECK-GI-NEXT: ret1781entry:1782 %vrsubhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)1783 %0 = bitcast <8 x i8> %r to <1 x i64>1784 %1 = bitcast <8 x i8> %vrsubhn2.i.i to <1 x i64>1785 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1786 %2 = bitcast <2 x i64> %shuffle.i.i to <16 x i8>1787 ret <16 x i8> %21788}1789 1790define <8 x i16> @test_vrsubhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {1791; CHECK-SD-LABEL: test_vrsubhn_high_u32:1792; CHECK-SD: // %bb.0: // %entry1793; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01794; CHECK-SD-NEXT: rsubhn2 v0.8h, v1.4s, v2.4s1795; CHECK-SD-NEXT: ret1796;1797; CHECK-GI-LABEL: test_vrsubhn_high_u32:1798; CHECK-GI: // %bb.0: // %entry1799; CHECK-GI-NEXT: rsubhn v1.4h, v1.4s, v2.4s1800; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01801; CHECK-GI-NEXT: fmov x8, d11802; CHECK-GI-NEXT: mov v0.d[1], x81803; CHECK-GI-NEXT: ret1804entry:1805 %vrsubhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)1806 %0 = bitcast <4 x i16> %r to <1 x i64>1807 %1 = bitcast <4 x i16> %vrsubhn2.i.i to <1 x i64>1808 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1809 %2 = bitcast <2 x i64> %shuffle.i.i to <8 x i16>1810 ret <8 x i16> %21811}1812 1813define <4 x i32> @test_vrsubhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {1814; CHECK-SD-LABEL: test_vrsubhn_high_u64:1815; CHECK-SD: // %bb.0: // %entry1816; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01817; CHECK-SD-NEXT: rsubhn2 v0.4s, v1.2d, v2.2d1818; CHECK-SD-NEXT: ret1819;1820; CHECK-GI-LABEL: test_vrsubhn_high_u64:1821; CHECK-GI: // %bb.0: // %entry1822; CHECK-GI-NEXT: rsubhn v1.2s, v1.2d, v2.2d1823; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01824; CHECK-GI-NEXT: fmov x8, d11825; CHECK-GI-NEXT: mov v0.d[1], x81826; CHECK-GI-NEXT: ret1827entry:1828 %vrsubhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)1829 %0 = bitcast <2 x i32> %r to <1 x i64>1830 %1 = bitcast <2 x i32> %vrsubhn2.i.i to <1 x i64>1831 %shuffle.i.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>1832 %2 = bitcast <2 x i64> %shuffle.i.i to <4 x i32>1833 ret <4 x i32> %21834}1835 1836define <8 x i16> @test_vabdl_s8(<8 x i8> %a, <8 x i8> %b) {1837; CHECK-LABEL: test_vabdl_s8:1838; CHECK: // %bb.0: // %entry1839; CHECK-NEXT: sabdl v0.8h, v0.8b, v1.8b1840; CHECK-NEXT: ret1841entry:1842 %vabd.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %a, <8 x i8> %b)1843 %vmovl.i.i = zext <8 x i8> %vabd.i.i to <8 x i16>1844 ret <8 x i16> %vmovl.i.i1845}1846 1847define <4 x i32> @test_vabdl_s16(<4 x i16> %a, <4 x i16> %b) {1848; CHECK-LABEL: test_vabdl_s16:1849; CHECK: // %bb.0: // %entry1850; CHECK-NEXT: sabdl v0.4s, v0.4h, v1.4h1851; CHECK-NEXT: ret1852entry:1853 %vabd2.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %a, <4 x i16> %b)1854 %vmovl.i.i = zext <4 x i16> %vabd2.i.i to <4 x i32>1855 ret <4 x i32> %vmovl.i.i1856}1857 1858define <2 x i64> @test_vabdl_s32(<2 x i32> %a, <2 x i32> %b) {1859; CHECK-LABEL: test_vabdl_s32:1860; CHECK: // %bb.0: // %entry1861; CHECK-NEXT: sabdl v0.2d, v0.2s, v1.2s1862; CHECK-NEXT: ret1863entry:1864 %vabd2.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %a, <2 x i32> %b)1865 %vmovl.i.i = zext <2 x i32> %vabd2.i.i to <2 x i64>1866 ret <2 x i64> %vmovl.i.i1867}1868 1869define <8 x i16> @test_vabdl_u8(<8 x i8> %a, <8 x i8> %b) {1870; CHECK-LABEL: test_vabdl_u8:1871; CHECK: // %bb.0: // %entry1872; CHECK-NEXT: uabdl v0.8h, v0.8b, v1.8b1873; CHECK-NEXT: ret1874entry:1875 %vabd.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %a, <8 x i8> %b)1876 %vmovl.i.i = zext <8 x i8> %vabd.i.i to <8 x i16>1877 ret <8 x i16> %vmovl.i.i1878}1879 1880define <4 x i32> @test_vabdl_u16(<4 x i16> %a, <4 x i16> %b) {1881; CHECK-LABEL: test_vabdl_u16:1882; CHECK: // %bb.0: // %entry1883; CHECK-NEXT: uabdl v0.4s, v0.4h, v1.4h1884; CHECK-NEXT: ret1885entry:1886 %vabd2.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %a, <4 x i16> %b)1887 %vmovl.i.i = zext <4 x i16> %vabd2.i.i to <4 x i32>1888 ret <4 x i32> %vmovl.i.i1889}1890 1891define <2 x i64> @test_vabdl_u32(<2 x i32> %a, <2 x i32> %b) {1892; CHECK-LABEL: test_vabdl_u32:1893; CHECK: // %bb.0: // %entry1894; CHECK-NEXT: uabdl v0.2d, v0.2s, v1.2s1895; CHECK-NEXT: ret1896entry:1897 %vabd2.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %a, <2 x i32> %b)1898 %vmovl.i.i = zext <2 x i32> %vabd2.i.i to <2 x i64>1899 ret <2 x i64> %vmovl.i.i1900}1901 1902define <8 x i16> @test_vabal_s8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {1903; CHECK-LABEL: test_vabal_s8:1904; CHECK: // %bb.0: // %entry1905; CHECK-NEXT: sabal v0.8h, v1.8b, v2.8b1906; CHECK-NEXT: ret1907entry:1908 %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %b, <8 x i8> %c)1909 %vmovl.i.i.i = zext <8 x i8> %vabd.i.i.i to <8 x i16>1910 %add.i = add <8 x i16> %vmovl.i.i.i, %a1911 ret <8 x i16> %add.i1912}1913 1914define <4 x i32> @test_vabal_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {1915; CHECK-LABEL: test_vabal_s16:1916; CHECK: // %bb.0: // %entry1917; CHECK-NEXT: sabal v0.4s, v1.4h, v2.4h1918; CHECK-NEXT: ret1919entry:1920 %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %b, <4 x i16> %c)1921 %vmovl.i.i.i = zext <4 x i16> %vabd2.i.i.i to <4 x i32>1922 %add.i = add <4 x i32> %vmovl.i.i.i, %a1923 ret <4 x i32> %add.i1924}1925 1926define <2 x i64> @test_vabal_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {1927; CHECK-LABEL: test_vabal_s32:1928; CHECK: // %bb.0: // %entry1929; CHECK-NEXT: sabal v0.2d, v1.2s, v2.2s1930; CHECK-NEXT: ret1931entry:1932 %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %b, <2 x i32> %c)1933 %vmovl.i.i.i = zext <2 x i32> %vabd2.i.i.i to <2 x i64>1934 %add.i = add <2 x i64> %vmovl.i.i.i, %a1935 ret <2 x i64> %add.i1936}1937 1938define <8 x i16> @test_vabal_u8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {1939; CHECK-LABEL: test_vabal_u8:1940; CHECK: // %bb.0: // %entry1941; CHECK-NEXT: uabal v0.8h, v1.8b, v2.8b1942; CHECK-NEXT: ret1943entry:1944 %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %b, <8 x i8> %c)1945 %vmovl.i.i.i = zext <8 x i8> %vabd.i.i.i to <8 x i16>1946 %add.i = add <8 x i16> %vmovl.i.i.i, %a1947 ret <8 x i16> %add.i1948}1949 1950define <4 x i32> @test_vabal_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {1951; CHECK-LABEL: test_vabal_u16:1952; CHECK: // %bb.0: // %entry1953; CHECK-NEXT: uabal v0.4s, v1.4h, v2.4h1954; CHECK-NEXT: ret1955entry:1956 %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %b, <4 x i16> %c)1957 %vmovl.i.i.i = zext <4 x i16> %vabd2.i.i.i to <4 x i32>1958 %add.i = add <4 x i32> %vmovl.i.i.i, %a1959 ret <4 x i32> %add.i1960}1961 1962define <2 x i64> @test_vabal_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {1963; CHECK-LABEL: test_vabal_u32:1964; CHECK: // %bb.0: // %entry1965; CHECK-NEXT: uabal v0.2d, v1.2s, v2.2s1966; CHECK-NEXT: ret1967entry:1968 %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %b, <2 x i32> %c)1969 %vmovl.i.i.i = zext <2 x i32> %vabd2.i.i.i to <2 x i64>1970 %add.i = add <2 x i64> %vmovl.i.i.i, %a1971 ret <2 x i64> %add.i1972}1973 1974define <8 x i16> @test_vabdl_high_s8(<16 x i8> %a, <16 x i8> %b) {1975; CHECK-LABEL: test_vabdl_high_s8:1976; CHECK: // %bb.0: // %entry1977; CHECK-NEXT: sabdl2 v0.8h, v0.16b, v1.16b1978; CHECK-NEXT: ret1979entry:1980 %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1981 %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1982 %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)1983 %vmovl.i.i.i = zext <8 x i8> %vabd.i.i.i to <8 x i16>1984 ret <8 x i16> %vmovl.i.i.i1985}1986 1987define <4 x i32> @test_vabdl_high_s16(<8 x i16> %a, <8 x i16> %b) {1988; CHECK-LABEL: test_vabdl_high_s16:1989; CHECK: // %bb.0: // %entry1990; CHECK-NEXT: sabdl2 v0.4s, v0.8h, v1.8h1991; CHECK-NEXT: ret1992entry:1993 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1994 %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1995 %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)1996 %vmovl.i.i.i = zext <4 x i16> %vabd2.i.i.i to <4 x i32>1997 ret <4 x i32> %vmovl.i.i.i1998}1999 2000define <2 x i64> @test_vabdl_high_s32(<4 x i32> %a, <4 x i32> %b) {2001; CHECK-LABEL: test_vabdl_high_s32:2002; CHECK: // %bb.0: // %entry2003; CHECK-NEXT: sabdl2 v0.2d, v0.4s, v1.4s2004; CHECK-NEXT: ret2005entry:2006 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2007 %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2008 %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2009 %vmovl.i.i.i = zext <2 x i32> %vabd2.i.i.i to <2 x i64>2010 ret <2 x i64> %vmovl.i.i.i2011}2012 2013define <8 x i16> @test_vabdl_high_u8(<16 x i8> %a, <16 x i8> %b) {2014; CHECK-LABEL: test_vabdl_high_u8:2015; CHECK: // %bb.0: // %entry2016; CHECK-NEXT: uabdl2 v0.8h, v0.16b, v1.16b2017; CHECK-NEXT: ret2018entry:2019 %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2020 %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2021 %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2022 %vmovl.i.i.i = zext <8 x i8> %vabd.i.i.i to <8 x i16>2023 ret <8 x i16> %vmovl.i.i.i2024}2025 2026define <4 x i32> @test_vabdl_high_u16(<8 x i16> %a, <8 x i16> %b) {2027; CHECK-LABEL: test_vabdl_high_u16:2028; CHECK: // %bb.0: // %entry2029; CHECK-NEXT: uabdl2 v0.4s, v0.8h, v1.8h2030; CHECK-NEXT: ret2031entry:2032 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2033 %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2034 %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2035 %vmovl.i.i.i = zext <4 x i16> %vabd2.i.i.i to <4 x i32>2036 ret <4 x i32> %vmovl.i.i.i2037}2038 2039define <2 x i64> @test_vabdl_high_u32(<4 x i32> %a, <4 x i32> %b) {2040; CHECK-LABEL: test_vabdl_high_u32:2041; CHECK: // %bb.0: // %entry2042; CHECK-NEXT: uabdl2 v0.2d, v0.4s, v1.4s2043; CHECK-NEXT: ret2044entry:2045 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2046 %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2047 %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2048 %vmovl.i.i.i = zext <2 x i32> %vabd2.i.i.i to <2 x i64>2049 ret <2 x i64> %vmovl.i.i.i2050}2051 2052define <8 x i16> @test_vabal_high_s8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {2053; CHECK-LABEL: test_vabal_high_s8:2054; CHECK: // %bb.0: // %entry2055; CHECK-NEXT: sabal2 v0.8h, v1.16b, v2.16b2056; CHECK-NEXT: ret2057entry:2058 %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2059 %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2060 %vabd.i.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2061 %vmovl.i.i.i.i = zext <8 x i8> %vabd.i.i.i.i to <8 x i16>2062 %add.i.i = add <8 x i16> %vmovl.i.i.i.i, %a2063 ret <8 x i16> %add.i.i2064}2065 2066define <4 x i32> @test_vabal_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2067; CHECK-LABEL: test_vabal_high_s16:2068; CHECK: // %bb.0: // %entry2069; CHECK-NEXT: sabal2 v0.4s, v1.8h, v2.8h2070; CHECK-NEXT: ret2071entry:2072 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2073 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2074 %vabd2.i.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2075 %vmovl.i.i.i.i = zext <4 x i16> %vabd2.i.i.i.i to <4 x i32>2076 %add.i.i = add <4 x i32> %vmovl.i.i.i.i, %a2077 ret <4 x i32> %add.i.i2078}2079 2080define <2 x i64> @test_vabal_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2081; CHECK-LABEL: test_vabal_high_s32:2082; CHECK: // %bb.0: // %entry2083; CHECK-NEXT: sabal2 v0.2d, v1.4s, v2.4s2084; CHECK-NEXT: ret2085entry:2086 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2087 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2088 %vabd2.i.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2089 %vmovl.i.i.i.i = zext <2 x i32> %vabd2.i.i.i.i to <2 x i64>2090 %add.i.i = add <2 x i64> %vmovl.i.i.i.i, %a2091 ret <2 x i64> %add.i.i2092}2093 2094define <8 x i16> @test_vabal_high_u8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {2095; CHECK-LABEL: test_vabal_high_u8:2096; CHECK: // %bb.0: // %entry2097; CHECK-NEXT: uabal2 v0.8h, v1.16b, v2.16b2098; CHECK-NEXT: ret2099entry:2100 %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2101 %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2102 %vabd.i.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2103 %vmovl.i.i.i.i = zext <8 x i8> %vabd.i.i.i.i to <8 x i16>2104 %add.i.i = add <8 x i16> %vmovl.i.i.i.i, %a2105 ret <8 x i16> %add.i.i2106}2107 2108define <4 x i32> @test_vabal_high_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2109; CHECK-LABEL: test_vabal_high_u16:2110; CHECK: // %bb.0: // %entry2111; CHECK-NEXT: uabal2 v0.4s, v1.8h, v2.8h2112; CHECK-NEXT: ret2113entry:2114 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2115 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2116 %vabd2.i.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2117 %vmovl.i.i.i.i = zext <4 x i16> %vabd2.i.i.i.i to <4 x i32>2118 %add.i.i = add <4 x i32> %vmovl.i.i.i.i, %a2119 ret <4 x i32> %add.i.i2120}2121 2122define <2 x i64> @test_vabal_high_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2123; CHECK-LABEL: test_vabal_high_u32:2124; CHECK: // %bb.0: // %entry2125; CHECK-NEXT: uabal2 v0.2d, v1.4s, v2.4s2126; CHECK-NEXT: ret2127entry:2128 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2129 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2130 %vabd2.i.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2131 %vmovl.i.i.i.i = zext <2 x i32> %vabd2.i.i.i.i to <2 x i64>2132 %add.i.i = add <2 x i64> %vmovl.i.i.i.i, %a2133 ret <2 x i64> %add.i.i2134}2135 2136define <8 x i16> @test_vmull_s8(<8 x i8> %a, <8 x i8> %b) {2137; CHECK-LABEL: test_vmull_s8:2138; CHECK: // %bb.0: // %entry2139; CHECK-NEXT: smull v0.8h, v0.8b, v1.8b2140; CHECK-NEXT: ret2141entry:2142 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %a, <8 x i8> %b)2143 ret <8 x i16> %vmull.i2144}2145 2146define <4 x i32> @test_vmull_s16(<4 x i16> %a, <4 x i16> %b) {2147; CHECK-LABEL: test_vmull_s16:2148; CHECK: // %bb.0: // %entry2149; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h2150; CHECK-NEXT: ret2151entry:2152 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %b)2153 ret <4 x i32> %vmull2.i2154}2155 2156define <2 x i64> @test_vmull_s32(<2 x i32> %a, <2 x i32> %b) {2157; CHECK-LABEL: test_vmull_s32:2158; CHECK: // %bb.0: // %entry2159; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s2160; CHECK-NEXT: ret2161entry:2162 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %b)2163 ret <2 x i64> %vmull2.i2164}2165 2166define <8 x i16> @test_vmull_u8(<8 x i8> %a, <8 x i8> %b) {2167; CHECK-LABEL: test_vmull_u8:2168; CHECK: // %bb.0: // %entry2169; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b2170; CHECK-NEXT: ret2171entry:2172 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %a, <8 x i8> %b)2173 ret <8 x i16> %vmull.i2174}2175 2176define <4 x i32> @test_vmull_u16(<4 x i16> %a, <4 x i16> %b) {2177; CHECK-LABEL: test_vmull_u16:2178; CHECK: // %bb.0: // %entry2179; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h2180; CHECK-NEXT: ret2181entry:2182 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %b)2183 ret <4 x i32> %vmull2.i2184}2185 2186define <2 x i64> @test_vmull_u32(<2 x i32> %a, <2 x i32> %b) {2187; CHECK-LABEL: test_vmull_u32:2188; CHECK: // %bb.0: // %entry2189; CHECK-NEXT: umull v0.2d, v0.2s, v1.2s2190; CHECK-NEXT: ret2191entry:2192 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %b)2193 ret <2 x i64> %vmull2.i2194}2195 2196define <8 x i16> @test_vmull_high_s8(<16 x i8> %a, <16 x i8> %b) {2197; CHECK-LABEL: test_vmull_high_s8:2198; CHECK: // %bb.0: // %entry2199; CHECK-NEXT: smull2 v0.8h, v0.16b, v1.16b2200; CHECK-NEXT: ret2201entry:2202 %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2203 %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2204 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2205 ret <8 x i16> %vmull.i.i2206}2207 2208define <4 x i32> @test_vmull_high_s16(<8 x i16> %a, <8 x i16> %b) {2209; CHECK-LABEL: test_vmull_high_s16:2210; CHECK: // %bb.0: // %entry2211; CHECK-NEXT: smull2 v0.4s, v0.8h, v1.8h2212; CHECK-NEXT: ret2213entry:2214 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2215 %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2216 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2217 ret <4 x i32> %vmull2.i.i2218}2219 2220define <2 x i64> @test_vmull_high_s32(<4 x i32> %a, <4 x i32> %b) {2221; CHECK-LABEL: test_vmull_high_s32:2222; CHECK: // %bb.0: // %entry2223; CHECK-NEXT: smull2 v0.2d, v0.4s, v1.4s2224; CHECK-NEXT: ret2225entry:2226 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2227 %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2228 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2229 ret <2 x i64> %vmull2.i.i2230}2231 2232define <8 x i16> @test_vmull_high_u8(<16 x i8> %a, <16 x i8> %b) {2233; CHECK-LABEL: test_vmull_high_u8:2234; CHECK: // %bb.0: // %entry2235; CHECK-NEXT: umull2 v0.8h, v0.16b, v1.16b2236; CHECK-NEXT: ret2237entry:2238 %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2239 %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2240 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2241 ret <8 x i16> %vmull.i.i2242}2243 2244define <4 x i32> @test_vmull_high_u16(<8 x i16> %a, <8 x i16> %b) {2245; CHECK-LABEL: test_vmull_high_u16:2246; CHECK: // %bb.0: // %entry2247; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h2248; CHECK-NEXT: ret2249entry:2250 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2251 %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2252 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2253 ret <4 x i32> %vmull2.i.i2254}2255 2256define <2 x i64> @test_vmull_high_u32(<4 x i32> %a, <4 x i32> %b) {2257; CHECK-LABEL: test_vmull_high_u32:2258; CHECK: // %bb.0: // %entry2259; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s2260; CHECK-NEXT: ret2261entry:2262 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2263 %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2264 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2265 ret <2 x i64> %vmull2.i.i2266}2267 2268define <8 x i16> @test_vmlal_s8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {2269; CHECK-LABEL: test_vmlal_s8:2270; CHECK: // %bb.0: // %entry2271; CHECK-NEXT: smlal v0.8h, v1.8b, v2.8b2272; CHECK-NEXT: ret2273entry:2274 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %b, <8 x i8> %c)2275 %add.i = add <8 x i16> %vmull.i.i, %a2276 ret <8 x i16> %add.i2277}2278 2279define <4 x i32> @test_vmlal_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {2280; CHECK-LABEL: test_vmlal_s16:2281; CHECK: // %bb.0: // %entry2282; CHECK-NEXT: smlal v0.4s, v1.4h, v2.4h2283; CHECK-NEXT: ret2284entry:2285 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %b, <4 x i16> %c)2286 %add.i = add <4 x i32> %vmull2.i.i, %a2287 ret <4 x i32> %add.i2288}2289 2290define <2 x i64> @test_vmlal_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {2291; CHECK-LABEL: test_vmlal_s32:2292; CHECK: // %bb.0: // %entry2293; CHECK-NEXT: smlal v0.2d, v1.2s, v2.2s2294; CHECK-NEXT: ret2295entry:2296 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %c)2297 %add.i = add <2 x i64> %vmull2.i.i, %a2298 ret <2 x i64> %add.i2299}2300 2301define <8 x i16> @test_vmlal_u8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {2302; CHECK-LABEL: test_vmlal_u8:2303; CHECK: // %bb.0: // %entry2304; CHECK-NEXT: umlal v0.8h, v1.8b, v2.8b2305; CHECK-NEXT: ret2306entry:2307 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %b, <8 x i8> %c)2308 %add.i = add <8 x i16> %vmull.i.i, %a2309 ret <8 x i16> %add.i2310}2311 2312define <4 x i32> @test_vmlal_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {2313; CHECK-LABEL: test_vmlal_u16:2314; CHECK: // %bb.0: // %entry2315; CHECK-NEXT: umlal v0.4s, v1.4h, v2.4h2316; CHECK-NEXT: ret2317entry:2318 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %b, <4 x i16> %c)2319 %add.i = add <4 x i32> %vmull2.i.i, %a2320 ret <4 x i32> %add.i2321}2322 2323define <2 x i64> @test_vmlal_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {2324; CHECK-LABEL: test_vmlal_u32:2325; CHECK: // %bb.0: // %entry2326; CHECK-NEXT: umlal v0.2d, v1.2s, v2.2s2327; CHECK-NEXT: ret2328entry:2329 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %b, <2 x i32> %c)2330 %add.i = add <2 x i64> %vmull2.i.i, %a2331 ret <2 x i64> %add.i2332}2333 2334define <8 x i16> @test_vmlal_high_s8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {2335; CHECK-LABEL: test_vmlal_high_s8:2336; CHECK: // %bb.0: // %entry2337; CHECK-NEXT: smlal2 v0.8h, v1.16b, v2.16b2338; CHECK-NEXT: ret2339entry:2340 %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2341 %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2342 %vmull.i.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2343 %add.i.i = add <8 x i16> %vmull.i.i.i, %a2344 ret <8 x i16> %add.i.i2345}2346 2347define <4 x i32> @test_vmlal_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2348; CHECK-LABEL: test_vmlal_high_s16:2349; CHECK: // %bb.0: // %entry2350; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.8h2351; CHECK-NEXT: ret2352entry:2353 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2354 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2355 %vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2356 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a2357 ret <4 x i32> %add.i.i2358}2359 2360define <2 x i64> @test_vmlal_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2361; CHECK-LABEL: test_vmlal_high_s32:2362; CHECK: // %bb.0: // %entry2363; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s2364; CHECK-NEXT: ret2365entry:2366 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2367 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2368 %vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2369 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a2370 ret <2 x i64> %add.i.i2371}2372 2373define <8 x i16> @test_vmlal_high_u8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {2374; CHECK-LABEL: test_vmlal_high_u8:2375; CHECK: // %bb.0: // %entry2376; CHECK-NEXT: umlal2 v0.8h, v1.16b, v2.16b2377; CHECK-NEXT: ret2378entry:2379 %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2380 %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2381 %vmull.i.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2382 %add.i.i = add <8 x i16> %vmull.i.i.i, %a2383 ret <8 x i16> %add.i.i2384}2385 2386define <4 x i32> @test_vmlal_high_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2387; CHECK-LABEL: test_vmlal_high_u16:2388; CHECK: // %bb.0: // %entry2389; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.8h2390; CHECK-NEXT: ret2391entry:2392 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2393 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2394 %vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2395 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a2396 ret <4 x i32> %add.i.i2397}2398 2399define <2 x i64> @test_vmlal_high_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2400; CHECK-LABEL: test_vmlal_high_u32:2401; CHECK: // %bb.0: // %entry2402; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s2403; CHECK-NEXT: ret2404entry:2405 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2406 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2407 %vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2408 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a2409 ret <2 x i64> %add.i.i2410}2411 2412define <8 x i16> @test_vmlsl_s8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {2413; CHECK-LABEL: test_vmlsl_s8:2414; CHECK: // %bb.0: // %entry2415; CHECK-NEXT: smlsl v0.8h, v1.8b, v2.8b2416; CHECK-NEXT: ret2417entry:2418 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %b, <8 x i8> %c)2419 %sub.i = sub <8 x i16> %a, %vmull.i.i2420 ret <8 x i16> %sub.i2421}2422 2423define <4 x i32> @test_vmlsl_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {2424; CHECK-LABEL: test_vmlsl_s16:2425; CHECK: // %bb.0: // %entry2426; CHECK-NEXT: smlsl v0.4s, v1.4h, v2.4h2427; CHECK-NEXT: ret2428entry:2429 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %b, <4 x i16> %c)2430 %sub.i = sub <4 x i32> %a, %vmull2.i.i2431 ret <4 x i32> %sub.i2432}2433 2434define <2 x i64> @test_vmlsl_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {2435; CHECK-LABEL: test_vmlsl_s32:2436; CHECK: // %bb.0: // %entry2437; CHECK-NEXT: smlsl v0.2d, v1.2s, v2.2s2438; CHECK-NEXT: ret2439entry:2440 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %c)2441 %sub.i = sub <2 x i64> %a, %vmull2.i.i2442 ret <2 x i64> %sub.i2443}2444 2445define <8 x i16> @test_vmlsl_u8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {2446; CHECK-LABEL: test_vmlsl_u8:2447; CHECK: // %bb.0: // %entry2448; CHECK-NEXT: umlsl v0.8h, v1.8b, v2.8b2449; CHECK-NEXT: ret2450entry:2451 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %b, <8 x i8> %c)2452 %sub.i = sub <8 x i16> %a, %vmull.i.i2453 ret <8 x i16> %sub.i2454}2455 2456define <4 x i32> @test_vmlsl_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {2457; CHECK-LABEL: test_vmlsl_u16:2458; CHECK: // %bb.0: // %entry2459; CHECK-NEXT: umlsl v0.4s, v1.4h, v2.4h2460; CHECK-NEXT: ret2461entry:2462 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %b, <4 x i16> %c)2463 %sub.i = sub <4 x i32> %a, %vmull2.i.i2464 ret <4 x i32> %sub.i2465}2466 2467define <2 x i64> @test_vmlsl_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {2468; CHECK-LABEL: test_vmlsl_u32:2469; CHECK: // %bb.0: // %entry2470; CHECK-NEXT: umlsl v0.2d, v1.2s, v2.2s2471; CHECK-NEXT: ret2472entry:2473 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %b, <2 x i32> %c)2474 %sub.i = sub <2 x i64> %a, %vmull2.i.i2475 ret <2 x i64> %sub.i2476}2477 2478define <8 x i16> @test_vmlsl_high_s8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {2479; CHECK-LABEL: test_vmlsl_high_s8:2480; CHECK: // %bb.0: // %entry2481; CHECK-NEXT: smlsl2 v0.8h, v1.16b, v2.16b2482; CHECK-NEXT: ret2483entry:2484 %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2485 %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2486 %vmull.i.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2487 %sub.i.i = sub <8 x i16> %a, %vmull.i.i.i2488 ret <8 x i16> %sub.i.i2489}2490 2491define <4 x i32> @test_vmlsl_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2492; CHECK-LABEL: test_vmlsl_high_s16:2493; CHECK: // %bb.0: // %entry2494; CHECK-NEXT: smlsl2 v0.4s, v1.8h, v2.8h2495; CHECK-NEXT: ret2496entry:2497 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2498 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2499 %vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2500 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i2501 ret <4 x i32> %sub.i.i2502}2503 2504define <2 x i64> @test_vmlsl_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2505; CHECK-LABEL: test_vmlsl_high_s32:2506; CHECK: // %bb.0: // %entry2507; CHECK-NEXT: smlsl2 v0.2d, v1.4s, v2.4s2508; CHECK-NEXT: ret2509entry:2510 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2511 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2512 %vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2513 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i2514 ret <2 x i64> %sub.i.i2515}2516 2517define <8 x i16> @test_vmlsl_high_u8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {2518; CHECK-LABEL: test_vmlsl_high_u8:2519; CHECK: // %bb.0: // %entry2520; CHECK-NEXT: umlsl2 v0.8h, v1.16b, v2.16b2521; CHECK-NEXT: ret2522entry:2523 %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2524 %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2525 %vmull.i.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2526 %sub.i.i = sub <8 x i16> %a, %vmull.i.i.i2527 ret <8 x i16> %sub.i.i2528}2529 2530define <4 x i32> @test_vmlsl_high_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2531; CHECK-LABEL: test_vmlsl_high_u16:2532; CHECK: // %bb.0: // %entry2533; CHECK-NEXT: umlsl2 v0.4s, v1.8h, v2.8h2534; CHECK-NEXT: ret2535entry:2536 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2537 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2538 %vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2539 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i2540 ret <4 x i32> %sub.i.i2541}2542 2543define <2 x i64> @test_vmlsl_high_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2544; CHECK-LABEL: test_vmlsl_high_u32:2545; CHECK: // %bb.0: // %entry2546; CHECK-NEXT: umlsl2 v0.2d, v1.4s, v2.4s2547; CHECK-NEXT: ret2548entry:2549 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2550 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2551 %vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2552 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i2553 ret <2 x i64> %sub.i.i2554}2555 2556define <4 x i32> @test_vqdmull_s16(<4 x i16> %a, <4 x i16> %b) {2557; CHECK-LABEL: test_vqdmull_s16:2558; CHECK: // %bb.0: // %entry2559; CHECK-NEXT: sqdmull v0.4s, v0.4h, v1.4h2560; CHECK-NEXT: ret2561entry:2562 %vqdmull2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %a, <4 x i16> %b)2563 ret <4 x i32> %vqdmull2.i2564}2565 2566define <2 x i64> @test_vqdmull_s32(<2 x i32> %a, <2 x i32> %b) {2567; CHECK-LABEL: test_vqdmull_s32:2568; CHECK: // %bb.0: // %entry2569; CHECK-NEXT: sqdmull v0.2d, v0.2s, v1.2s2570; CHECK-NEXT: ret2571entry:2572 %vqdmull2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %a, <2 x i32> %b)2573 ret <2 x i64> %vqdmull2.i2574}2575 2576define <4 x i32> @test_vqdmlal_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {2577; CHECK-LABEL: test_vqdmlal_s16:2578; CHECK: // %bb.0: // %entry2579; CHECK-NEXT: sqdmlal v0.4s, v1.4h, v2.4h2580; CHECK-NEXT: ret2581entry:2582 %vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)2583 %vqdmlal4.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2.i)2584 ret <4 x i32> %vqdmlal4.i2585}2586 2587define <2 x i64> @test_vqdmlal_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {2588; CHECK-LABEL: test_vqdmlal_s32:2589; CHECK: // %bb.0: // %entry2590; CHECK-NEXT: sqdmlal v0.2d, v1.2s, v2.2s2591; CHECK-NEXT: ret2592entry:2593 %vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)2594 %vqdmlal4.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2.i)2595 ret <2 x i64> %vqdmlal4.i2596}2597 2598define <4 x i32> @test_vqdmlsl_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {2599; CHECK-LABEL: test_vqdmlsl_s16:2600; CHECK: // %bb.0: // %entry2601; CHECK-NEXT: sqdmlsl v0.4s, v1.4h, v2.4h2602; CHECK-NEXT: ret2603entry:2604 %vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)2605 %vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2.i)2606 ret <4 x i32> %vqdmlsl4.i2607}2608 2609define <2 x i64> @test_vqdmlsl_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {2610; CHECK-LABEL: test_vqdmlsl_s32:2611; CHECK: // %bb.0: // %entry2612; CHECK-NEXT: sqdmlsl v0.2d, v1.2s, v2.2s2613; CHECK-NEXT: ret2614entry:2615 %vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)2616 %vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2.i)2617 ret <2 x i64> %vqdmlsl4.i2618}2619 2620define <4 x i32> @test_vqdmull_high_s16(<8 x i16> %a, <8 x i16> %b) {2621; CHECK-LABEL: test_vqdmull_high_s16:2622; CHECK: // %bb.0: // %entry2623; CHECK-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h2624; CHECK-NEXT: ret2625entry:2626 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2627 %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2628 %vqdmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2629 ret <4 x i32> %vqdmull2.i.i2630}2631 2632define <2 x i64> @test_vqdmull_high_s32(<4 x i32> %a, <4 x i32> %b) {2633; CHECK-LABEL: test_vqdmull_high_s32:2634; CHECK: // %bb.0: // %entry2635; CHECK-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s2636; CHECK-NEXT: ret2637entry:2638 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2639 %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2640 %vqdmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2641 ret <2 x i64> %vqdmull2.i.i2642}2643 2644define <4 x i32> @test_vqdmlal_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2645; CHECK-LABEL: test_vqdmlal_high_s16:2646; CHECK: // %bb.0: // %entry2647; CHECK-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h2648; CHECK-NEXT: ret2649entry:2650 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2651 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2652 %vqdmlal2.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2653 %vqdmlal4.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2.i.i)2654 ret <4 x i32> %vqdmlal4.i.i2655}2656 2657define <2 x i64> @test_vqdmlal_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2658; CHECK-LABEL: test_vqdmlal_high_s32:2659; CHECK: // %bb.0: // %entry2660; CHECK-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s2661; CHECK-NEXT: ret2662entry:2663 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2664 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2665 %vqdmlal2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2666 %vqdmlal4.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2.i.i)2667 ret <2 x i64> %vqdmlal4.i.i2668}2669 2670define <4 x i32> @test_vqdmlsl_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {2671; CHECK-LABEL: test_vqdmlsl_high_s16:2672; CHECK: // %bb.0: // %entry2673; CHECK-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h2674; CHECK-NEXT: ret2675entry:2676 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2677 %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2678 %vqdmlsl2.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2679 %vqdmlsl4.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2.i.i)2680 ret <4 x i32> %vqdmlsl4.i.i2681}2682 2683define <2 x i64> @test_vqdmlsl_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {2684; CHECK-LABEL: test_vqdmlsl_high_s32:2685; CHECK: // %bb.0: // %entry2686; CHECK-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s2687; CHECK-NEXT: ret2688entry:2689 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2690 %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>2691 %vqdmlsl2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %shuffle.i3.i)2692 %vqdmlsl4.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2.i.i)2693 ret <2 x i64> %vqdmlsl4.i.i2694}2695 2696define <8 x i16> @test_vmull_p8(<8 x i8> %a, <8 x i8> %b) {2697; CHECK-LABEL: test_vmull_p8:2698; CHECK: // %bb.0: // %entry2699; CHECK-NEXT: pmull v0.8h, v0.8b, v1.8b2700; CHECK-NEXT: ret2701entry:2702 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %a, <8 x i8> %b)2703 ret <8 x i16> %vmull.i2704}2705 2706define <8 x i16> @test_vmull_high_p8(<16 x i8> %a, <16 x i8> %b) {2707; CHECK-LABEL: test_vmull_high_p8:2708; CHECK: // %bb.0: // %entry2709; CHECK-NEXT: pmull2 v0.8h, v0.16b, v1.16b2710; CHECK-NEXT: ret2711entry:2712 %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2713 %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>2714 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %shuffle.i3.i)2715 ret <8 x i16> %vmull.i.i2716}2717 2718define i128 @test_vmull_p64(i64 %a, i64 %b) #4 {2719; CHECK-SD-LABEL: test_vmull_p64:2720; CHECK-SD: // %bb.0: // %entry2721; CHECK-SD-NEXT: fmov d0, x12722; CHECK-SD-NEXT: fmov d1, x02723; CHECK-SD-NEXT: pmull v0.1q, v1.1d, v0.1d2724; CHECK-SD-NEXT: mov x1, v0.d[1]2725; CHECK-SD-NEXT: fmov x0, d02726; CHECK-SD-NEXT: ret2727;2728; CHECK-GI-LABEL: test_vmull_p64:2729; CHECK-GI: // %bb.0: // %entry2730; CHECK-GI-NEXT: fmov d0, x02731; CHECK-GI-NEXT: fmov d1, x12732; CHECK-GI-NEXT: pmull v0.1q, v0.1d, v1.1d2733; CHECK-GI-NEXT: mov d1, v0.d[1]2734; CHECK-GI-NEXT: fmov x0, d02735; CHECK-GI-NEXT: fmov x1, d12736; CHECK-GI-NEXT: ret2737entry:2738 %vmull2.i = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %a, i64 %b)2739 %vmull3.i = bitcast <16 x i8> %vmull2.i to i1282740 ret i128 %vmull3.i2741}2742 2743define i128 @test_vmull_high_p64(<2 x i64> %a, <2 x i64> %b) #4 {2744; CHECK-SD-LABEL: test_vmull_high_p64:2745; CHECK-SD: // %bb.0: // %entry2746; CHECK-SD-NEXT: pmull2 v0.1q, v0.2d, v1.2d2747; CHECK-SD-NEXT: mov x1, v0.d[1]2748; CHECK-SD-NEXT: fmov x0, d02749; CHECK-SD-NEXT: ret2750;2751; CHECK-GI-LABEL: test_vmull_high_p64:2752; CHECK-GI: // %bb.0: // %entry2753; CHECK-GI-NEXT: mov d0, v0.d[1]2754; CHECK-GI-NEXT: mov d1, v1.d[1]2755; CHECK-GI-NEXT: pmull v0.1q, v0.1d, v1.1d2756; CHECK-GI-NEXT: mov d1, v0.d[1]2757; CHECK-GI-NEXT: fmov x0, d02758; CHECK-GI-NEXT: fmov x1, d12759; CHECK-GI-NEXT: ret2760entry:2761 %0 = extractelement <2 x i64> %a, i32 12762 %1 = extractelement <2 x i64> %b, i32 12763 %vmull2.i.i = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %0, i64 %1) #12764 %vmull3.i.i = bitcast <16 x i8> %vmull2.i.i to i1282765 ret i128 %vmull3.i.i2766}2767 2768define <8 x i16> @cmplx_mul_combined_re_im(<8 x i16> noundef %a, i64 %scale.coerce) {2769; CHECK-SD-LABEL: cmplx_mul_combined_re_im:2770; CHECK-SD: // %bb.0: // %entry2771; CHECK-SD-NEXT: lsr x8, x0, #162772; CHECK-SD-NEXT: movi v1.2d, #0xffff0000ffff00002773; CHECK-SD-NEXT: rev32 v4.8h, v0.8h2774; CHECK-SD-NEXT: dup v2.8h, w82775; CHECK-SD-NEXT: sqneg v3.8h, v2.8h2776; CHECK-SD-NEXT: bsl v1.16b, v2.16b, v3.16b2777; CHECK-SD-NEXT: fmov d3, x02778; CHECK-SD-NEXT: sqdmull v2.4s, v4.4h, v1.4h2779; CHECK-SD-NEXT: sqdmull2 v1.4s, v4.8h, v1.8h2780; CHECK-SD-NEXT: sqdmlal v2.4s, v0.4h, v3.h[0]2781; CHECK-SD-NEXT: sqdmlal2 v1.4s, v0.8h, v3.h[0]2782; CHECK-SD-NEXT: uzp2 v0.8h, v2.8h, v1.8h2783; CHECK-SD-NEXT: ret2784;2785; CHECK-GI-LABEL: cmplx_mul_combined_re_im:2786; CHECK-GI: // %bb.0: // %entry2787; CHECK-GI-NEXT: lsr x9, x0, #162788; CHECK-GI-NEXT: adrp x8, .LCPI192_02789; CHECK-GI-NEXT: rev32 v4.8h, v0.8h2790; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI192_0]2791; CHECK-GI-NEXT: fmov d1, x92792; CHECK-GI-NEXT: dup v2.8h, v1.h[0]2793; CHECK-GI-NEXT: sqneg v1.8h, v2.8h2794; CHECK-GI-NEXT: tbl v1.16b, { v1.16b, v2.16b }, v3.16b2795; CHECK-GI-NEXT: mov d2, v0.d[1]2796; CHECK-GI-NEXT: fmov d3, x02797; CHECK-GI-NEXT: sqdmull v2.4s, v2.4h, v3.h[0]2798; CHECK-GI-NEXT: sqdmull v5.4s, v4.4h, v1.4h2799; CHECK-GI-NEXT: sqdmlal v5.4s, v0.4h, v3.h[0]2800; CHECK-GI-NEXT: sqdmlal2 v2.4s, v4.8h, v1.8h2801; CHECK-GI-NEXT: uzp2 v0.8h, v5.8h, v2.8h2802; CHECK-GI-NEXT: ret2803entry:2804 %scale.sroa.2.0.extract.shift23 = lshr i64 %scale.coerce, 162805 %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>2806 %vec.scale.coerce = bitcast i64 %scale.coerce to <4 x i16>2807 %vec.scale.sroa.2.0.extract.shift23 = bitcast i64 %scale.sroa.2.0.extract.shift23 to <4 x i16>2808 %vecinit7.i25 = shufflevector <4 x i16> %vec.scale.sroa.2.0.extract.shift23, <4 x i16> poison, <8 x i32> zeroinitializer2809 %vqnegq_v1.i = tail call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %vecinit7.i25)2810 %0 = shufflevector <8 x i16> %vqnegq_v1.i, <8 x i16> %vecinit7.i25, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>2811 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2812 %shuffle.i3.i = shufflevector <4 x i16> %vec.scale.coerce, <4 x i16> poison, <4 x i32> zeroinitializer2813 %vqdmull_v2.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %shuffle.i3.i)2814 %shuffle.i.i26 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2815 %vqdmull_v2.i.i28 = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i26, <4 x i16> %shuffle.i3.i)2816 %shuffle.i.i29 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2817 %shuffle.i3.i30 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2818 %vqdmlal2.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i29, <4 x i16> %shuffle.i3.i30)2819 %vqdmlal_v3.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %vqdmull_v2.i.i, <4 x i32> %vqdmlal2.i.i)2820 %shuffle.i.i31 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2821 %shuffle.i3.i32 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>2822 %vqdmlal2.i.i33 = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i31, <4 x i16> %shuffle.i3.i32)2823 %vqdmlal_v3.i.i34 = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %vqdmull_v2.i.i28, <4 x i32> %vqdmlal2.i.i33)2824 %1 = bitcast <4 x i32> %vqdmlal_v3.i.i to <8 x i16>2825 %2 = bitcast <4 x i32> %vqdmlal_v3.i.i34 to <8 x i16>2826 %shuffle.i35 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>2827 ret <8 x i16> %shuffle.i352828}2829 2830declare <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16>)2831