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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=arm64-none-linux-gnu -mattr=+neon -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)6declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)7declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)8declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)9declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)10declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)11declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)12declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)13declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)14declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)15declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>)16declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>)17declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)18declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)19declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)20declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)21declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>)22declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)23declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)24declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)25declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)26declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)27declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)28declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)29declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)30declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)31declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)32declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)33declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)34declare i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32>)35declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16>)36declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>)37declare i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32>)38declare i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16>)39declare i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8>)40declare i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16>)41declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8>)42declare i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16>)43declare i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8>)44 45define i16 @test_vaddlv_s8(<8 x i8> %a) {46; CHECK-LABEL: test_vaddlv_s8:47; CHECK: // %bb.0: // %entry48; CHECK-NEXT: saddlv h0, v0.8b49; CHECK-NEXT: fmov w0, s050; CHECK-NEXT: ret51entry:52 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %a)53 %0 = trunc i32 %saddlvv.i to i1654 ret i16 %055}56 57define i32 @test_vaddlv_s16(<4 x i16> %a) {58; CHECK-LABEL: test_vaddlv_s16:59; CHECK: // %bb.0: // %entry60; CHECK-NEXT: saddlv s0, v0.4h61; CHECK-NEXT: fmov w0, s062; CHECK-NEXT: ret63entry:64 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %a)65 ret i32 %saddlvv.i66}67 68define i16 @test_vaddlv_u8(<8 x i8> %a) {69; CHECK-LABEL: test_vaddlv_u8:70; CHECK: // %bb.0: // %entry71; CHECK-NEXT: uaddlv h0, v0.8b72; CHECK-NEXT: fmov w0, s073; CHECK-NEXT: ret74entry:75 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a)76 %0 = trunc i32 %uaddlvv.i to i1677 ret i16 %078}79 80define i32 @test_vaddlv_u16(<4 x i16> %a) {81; CHECK-LABEL: test_vaddlv_u16:82; CHECK: // %bb.0: // %entry83; CHECK-NEXT: uaddlv s0, v0.4h84; CHECK-NEXT: fmov w0, s085; CHECK-NEXT: ret86entry:87 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> %a)88 ret i32 %uaddlvv.i89}90 91define i16 @test_vaddlvq_s8(<16 x i8> %a) {92; CHECK-LABEL: test_vaddlvq_s8:93; CHECK: // %bb.0: // %entry94; CHECK-NEXT: saddlv h0, v0.16b95; CHECK-NEXT: fmov w0, s096; CHECK-NEXT: ret97entry:98 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8> %a)99 %0 = trunc i32 %saddlvv.i to i16100 ret i16 %0101}102 103define i32 @test_vaddlvq_s16(<8 x i16> %a) {104; CHECK-LABEL: test_vaddlvq_s16:105; CHECK: // %bb.0: // %entry106; CHECK-NEXT: saddlv s0, v0.8h107; CHECK-NEXT: fmov w0, s0108; CHECK-NEXT: ret109entry:110 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> %a)111 ret i32 %saddlvv.i112}113 114define i64 @test_vaddlvq_s32(<4 x i32> %a) {115; CHECK-LABEL: test_vaddlvq_s32:116; CHECK: // %bb.0: // %entry117; CHECK-NEXT: saddlv d0, v0.4s118; CHECK-NEXT: fmov x0, d0119; CHECK-NEXT: ret120entry:121 %saddlvv.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %a)122 ret i64 %saddlvv.i123}124 125define i16 @test_vaddlvq_u8(<16 x i8> %a) {126; CHECK-LABEL: test_vaddlvq_u8:127; CHECK: // %bb.0: // %entry128; CHECK-NEXT: uaddlv h0, v0.16b129; CHECK-NEXT: fmov w0, s0130; CHECK-NEXT: ret131entry:132 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> %a)133 %0 = trunc i32 %uaddlvv.i to i16134 ret i16 %0135}136 137define i32 @test_vaddlvq_u16(<8 x i16> %a) {138; CHECK-LABEL: test_vaddlvq_u16:139; CHECK: // %bb.0: // %entry140; CHECK-NEXT: uaddlv s0, v0.8h141; CHECK-NEXT: fmov w0, s0142; CHECK-NEXT: ret143entry:144 %uaddlvv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> %a)145 ret i32 %uaddlvv.i146}147 148define i64 @test_vaddlvq_u32(<4 x i32> %a) {149; CHECK-LABEL: test_vaddlvq_u32:150; CHECK: // %bb.0: // %entry151; CHECK-NEXT: uaddlv d0, v0.4s152; CHECK-NEXT: fmov x0, d0153; CHECK-NEXT: ret154entry:155 %uaddlvv.i = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> %a)156 ret i64 %uaddlvv.i157}158 159define i8 @test_vmaxv_s8(<8 x i8> %a) {160; CHECK-SD-LABEL: test_vmaxv_s8:161; CHECK-SD: // %bb.0: // %entry162; CHECK-SD-NEXT: smaxv b0, v0.8b163; CHECK-SD-NEXT: fmov w0, s0164; CHECK-SD-NEXT: ret165;166; CHECK-GI-LABEL: test_vmaxv_s8:167; CHECK-GI: // %bb.0: // %entry168; CHECK-GI-NEXT: smaxv b0, v0.8b169; CHECK-GI-NEXT: smov w0, v0.b[0]170; CHECK-GI-NEXT: ret171entry:172 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)173 %0 = trunc i32 %smaxv.i to i8174 ret i8 %0175}176 177define i16 @test_vmaxv_s16(<4 x i16> %a) {178; CHECK-SD-LABEL: test_vmaxv_s16:179; CHECK-SD: // %bb.0: // %entry180; CHECK-SD-NEXT: smaxv h0, v0.4h181; CHECK-SD-NEXT: fmov w0, s0182; CHECK-SD-NEXT: ret183;184; CHECK-GI-LABEL: test_vmaxv_s16:185; CHECK-GI: // %bb.0: // %entry186; CHECK-GI-NEXT: smaxv h0, v0.4h187; CHECK-GI-NEXT: smov w0, v0.h[0]188; CHECK-GI-NEXT: ret189entry:190 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)191 %0 = trunc i32 %smaxv.i to i16192 ret i16 %0193}194 195define i8 @test_vmaxv_u8(<8 x i8> %a) {196; CHECK-LABEL: test_vmaxv_u8:197; CHECK: // %bb.0: // %entry198; CHECK-NEXT: umaxv b0, v0.8b199; CHECK-NEXT: fmov w0, s0200; CHECK-NEXT: ret201entry:202 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)203 %0 = trunc i32 %umaxv.i to i8204 ret i8 %0205}206 207define i16 @test_vmaxv_u16(<4 x i16> %a) {208; CHECK-LABEL: test_vmaxv_u16:209; CHECK: // %bb.0: // %entry210; CHECK-NEXT: umaxv h0, v0.4h211; CHECK-NEXT: fmov w0, s0212; CHECK-NEXT: ret213entry:214 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a)215 %0 = trunc i32 %umaxv.i to i16216 ret i16 %0217}218 219define i8 @test_vmaxvq_s8(<16 x i8> %a) {220; CHECK-SD-LABEL: test_vmaxvq_s8:221; CHECK-SD: // %bb.0: // %entry222; CHECK-SD-NEXT: smaxv b0, v0.16b223; CHECK-SD-NEXT: fmov w0, s0224; CHECK-SD-NEXT: ret225;226; CHECK-GI-LABEL: test_vmaxvq_s8:227; CHECK-GI: // %bb.0: // %entry228; CHECK-GI-NEXT: smaxv b0, v0.16b229; CHECK-GI-NEXT: smov w0, v0.b[0]230; CHECK-GI-NEXT: ret231entry:232 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a)233 %0 = trunc i32 %smaxv.i to i8234 ret i8 %0235}236 237define i16 @test_vmaxvq_s16(<8 x i16> %a) {238; CHECK-SD-LABEL: test_vmaxvq_s16:239; CHECK-SD: // %bb.0: // %entry240; CHECK-SD-NEXT: smaxv h0, v0.8h241; CHECK-SD-NEXT: fmov w0, s0242; CHECK-SD-NEXT: ret243;244; CHECK-GI-LABEL: test_vmaxvq_s16:245; CHECK-GI: // %bb.0: // %entry246; CHECK-GI-NEXT: smaxv h0, v0.8h247; CHECK-GI-NEXT: smov w0, v0.h[0]248; CHECK-GI-NEXT: ret249entry:250 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a)251 %0 = trunc i32 %smaxv.i to i16252 ret i16 %0253}254 255define i32 @test_vmaxvq_s32(<4 x i32> %a) {256; CHECK-LABEL: test_vmaxvq_s32:257; CHECK: // %bb.0: // %entry258; CHECK-NEXT: smaxv s0, v0.4s259; CHECK-NEXT: fmov w0, s0260; CHECK-NEXT: ret261entry:262 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a)263 ret i32 %smaxv.i264}265 266define i8 @test_vmaxvq_u8(<16 x i8> %a) {267; CHECK-LABEL: test_vmaxvq_u8:268; CHECK: // %bb.0: // %entry269; CHECK-NEXT: umaxv b0, v0.16b270; CHECK-NEXT: fmov w0, s0271; CHECK-NEXT: ret272entry:273 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a)274 %0 = trunc i32 %umaxv.i to i8275 ret i8 %0276}277 278define i16 @test_vmaxvq_u16(<8 x i16> %a) {279; CHECK-LABEL: test_vmaxvq_u16:280; CHECK: // %bb.0: // %entry281; CHECK-NEXT: umaxv h0, v0.8h282; CHECK-NEXT: fmov w0, s0283; CHECK-NEXT: ret284entry:285 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a)286 %0 = trunc i32 %umaxv.i to i16287 ret i16 %0288}289 290define i32 @test_vmaxvq_u32(<4 x i32> %a) {291; CHECK-LABEL: test_vmaxvq_u32:292; CHECK: // %bb.0: // %entry293; CHECK-NEXT: umaxv s0, v0.4s294; CHECK-NEXT: fmov w0, s0295; CHECK-NEXT: ret296entry:297 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a)298 ret i32 %umaxv.i299}300 301define i8 @test_vminv_s8(<8 x i8> %a) {302; CHECK-SD-LABEL: test_vminv_s8:303; CHECK-SD: // %bb.0: // %entry304; CHECK-SD-NEXT: sminv b0, v0.8b305; CHECK-SD-NEXT: fmov w0, s0306; CHECK-SD-NEXT: ret307;308; CHECK-GI-LABEL: test_vminv_s8:309; CHECK-GI: // %bb.0: // %entry310; CHECK-GI-NEXT: sminv b0, v0.8b311; CHECK-GI-NEXT: smov w0, v0.b[0]312; CHECK-GI-NEXT: ret313entry:314 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a)315 %0 = trunc i32 %sminv.i to i8316 ret i8 %0317}318 319define i16 @test_vminv_s16(<4 x i16> %a) {320; CHECK-SD-LABEL: test_vminv_s16:321; CHECK-SD: // %bb.0: // %entry322; CHECK-SD-NEXT: sminv h0, v0.4h323; CHECK-SD-NEXT: fmov w0, s0324; CHECK-SD-NEXT: ret325;326; CHECK-GI-LABEL: test_vminv_s16:327; CHECK-GI: // %bb.0: // %entry328; CHECK-GI-NEXT: sminv h0, v0.4h329; CHECK-GI-NEXT: smov w0, v0.h[0]330; CHECK-GI-NEXT: ret331entry:332 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a)333 %0 = trunc i32 %sminv.i to i16334 ret i16 %0335}336 337define i8 @test_vminv_u8(<8 x i8> %a) {338; CHECK-LABEL: test_vminv_u8:339; CHECK: // %bb.0: // %entry340; CHECK-NEXT: uminv b0, v0.8b341; CHECK-NEXT: fmov w0, s0342; CHECK-NEXT: ret343entry:344 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a)345 %0 = trunc i32 %uminv.i to i8346 ret i8 %0347}348 349define i16 @test_vminv_u16(<4 x i16> %a) {350; CHECK-LABEL: test_vminv_u16:351; CHECK: // %bb.0: // %entry352; CHECK-NEXT: uminv h0, v0.4h353; CHECK-NEXT: fmov w0, s0354; CHECK-NEXT: ret355entry:356 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a)357 %0 = trunc i32 %uminv.i to i16358 ret i16 %0359}360 361define i8 @test_vminvq_s8(<16 x i8> %a) {362; CHECK-SD-LABEL: test_vminvq_s8:363; CHECK-SD: // %bb.0: // %entry364; CHECK-SD-NEXT: sminv b0, v0.16b365; CHECK-SD-NEXT: fmov w0, s0366; CHECK-SD-NEXT: ret367;368; CHECK-GI-LABEL: test_vminvq_s8:369; CHECK-GI: // %bb.0: // %entry370; CHECK-GI-NEXT: sminv b0, v0.16b371; CHECK-GI-NEXT: smov w0, v0.b[0]372; CHECK-GI-NEXT: ret373entry:374 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a)375 %0 = trunc i32 %sminv.i to i8376 ret i8 %0377}378 379define i16 @test_vminvq_s16(<8 x i16> %a) {380; CHECK-SD-LABEL: test_vminvq_s16:381; CHECK-SD: // %bb.0: // %entry382; CHECK-SD-NEXT: sminv h0, v0.8h383; CHECK-SD-NEXT: fmov w0, s0384; CHECK-SD-NEXT: ret385;386; CHECK-GI-LABEL: test_vminvq_s16:387; CHECK-GI: // %bb.0: // %entry388; CHECK-GI-NEXT: sminv h0, v0.8h389; CHECK-GI-NEXT: smov w0, v0.h[0]390; CHECK-GI-NEXT: ret391entry:392 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a)393 %0 = trunc i32 %sminv.i to i16394 ret i16 %0395}396 397define i32 @test_vminvq_s32(<4 x i32> %a) {398; CHECK-LABEL: test_vminvq_s32:399; CHECK: // %bb.0: // %entry400; CHECK-NEXT: sminv s0, v0.4s401; CHECK-NEXT: fmov w0, s0402; CHECK-NEXT: ret403entry:404 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a)405 ret i32 %sminv.i406}407 408define i8 @test_vminvq_u8(<16 x i8> %a) {409; CHECK-LABEL: test_vminvq_u8:410; CHECK: // %bb.0: // %entry411; CHECK-NEXT: uminv b0, v0.16b412; CHECK-NEXT: fmov w0, s0413; CHECK-NEXT: ret414entry:415 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a)416 %0 = trunc i32 %uminv.i to i8417 ret i8 %0418}419 420define i16 @test_vminvq_u16(<8 x i16> %a) {421; CHECK-LABEL: test_vminvq_u16:422; CHECK: // %bb.0: // %entry423; CHECK-NEXT: uminv h0, v0.8h424; CHECK-NEXT: fmov w0, s0425; CHECK-NEXT: ret426entry:427 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a)428 %0 = trunc i32 %uminv.i to i16429 ret i16 %0430}431 432define i32 @test_vminvq_u32(<4 x i32> %a) {433; CHECK-LABEL: test_vminvq_u32:434; CHECK: // %bb.0: // %entry435; CHECK-NEXT: uminv s0, v0.4s436; CHECK-NEXT: fmov w0, s0437; CHECK-NEXT: ret438entry:439 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a)440 ret i32 %uminv.i441}442 443define i8 @test_vaddv_s8(<8 x i8> %a) {444; CHECK-SD-LABEL: test_vaddv_s8:445; CHECK-SD: // %bb.0: // %entry446; CHECK-SD-NEXT: addv b0, v0.8b447; CHECK-SD-NEXT: fmov w0, s0448; CHECK-SD-NEXT: ret449;450; CHECK-GI-LABEL: test_vaddv_s8:451; CHECK-GI: // %bb.0: // %entry452; CHECK-GI-NEXT: addv b0, v0.8b453; CHECK-GI-NEXT: smov w0, v0.b[0]454; CHECK-GI-NEXT: ret455entry:456 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a)457 %0 = trunc i32 %vaddv.i to i8458 ret i8 %0459}460 461define i16 @test_vaddv_s16(<4 x i16> %a) {462; CHECK-SD-LABEL: test_vaddv_s16:463; CHECK-SD: // %bb.0: // %entry464; CHECK-SD-NEXT: addv h0, v0.4h465; CHECK-SD-NEXT: fmov w0, s0466; CHECK-SD-NEXT: ret467;468; CHECK-GI-LABEL: test_vaddv_s16:469; CHECK-GI: // %bb.0: // %entry470; CHECK-GI-NEXT: addv h0, v0.4h471; CHECK-GI-NEXT: smov w0, v0.h[0]472; CHECK-GI-NEXT: ret473entry:474 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a)475 %0 = trunc i32 %vaddv.i to i16476 ret i16 %0477}478 479define i8 @test_vaddv_u8(<8 x i8> %a) {480; CHECK-SD-LABEL: test_vaddv_u8:481; CHECK-SD: // %bb.0: // %entry482; CHECK-SD-NEXT: addv b0, v0.8b483; CHECK-SD-NEXT: fmov w0, s0484; CHECK-SD-NEXT: ret485;486; CHECK-GI-LABEL: test_vaddv_u8:487; CHECK-GI: // %bb.0: // %entry488; CHECK-GI-NEXT: addv b0, v0.8b489; CHECK-GI-NEXT: smov w0, v0.b[0]490; CHECK-GI-NEXT: ret491entry:492 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a)493 %0 = trunc i32 %vaddv.i to i8494 ret i8 %0495}496 497define i16 @test_vaddv_u16(<4 x i16> %a) {498; CHECK-SD-LABEL: test_vaddv_u16:499; CHECK-SD: // %bb.0: // %entry500; CHECK-SD-NEXT: addv h0, v0.4h501; CHECK-SD-NEXT: fmov w0, s0502; CHECK-SD-NEXT: ret503;504; CHECK-GI-LABEL: test_vaddv_u16:505; CHECK-GI: // %bb.0: // %entry506; CHECK-GI-NEXT: addv h0, v0.4h507; CHECK-GI-NEXT: smov w0, v0.h[0]508; CHECK-GI-NEXT: ret509entry:510 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a)511 %0 = trunc i32 %vaddv.i to i16512 ret i16 %0513}514 515define i8 @test_vaddvq_s8(<16 x i8> %a) {516; CHECK-SD-LABEL: test_vaddvq_s8:517; CHECK-SD: // %bb.0: // %entry518; CHECK-SD-NEXT: addv b0, v0.16b519; CHECK-SD-NEXT: fmov w0, s0520; CHECK-SD-NEXT: ret521;522; CHECK-GI-LABEL: test_vaddvq_s8:523; CHECK-GI: // %bb.0: // %entry524; CHECK-GI-NEXT: addv b0, v0.16b525; CHECK-GI-NEXT: smov w0, v0.b[0]526; CHECK-GI-NEXT: ret527entry:528 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a)529 %0 = trunc i32 %vaddv.i to i8530 ret i8 %0531}532 533define i16 @test_vaddvq_s16(<8 x i16> %a) {534; CHECK-SD-LABEL: test_vaddvq_s16:535; CHECK-SD: // %bb.0: // %entry536; CHECK-SD-NEXT: addv h0, v0.8h537; CHECK-SD-NEXT: fmov w0, s0538; CHECK-SD-NEXT: ret539;540; CHECK-GI-LABEL: test_vaddvq_s16:541; CHECK-GI: // %bb.0: // %entry542; CHECK-GI-NEXT: addv h0, v0.8h543; CHECK-GI-NEXT: smov w0, v0.h[0]544; CHECK-GI-NEXT: ret545entry:546 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a)547 %0 = trunc i32 %vaddv.i to i16548 ret i16 %0549}550 551define i32 @test_vaddvq_s32(<4 x i32> %a) {552; CHECK-LABEL: test_vaddvq_s32:553; CHECK: // %bb.0: // %entry554; CHECK-NEXT: addv s0, v0.4s555; CHECK-NEXT: fmov w0, s0556; CHECK-NEXT: ret557entry:558 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a)559 ret i32 %vaddv.i560}561 562define i8 @test_vaddvq_u8(<16 x i8> %a) {563; CHECK-SD-LABEL: test_vaddvq_u8:564; CHECK-SD: // %bb.0: // %entry565; CHECK-SD-NEXT: addv b0, v0.16b566; CHECK-SD-NEXT: fmov w0, s0567; CHECK-SD-NEXT: ret568;569; CHECK-GI-LABEL: test_vaddvq_u8:570; CHECK-GI: // %bb.0: // %entry571; CHECK-GI-NEXT: addv b0, v0.16b572; CHECK-GI-NEXT: smov w0, v0.b[0]573; CHECK-GI-NEXT: ret574entry:575 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a)576 %0 = trunc i32 %vaddv.i to i8577 ret i8 %0578}579 580define i16 @test_vaddvq_u16(<8 x i16> %a) {581; CHECK-SD-LABEL: test_vaddvq_u16:582; CHECK-SD: // %bb.0: // %entry583; CHECK-SD-NEXT: addv h0, v0.8h584; CHECK-SD-NEXT: fmov w0, s0585; CHECK-SD-NEXT: ret586;587; CHECK-GI-LABEL: test_vaddvq_u16:588; CHECK-GI: // %bb.0: // %entry589; CHECK-GI-NEXT: addv h0, v0.8h590; CHECK-GI-NEXT: smov w0, v0.h[0]591; CHECK-GI-NEXT: ret592entry:593 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a)594 %0 = trunc i32 %vaddv.i to i16595 ret i16 %0596}597 598define i32 @test_vaddvq_u32(<4 x i32> %a) {599; CHECK-LABEL: test_vaddvq_u32:600; CHECK: // %bb.0: // %entry601; CHECK-NEXT: addv s0, v0.4s602; CHECK-NEXT: fmov w0, s0603; CHECK-NEXT: ret604entry:605 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a)606 ret i32 %vaddv.i607}608 609define float @test_vmaxvq_f32(<4 x float> %a) {610; CHECK-LABEL: test_vmaxvq_f32:611; CHECK: // %bb.0: // %entry612; CHECK-NEXT: fmaxv s0, v0.4s613; CHECK-NEXT: ret614entry:615 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %a)616 ret float %0617}618 619define float @test_vminvq_f32(<4 x float> %a) {620; CHECK-LABEL: test_vminvq_f32:621; CHECK: // %bb.0: // %entry622; CHECK-NEXT: fminv s0, v0.4s623; CHECK-NEXT: ret624entry:625 %0 = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %a)626 ret float %0627}628 629define float @test_vmaxnmvq_f32(<4 x float> %a) {630; CHECK-LABEL: test_vmaxnmvq_f32:631; CHECK: // %bb.0: // %entry632; CHECK-NEXT: fmaxnmv s0, v0.4s633; CHECK-NEXT: ret634entry:635 %0 = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %a)636 ret float %0637}638 639define float @test_vminnmvq_f32(<4 x float> %a) {640; CHECK-LABEL: test_vminnmvq_f32:641; CHECK: // %bb.0: // %entry642; CHECK-NEXT: fminnmv s0, v0.4s643; CHECK-NEXT: ret644entry:645 %0 = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %a)646 ret float %0647}648 649