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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f646; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f327; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef8; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i329 10define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {11; CHECK-LABEL: ins16bw:12; CHECK: // %bb.0:13; CHECK-NEXT: mov v0.b[15], w014; CHECK-NEXT: ret15 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 1516 ret <16 x i8> %tmp317}18 19define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {20; CHECK-LABEL: ins8hw:21; CHECK: // %bb.0:22; CHECK-NEXT: mov v0.h[6], w023; CHECK-NEXT: ret24 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 625 ret <8 x i16> %tmp326}27 28define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {29; CHECK-LABEL: ins4sw:30; CHECK: // %bb.0:31; CHECK-NEXT: mov v0.s[2], w032; CHECK-NEXT: ret33 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 234 ret <4 x i32> %tmp335}36 37define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {38; CHECK-LABEL: ins2dw:39; CHECK: // %bb.0:40; CHECK-NEXT: mov v0.d[1], x041; CHECK-NEXT: ret42 %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 143 ret <2 x i64> %tmp344}45 46define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {47; CHECK-LABEL: ins8bw:48; CHECK: // %bb.0:49; CHECK-NEXT: // kill: def $d0 killed $d0 def $q050; CHECK-NEXT: mov v0.b[5], w051; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q052; CHECK-NEXT: ret53 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 554 ret <8 x i8> %tmp355}56 57define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {58; CHECK-LABEL: ins4hw:59; CHECK: // %bb.0:60; CHECK-NEXT: // kill: def $d0 killed $d0 def $q061; CHECK-NEXT: mov v0.h[3], w062; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q063; CHECK-NEXT: ret64 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 365 ret <4 x i16> %tmp366}67 68define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {69; CHECK-LABEL: ins2sw:70; CHECK: // %bb.0:71; CHECK-NEXT: // kill: def $d0 killed $d0 def $q072; CHECK-NEXT: mov v0.s[1], w073; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q074; CHECK-NEXT: ret75 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 176 ret <2 x i32> %tmp377}78 79define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {80; CHECK-LABEL: ins16b16:81; CHECK: // %bb.0:82; CHECK-NEXT: mov v1.b[15], v0.b[2]83; CHECK-NEXT: mov v0.16b, v1.16b84; CHECK-NEXT: ret85 %tmp3 = extractelement <16 x i8> %tmp1, i32 286 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 1587 ret <16 x i8> %tmp488}89 90define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {91; CHECK-LABEL: ins8h8:92; CHECK: // %bb.0:93; CHECK-NEXT: mov v1.h[7], v0.h[2]94; CHECK-NEXT: mov v0.16b, v1.16b95; CHECK-NEXT: ret96 %tmp3 = extractelement <8 x i16> %tmp1, i32 297 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 798 ret <8 x i16> %tmp499}100 101define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {102; CHECK-LABEL: ins4s4:103; CHECK: // %bb.0:104; CHECK-NEXT: mov v1.s[1], v0.s[2]105; CHECK-NEXT: mov v0.16b, v1.16b106; CHECK-NEXT: ret107 %tmp3 = extractelement <4 x i32> %tmp1, i32 2108 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1109 ret <4 x i32> %tmp4110}111 112define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {113; CHECK-LABEL: ins2d2:114; CHECK: // %bb.0:115; CHECK-NEXT: mov v1.d[1], v0.d[0]116; CHECK-NEXT: mov v0.16b, v1.16b117; CHECK-NEXT: ret118 %tmp3 = extractelement <2 x i64> %tmp1, i32 0119 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1120 ret <2 x i64> %tmp4121}122 123define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {124; CHECK-LABEL: ins4f4:125; CHECK: // %bb.0:126; CHECK-NEXT: mov v1.s[1], v0.s[2]127; CHECK-NEXT: mov v0.16b, v1.16b128; CHECK-NEXT: ret129 %tmp3 = extractelement <4 x float> %tmp1, i32 2130 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1131 ret <4 x float> %tmp4132}133 134define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {135; CHECK-LABEL: ins2df2:136; CHECK: // %bb.0:137; CHECK-NEXT: mov v1.d[1], v0.d[0]138; CHECK-NEXT: mov v0.16b, v1.16b139; CHECK-NEXT: ret140 %tmp3 = extractelement <2 x double> %tmp1, i32 0141 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1142 ret <2 x double> %tmp4143}144 145define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {146; CHECK-LABEL: ins8b16:147; CHECK: // %bb.0:148; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0149; CHECK-NEXT: mov v1.b[15], v0.b[2]150; CHECK-NEXT: mov v0.16b, v1.16b151; CHECK-NEXT: ret152 %tmp3 = extractelement <8 x i8> %tmp1, i32 2153 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15154 ret <16 x i8> %tmp4155}156 157define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {158; CHECK-LABEL: ins4h8:159; CHECK: // %bb.0:160; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0161; CHECK-NEXT: mov v1.h[7], v0.h[2]162; CHECK-NEXT: mov v0.16b, v1.16b163; CHECK-NEXT: ret164 %tmp3 = extractelement <4 x i16> %tmp1, i32 2165 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7166 ret <8 x i16> %tmp4167}168 169define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {170; CHECK-LABEL: ins2s4:171; CHECK: // %bb.0:172; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0173; CHECK-NEXT: mov v1.s[1], v0.s[1]174; CHECK-NEXT: mov v0.16b, v1.16b175; CHECK-NEXT: ret176 %tmp3 = extractelement <2 x i32> %tmp1, i32 1177 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1178 ret <4 x i32> %tmp4179}180 181define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {182; CHECK-LABEL: ins1d2:183; CHECK: // %bb.0:184; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0185; CHECK-NEXT: mov v1.d[1], v0.d[0]186; CHECK-NEXT: mov v0.16b, v1.16b187; CHECK-NEXT: ret188 %tmp3 = extractelement <1 x i64> %tmp1, i32 0189 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1190 ret <2 x i64> %tmp4191}192 193define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {194; CHECK-LABEL: ins2f4:195; CHECK: // %bb.0:196; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0197; CHECK-NEXT: mov v1.s[1], v0.s[1]198; CHECK-NEXT: mov v0.16b, v1.16b199; CHECK-NEXT: ret200 %tmp3 = extractelement <2 x float> %tmp1, i32 1201 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1202 ret <4 x float> %tmp4203}204 205define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {206; CHECK-LABEL: ins1f2:207; CHECK: // %bb.0:208; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0209; CHECK-NEXT: mov v1.d[1], v0.d[0]210; CHECK-NEXT: mov v0.16b, v1.16b211; CHECK-NEXT: ret212 %tmp3 = extractelement <1 x double> %tmp1, i32 0213 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1214 ret <2 x double> %tmp4215}216 217define <2 x double> @ins1f2_args_flipped(<2 x double> %tmp2, <1 x double> %tmp1) {218; CHECK-LABEL: ins1f2_args_flipped:219; CHECK: // %bb.0:220; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1221; CHECK-NEXT: mov v0.d[1], v1.d[0]222; CHECK-NEXT: ret223 %tmp3 = extractelement <1 x double> %tmp1, i32 0224 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1225 ret <2 x double> %tmp4226}227 228define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {229; CHECK-LABEL: ins16b8:230; CHECK: // %bb.0:231; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1232; CHECK-NEXT: mov v1.b[7], v0.b[2]233; CHECK-NEXT: fmov d0, d1234; CHECK-NEXT: ret235 %tmp3 = extractelement <16 x i8> %tmp1, i32 2236 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7237 ret <8 x i8> %tmp4238}239 240define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {241; CHECK-LABEL: ins8h4:242; CHECK: // %bb.0:243; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1244; CHECK-NEXT: mov v1.h[3], v0.h[2]245; CHECK-NEXT: fmov d0, d1246; CHECK-NEXT: ret247 %tmp3 = extractelement <8 x i16> %tmp1, i32 2248 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3249 ret <4 x i16> %tmp4250}251 252define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {253; CHECK-LABEL: ins4s2:254; CHECK: // %bb.0:255; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1256; CHECK-NEXT: mov v1.s[1], v0.s[2]257; CHECK-NEXT: fmov d0, d1258; CHECK-NEXT: ret259 %tmp3 = extractelement <4 x i32> %tmp1, i32 2260 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1261 ret <2 x i32> %tmp4262}263 264define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {265; CHECK-LABEL: ins2d1:266; CHECK: // %bb.0:267; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0268; CHECK-NEXT: ret269 %tmp3 = extractelement <2 x i64> %tmp1, i32 0270 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0271 ret <1 x i64> %tmp4272}273 274define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {275; CHECK-LABEL: ins4f2:276; CHECK: // %bb.0:277; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1278; CHECK-NEXT: mov v1.s[1], v0.s[2]279; CHECK-NEXT: fmov d0, d1280; CHECK-NEXT: ret281 %tmp3 = extractelement <4 x float> %tmp1, i32 2282 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1283 ret <2 x float> %tmp4284}285 286define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {287; CHECK-SD-LABEL: ins2f1:288; CHECK-SD: // %bb.0:289; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8290; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0291; CHECK-SD-NEXT: ret292;293; CHECK-GI-LABEL: ins2f1:294; CHECK-GI: // %bb.0:295; CHECK-GI-NEXT: mov d0, v0.d[1]296; CHECK-GI-NEXT: ret297 %tmp3 = extractelement <2 x double> %tmp1, i32 1298 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0299 ret <1 x double> %tmp4300}301 302define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {303; CHECK-LABEL: ins8b8:304; CHECK: // %bb.0:305; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1306; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0307; CHECK-NEXT: mov v1.b[4], v0.b[2]308; CHECK-NEXT: fmov d0, d1309; CHECK-NEXT: ret310 %tmp3 = extractelement <8 x i8> %tmp1, i32 2311 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4312 ret <8 x i8> %tmp4313}314 315define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {316; CHECK-LABEL: ins4h4:317; CHECK: // %bb.0:318; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1319; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0320; CHECK-NEXT: mov v1.h[3], v0.h[2]321; CHECK-NEXT: fmov d0, d1322; CHECK-NEXT: ret323 %tmp3 = extractelement <4 x i16> %tmp1, i32 2324 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3325 ret <4 x i16> %tmp4326}327 328define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {329; CHECK-LABEL: ins2s2:330; CHECK: // %bb.0:331; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1332; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0333; CHECK-NEXT: mov v1.s[1], v0.s[0]334; CHECK-NEXT: fmov d0, d1335; CHECK-NEXT: ret336 %tmp3 = extractelement <2 x i32> %tmp1, i32 0337 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1338 ret <2 x i32> %tmp4339}340 341define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {342; CHECK-LABEL: ins1d1:343; CHECK: // %bb.0:344; CHECK-NEXT: ret345 %tmp3 = extractelement <1 x i64> %tmp1, i32 0346 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0347 ret <1 x i64> %tmp4348}349 350define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {351; CHECK-LABEL: ins2f2:352; CHECK: // %bb.0:353; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1354; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0355; CHECK-NEXT: mov v1.s[1], v0.s[0]356; CHECK-NEXT: fmov d0, d1357; CHECK-NEXT: ret358 %tmp3 = extractelement <2 x float> %tmp1, i32 0359 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1360 ret <2 x float> %tmp4361}362 363define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {364; CHECK-LABEL: ins1df1:365; CHECK: // %bb.0:366; CHECK-NEXT: ret367 %tmp3 = extractelement <1 x double> %tmp1, i32 0368 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0369 ret <1 x double> %tmp4370}371 372define i32 @umovw16b(<16 x i8> %tmp1) {373; CHECK-LABEL: umovw16b:374; CHECK: // %bb.0:375; CHECK-NEXT: umov w0, v0.b[8]376; CHECK-NEXT: ret377 %tmp3 = extractelement <16 x i8> %tmp1, i32 8378 %tmp4 = zext i8 %tmp3 to i32379 ret i32 %tmp4380}381 382define i32 @umovw8h(<8 x i16> %tmp1) {383; CHECK-LABEL: umovw8h:384; CHECK: // %bb.0:385; CHECK-NEXT: umov w0, v0.h[2]386; CHECK-NEXT: ret387 %tmp3 = extractelement <8 x i16> %tmp1, i32 2388 %tmp4 = zext i16 %tmp3 to i32389 ret i32 %tmp4390}391 392define i32 @umovw4s(<4 x i32> %tmp1) {393; CHECK-SD-LABEL: umovw4s:394; CHECK-SD: // %bb.0:395; CHECK-SD-NEXT: mov w0, v0.s[2]396; CHECK-SD-NEXT: ret397;398; CHECK-GI-LABEL: umovw4s:399; CHECK-GI: // %bb.0:400; CHECK-GI-NEXT: mov s0, v0.s[2]401; CHECK-GI-NEXT: fmov w0, s0402; CHECK-GI-NEXT: ret403 %tmp3 = extractelement <4 x i32> %tmp1, i32 2404 ret i32 %tmp3405}406 407define i64 @umovx2d(<2 x i64> %tmp1) {408; CHECK-SD-LABEL: umovx2d:409; CHECK-SD: // %bb.0:410; CHECK-SD-NEXT: mov x0, v0.d[1]411; CHECK-SD-NEXT: ret412;413; CHECK-GI-LABEL: umovx2d:414; CHECK-GI: // %bb.0:415; CHECK-GI-NEXT: mov d0, v0.d[1]416; CHECK-GI-NEXT: fmov x0, d0417; CHECK-GI-NEXT: ret418 %tmp3 = extractelement <2 x i64> %tmp1, i32 1419 ret i64 %tmp3420}421 422define i32 @umovw8b(<8 x i8> %tmp1) {423; CHECK-LABEL: umovw8b:424; CHECK: // %bb.0:425; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0426; CHECK-NEXT: umov w0, v0.b[7]427; CHECK-NEXT: ret428 %tmp3 = extractelement <8 x i8> %tmp1, i32 7429 %tmp4 = zext i8 %tmp3 to i32430 ret i32 %tmp4431}432 433define i32 @umovw4h(<4 x i16> %tmp1) {434; CHECK-LABEL: umovw4h:435; CHECK: // %bb.0:436; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0437; CHECK-NEXT: umov w0, v0.h[2]438; CHECK-NEXT: ret439 %tmp3 = extractelement <4 x i16> %tmp1, i32 2440 %tmp4 = zext i16 %tmp3 to i32441 ret i32 %tmp4442}443 444define i32 @umovw2s(<2 x i32> %tmp1) {445; CHECK-SD-LABEL: umovw2s:446; CHECK-SD: // %bb.0:447; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0448; CHECK-SD-NEXT: mov w0, v0.s[1]449; CHECK-SD-NEXT: ret450;451; CHECK-GI-LABEL: umovw2s:452; CHECK-GI: // %bb.0:453; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0454; CHECK-GI-NEXT: mov s0, v0.s[1]455; CHECK-GI-NEXT: fmov w0, s0456; CHECK-GI-NEXT: ret457 %tmp3 = extractelement <2 x i32> %tmp1, i32 1458 ret i32 %tmp3459}460 461define i64 @umovx1d(<1 x i64> %tmp1) {462; CHECK-SD-LABEL: umovx1d:463; CHECK-SD: // %bb.0:464; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0465; CHECK-SD-NEXT: fmov x0, d0466; CHECK-SD-NEXT: ret467;468; CHECK-GI-LABEL: umovx1d:469; CHECK-GI: // %bb.0:470; CHECK-GI-NEXT: fmov x0, d0471; CHECK-GI-NEXT: ret472 %tmp3 = extractelement <1 x i64> %tmp1, i32 0473 ret i64 %tmp3474}475 476define i32 @smovw16b(<16 x i8> %tmp1) {477; CHECK-LABEL: smovw16b:478; CHECK: // %bb.0:479; CHECK-NEXT: smov w8, v0.b[8]480; CHECK-NEXT: add w0, w8, w8481; CHECK-NEXT: ret482 %tmp3 = extractelement <16 x i8> %tmp1, i32 8483 %tmp4 = sext i8 %tmp3 to i32484 %tmp5 = add i32 %tmp4, %tmp4485 ret i32 %tmp5486}487 488define i32 @smovw8h(<8 x i16> %tmp1) {489; CHECK-LABEL: smovw8h:490; CHECK: // %bb.0:491; CHECK-NEXT: smov w8, v0.h[2]492; CHECK-NEXT: add w0, w8, w8493; CHECK-NEXT: ret494 %tmp3 = extractelement <8 x i16> %tmp1, i32 2495 %tmp4 = sext i16 %tmp3 to i32496 %tmp5 = add i32 %tmp4, %tmp4497 ret i32 %tmp5498}499 500define i64 @smovx16b(<16 x i8> %tmp1) {501; CHECK-LABEL: smovx16b:502; CHECK: // %bb.0:503; CHECK-NEXT: smov x0, v0.b[8]504; CHECK-NEXT: ret505 %tmp3 = extractelement <16 x i8> %tmp1, i32 8506 %tmp4 = sext i8 %tmp3 to i64507 ret i64 %tmp4508}509 510define i64 @smovx8h(<8 x i16> %tmp1) {511; CHECK-LABEL: smovx8h:512; CHECK: // %bb.0:513; CHECK-NEXT: smov x0, v0.h[2]514; CHECK-NEXT: ret515 %tmp3 = extractelement <8 x i16> %tmp1, i32 2516 %tmp4 = sext i16 %tmp3 to i64517 ret i64 %tmp4518}519 520define i64 @smovx4s(<4 x i32> %tmp1) {521; CHECK-LABEL: smovx4s:522; CHECK: // %bb.0:523; CHECK-NEXT: smov x0, v0.s[2]524; CHECK-NEXT: ret525 %tmp3 = extractelement <4 x i32> %tmp1, i32 2526 %tmp4 = sext i32 %tmp3 to i64527 ret i64 %tmp4528}529 530define i32 @smovw8b(<8 x i8> %tmp1) {531; CHECK-LABEL: smovw8b:532; CHECK: // %bb.0:533; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0534; CHECK-NEXT: smov w8, v0.b[4]535; CHECK-NEXT: add w0, w8, w8536; CHECK-NEXT: ret537 %tmp3 = extractelement <8 x i8> %tmp1, i32 4538 %tmp4 = sext i8 %tmp3 to i32539 %tmp5 = add i32 %tmp4, %tmp4540 ret i32 %tmp5541}542 543define i32 @smovw4h(<4 x i16> %tmp1) {544; CHECK-LABEL: smovw4h:545; CHECK: // %bb.0:546; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0547; CHECK-NEXT: smov w8, v0.h[2]548; CHECK-NEXT: add w0, w8, w8549; CHECK-NEXT: ret550 %tmp3 = extractelement <4 x i16> %tmp1, i32 2551 %tmp4 = sext i16 %tmp3 to i32552 %tmp5 = add i32 %tmp4, %tmp4553 ret i32 %tmp5554}555 556define i32 @smovx8b(<8 x i8> %tmp1) {557; CHECK-LABEL: smovx8b:558; CHECK: // %bb.0:559; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0560; CHECK-NEXT: smov w0, v0.b[6]561; CHECK-NEXT: ret562 %tmp3 = extractelement <8 x i8> %tmp1, i32 6563 %tmp4 = sext i8 %tmp3 to i32564 ret i32 %tmp4565}566 567define i32 @smovx4h(<4 x i16> %tmp1) {568; CHECK-LABEL: smovx4h:569; CHECK: // %bb.0:570; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0571; CHECK-NEXT: smov w0, v0.h[2]572; CHECK-NEXT: ret573 %tmp3 = extractelement <4 x i16> %tmp1, i32 2574 %tmp4 = sext i16 %tmp3 to i32575 ret i32 %tmp4576}577 578define i64 @smovx2s(<2 x i32> %tmp1) {579; CHECK-LABEL: smovx2s:580; CHECK: // %bb.0:581; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0582; CHECK-NEXT: smov x0, v0.s[1]583; CHECK-NEXT: ret584 %tmp3 = extractelement <2 x i32> %tmp1, i32 1585 %tmp4 = sext i32 %tmp3 to i64586 ret i64 %tmp4587}588 589define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {590; CHECK-LABEL: test_vcopy_lane_s8:591; CHECK: // %bb.0:592; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0593; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1594; CHECK-NEXT: mov v0.b[5], v1.b[3]595; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0596; CHECK-NEXT: ret597 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>598 ret <8 x i8> %vset_lane599}600 601define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {602; CHECK-LABEL: test_vcopyq_laneq_s8:603; CHECK: // %bb.0:604; CHECK-NEXT: mov v0.b[14], v1.b[6]605; CHECK-NEXT: ret606 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15>607 ret <16 x i8> %vset_lane608}609 610define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {611; CHECK-LABEL: test_vcopy_lane_swap_s8:612; CHECK: // %bb.0:613; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1614; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0615; CHECK-NEXT: mov v1.b[7], v0.b[0]616; CHECK-NEXT: fmov d0, d1617; CHECK-NEXT: ret618 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>619 ret <8 x i8> %vset_lane620}621 622define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {623; CHECK-LABEL: test_vcopyq_laneq_swap_s8:624; CHECK: // %bb.0:625; CHECK-NEXT: mov v1.b[0], v0.b[15]626; CHECK-NEXT: mov v0.16b, v1.16b627; CHECK-NEXT: ret628 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>629 ret <16 x i8> %vset_lane630}631 632define <8 x i8> @test_vdup_n_u8(i8 %v1) #0 {633; CHECK-LABEL: test_vdup_n_u8:634; CHECK: // %bb.0:635; CHECK-NEXT: dup v0.8b, w0636; CHECK-NEXT: ret637 %vecinit.i = insertelement <8 x i8> undef, i8 %v1, i32 0638 %vecinit1.i = insertelement <8 x i8> %vecinit.i, i8 %v1, i32 1639 %vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 %v1, i32 2640 %vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 %v1, i32 3641 %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 %v1, i32 4642 %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 %v1, i32 5643 %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 %v1, i32 6644 %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 %v1, i32 7645 ret <8 x i8> %vecinit7.i646}647 648define <4 x i16> @test_vdup_n_u16(i16 %v1) #0 {649; CHECK-LABEL: test_vdup_n_u16:650; CHECK: // %bb.0:651; CHECK-NEXT: dup v0.4h, w0652; CHECK-NEXT: ret653 %vecinit.i = insertelement <4 x i16> undef, i16 %v1, i32 0654 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %v1, i32 1655 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %v1, i32 2656 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %v1, i32 3657 ret <4 x i16> %vecinit3.i658}659 660define <2 x i32> @test_vdup_n_u32(i32 %v1) #0 {661; CHECK-LABEL: test_vdup_n_u32:662; CHECK: // %bb.0:663; CHECK-NEXT: dup v0.2s, w0664; CHECK-NEXT: ret665 %vecinit.i = insertelement <2 x i32> undef, i32 %v1, i32 0666 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %v1, i32 1667 ret <2 x i32> %vecinit1.i668}669 670define <1 x i64> @test_vdup_n_u64(i64 %v1) #0 {671; CHECK-LABEL: test_vdup_n_u64:672; CHECK: // %bb.0:673; CHECK-NEXT: fmov d0, x0674; CHECK-NEXT: ret675 %vecinit.i = insertelement <1 x i64> undef, i64 %v1, i32 0676 ret <1 x i64> %vecinit.i677}678 679define <16 x i8> @test_vdupq_n_u8(i8 %v1) #0 {680; CHECK-LABEL: test_vdupq_n_u8:681; CHECK: // %bb.0:682; CHECK-NEXT: dup v0.16b, w0683; CHECK-NEXT: ret684 %vecinit.i = insertelement <16 x i8> undef, i8 %v1, i32 0685 %vecinit1.i = insertelement <16 x i8> %vecinit.i, i8 %v1, i32 1686 %vecinit2.i = insertelement <16 x i8> %vecinit1.i, i8 %v1, i32 2687 %vecinit3.i = insertelement <16 x i8> %vecinit2.i, i8 %v1, i32 3688 %vecinit4.i = insertelement <16 x i8> %vecinit3.i, i8 %v1, i32 4689 %vecinit5.i = insertelement <16 x i8> %vecinit4.i, i8 %v1, i32 5690 %vecinit6.i = insertelement <16 x i8> %vecinit5.i, i8 %v1, i32 6691 %vecinit7.i = insertelement <16 x i8> %vecinit6.i, i8 %v1, i32 7692 %vecinit8.i = insertelement <16 x i8> %vecinit7.i, i8 %v1, i32 8693 %vecinit9.i = insertelement <16 x i8> %vecinit8.i, i8 %v1, i32 9694 %vecinit10.i = insertelement <16 x i8> %vecinit9.i, i8 %v1, i32 10695 %vecinit11.i = insertelement <16 x i8> %vecinit10.i, i8 %v1, i32 11696 %vecinit12.i = insertelement <16 x i8> %vecinit11.i, i8 %v1, i32 12697 %vecinit13.i = insertelement <16 x i8> %vecinit12.i, i8 %v1, i32 13698 %vecinit14.i = insertelement <16 x i8> %vecinit13.i, i8 %v1, i32 14699 %vecinit15.i = insertelement <16 x i8> %vecinit14.i, i8 %v1, i32 15700 ret <16 x i8> %vecinit15.i701}702 703define <8 x i16> @test_vdupq_n_u16(i16 %v1) #0 {704; CHECK-LABEL: test_vdupq_n_u16:705; CHECK: // %bb.0:706; CHECK-NEXT: dup v0.8h, w0707; CHECK-NEXT: ret708 %vecinit.i = insertelement <8 x i16> undef, i16 %v1, i32 0709 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %v1, i32 1710 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %v1, i32 2711 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %v1, i32 3712 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %v1, i32 4713 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %v1, i32 5714 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %v1, i32 6715 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %v1, i32 7716 ret <8 x i16> %vecinit7.i717}718 719define <4 x i32> @test_vdupq_n_u32(i32 %v1) #0 {720; CHECK-LABEL: test_vdupq_n_u32:721; CHECK: // %bb.0:722; CHECK-NEXT: dup v0.4s, w0723; CHECK-NEXT: ret724 %vecinit.i = insertelement <4 x i32> undef, i32 %v1, i32 0725 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %v1, i32 1726 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %v1, i32 2727 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %v1, i32 3728 ret <4 x i32> %vecinit3.i729}730 731define <2 x i64> @test_vdupq_n_u64(i64 %v1) #0 {732; CHECK-LABEL: test_vdupq_n_u64:733; CHECK: // %bb.0:734; CHECK-NEXT: dup v0.2d, x0735; CHECK-NEXT: ret736 %vecinit.i = insertelement <2 x i64> undef, i64 %v1, i32 0737 %vecinit1.i = insertelement <2 x i64> %vecinit.i, i64 %v1, i32 1738 ret <2 x i64> %vecinit1.i739}740 741define <8 x i8> @test_vdup_lane_s8(<8 x i8> %v1) #0 {742; CHECK-LABEL: test_vdup_lane_s8:743; CHECK: // %bb.0:744; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0745; CHECK-NEXT: dup v0.8b, v0.b[5]746; CHECK-NEXT: ret747 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>748 ret <8 x i8> %shuffle749}750 751define <4 x i16> @test_vdup_lane_s16(<4 x i16> %v1) #0 {752; CHECK-LABEL: test_vdup_lane_s16:753; CHECK: // %bb.0:754; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0755; CHECK-NEXT: dup v0.4h, v0.h[2]756; CHECK-NEXT: ret757 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>758 ret <4 x i16> %shuffle759}760 761define <2 x i32> @test_vdup_lane_s32(<2 x i32> %v1) #0 {762; CHECK-LABEL: test_vdup_lane_s32:763; CHECK: // %bb.0:764; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0765; CHECK-NEXT: dup v0.2s, v0.s[1]766; CHECK-NEXT: ret767 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <2 x i32> <i32 1, i32 1>768 ret <2 x i32> %shuffle769}770 771define <16 x i8> @test_vdupq_lane_s8(<8 x i8> %v1) #0 {772; CHECK-LABEL: test_vdupq_lane_s8:773; CHECK: // %bb.0:774; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0775; CHECK-NEXT: dup v0.16b, v0.b[5]776; CHECK-NEXT: ret777 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>778 ret <16 x i8> %shuffle779}780 781define <8 x i16> @test_vdupq_lane_s16(<4 x i16> %v1) #0 {782; CHECK-LABEL: test_vdupq_lane_s16:783; CHECK: // %bb.0:784; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0785; CHECK-NEXT: dup v0.8h, v0.h[2]786; CHECK-NEXT: ret787 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>788 ret <8 x i16> %shuffle789}790 791define <4 x i32> @test_vdupq_lane_s32(<2 x i32> %v1) #0 {792; CHECK-LABEL: test_vdupq_lane_s32:793; CHECK: // %bb.0:794; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0795; CHECK-NEXT: dup v0.4s, v0.s[1]796; CHECK-NEXT: ret797 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>798 ret <4 x i32> %shuffle799}800 801define <2 x i64> @test_vdupq_lane_s64(<1 x i64> %v1) #0 {802; CHECK-LABEL: test_vdupq_lane_s64:803; CHECK: // %bb.0:804; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0805; CHECK-NEXT: dup v0.2d, v0.d[0]806; CHECK-NEXT: ret807 %shuffle = shufflevector <1 x i64> %v1, <1 x i64> undef, <2 x i32> zeroinitializer808 ret <2 x i64> %shuffle809}810 811define <8 x i8> @test_vdup_laneq_s8(<16 x i8> %v1) #0 {812; CHECK-LABEL: test_vdup_laneq_s8:813; CHECK: // %bb.0:814; CHECK-NEXT: dup v0.8b, v0.b[5]815; CHECK-NEXT: ret816 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>817 ret <8 x i8> %shuffle818}819 820define <4 x i16> @test_vdup_laneq_s16(<8 x i16> %v1) #0 {821; CHECK-LABEL: test_vdup_laneq_s16:822; CHECK: // %bb.0:823; CHECK-NEXT: dup v0.4h, v0.h[2]824; CHECK-NEXT: ret825 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>826 ret <4 x i16> %shuffle827}828 829define <2 x i32> @test_vdup_laneq_s32(<4 x i32> %v1) #0 {830; CHECK-LABEL: test_vdup_laneq_s32:831; CHECK: // %bb.0:832; CHECK-NEXT: dup v0.2s, v0.s[1]833; CHECK-NEXT: ret834 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 1, i32 1>835 ret <2 x i32> %shuffle836}837 838define <16 x i8> @test_vdupq_laneq_s8(<16 x i8> %v1) #0 {839; CHECK-LABEL: test_vdupq_laneq_s8:840; CHECK: // %bb.0:841; CHECK-NEXT: dup v0.16b, v0.b[5]842; CHECK-NEXT: ret843 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>844 ret <16 x i8> %shuffle845}846 847define <8 x i16> @test_vdupq_laneq_s16(<8 x i16> %v1) #0 {848; CHECK-LABEL: test_vdupq_laneq_s16:849; CHECK: // %bb.0:850; CHECK-NEXT: dup v0.8h, v0.h[2]851; CHECK-NEXT: ret852 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>853 ret <8 x i16> %shuffle854}855 856define <4 x i32> @test_vdupq_laneq_s32(<4 x i32> %v1) #0 {857; CHECK-LABEL: test_vdupq_laneq_s32:858; CHECK: // %bb.0:859; CHECK-NEXT: dup v0.4s, v0.s[1]860; CHECK-NEXT: ret861 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>862 ret <4 x i32> %shuffle863}864 865define <2 x i64> @test_vdupq_laneq_s64(<2 x i64> %v1) #0 {866; CHECK-LABEL: test_vdupq_laneq_s64:867; CHECK: // %bb.0:868; CHECK-NEXT: dup v0.2d, v0.d[0]869; CHECK-NEXT: ret870 %shuffle = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer871 ret <2 x i64> %shuffle872}873 874define i64 @test_bitcastv8i8toi64(<8 x i8> %in) {875; CHECK-LABEL: test_bitcastv8i8toi64:876; CHECK: // %bb.0:877; CHECK-NEXT: fmov x0, d0878; CHECK-NEXT: ret879 %res = bitcast <8 x i8> %in to i64880 ret i64 %res881}882 883define i64 @test_bitcastv4i16toi64(<4 x i16> %in) {884; CHECK-LABEL: test_bitcastv4i16toi64:885; CHECK: // %bb.0:886; CHECK-NEXT: fmov x0, d0887; CHECK-NEXT: ret888 %res = bitcast <4 x i16> %in to i64889 ret i64 %res890}891 892define i64 @test_bitcastv2i32toi64(<2 x i32> %in) {893; CHECK-LABEL: test_bitcastv2i32toi64:894; CHECK: // %bb.0:895; CHECK-NEXT: fmov x0, d0896; CHECK-NEXT: ret897 %res = bitcast <2 x i32> %in to i64898 ret i64 %res899}900 901define i64 @test_bitcastv2f32toi64(<2 x float> %in) {902; CHECK-LABEL: test_bitcastv2f32toi64:903; CHECK: // %bb.0:904; CHECK-NEXT: fmov x0, d0905; CHECK-NEXT: ret906 %res = bitcast <2 x float> %in to i64907 ret i64 %res908}909 910define i64 @test_bitcastv1i64toi64(<1 x i64> %in) {911; CHECK-LABEL: test_bitcastv1i64toi64:912; CHECK: // %bb.0:913; CHECK-NEXT: fmov x0, d0914; CHECK-NEXT: ret915 %res = bitcast <1 x i64> %in to i64916 ret i64 %res917}918 919define i64 @test_bitcastv1f64toi64(<1 x double> %in) {920; CHECK-LABEL: test_bitcastv1f64toi64:921; CHECK: // %bb.0:922; CHECK-NEXT: fmov x0, d0923; CHECK-NEXT: ret924 %res = bitcast <1 x double> %in to i64925 ret i64 %res926}927 928define <8 x i8> @test_bitcasti64tov8i8(i64 %in) {929; CHECK-LABEL: test_bitcasti64tov8i8:930; CHECK: // %bb.0:931; CHECK-NEXT: fmov d0, x0932; CHECK-NEXT: ret933 %res = bitcast i64 %in to <8 x i8>934 ret <8 x i8> %res935}936 937define <4 x i16> @test_bitcasti64tov4i16(i64 %in) {938; CHECK-LABEL: test_bitcasti64tov4i16:939; CHECK: // %bb.0:940; CHECK-NEXT: fmov d0, x0941; CHECK-NEXT: ret942 %res = bitcast i64 %in to <4 x i16>943 ret <4 x i16> %res944}945 946define <2 x i32> @test_bitcasti64tov2i32(i64 %in) {947; CHECK-LABEL: test_bitcasti64tov2i32:948; CHECK: // %bb.0:949; CHECK-NEXT: fmov d0, x0950; CHECK-NEXT: ret951 %res = bitcast i64 %in to <2 x i32>952 ret <2 x i32> %res953}954 955define <2 x float> @test_bitcasti64tov2f32(i64 %in) {956; CHECK-LABEL: test_bitcasti64tov2f32:957; CHECK: // %bb.0:958; CHECK-NEXT: fmov d0, x0959; CHECK-NEXT: ret960 %res = bitcast i64 %in to <2 x float>961 ret <2 x float> %res962}963 964define <1 x i64> @test_bitcasti64tov1i64(i64 %in) {965; CHECK-LABEL: test_bitcasti64tov1i64:966; CHECK: // %bb.0:967; CHECK-NEXT: fmov d0, x0968; CHECK-NEXT: ret969 %res = bitcast i64 %in to <1 x i64>970 ret <1 x i64> %res971}972 973define <1 x double> @test_bitcasti64tov1f64(i64 %in) {974; CHECK-LABEL: test_bitcasti64tov1f64:975; CHECK: // %bb.0:976; CHECK-NEXT: fmov d0, x0977; CHECK-NEXT: ret978 %res = bitcast i64 %in to <1 x double>979 ret <1 x double> %res980}981 982define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {983; CHECK-SD-LABEL: test_bitcastv8i8tov1f64:984; CHECK-SD: // %bb.0:985; CHECK-SD-NEXT: neg v0.8b, v0.8b986; CHECK-SD-NEXT: fcvtzs x8, d0987; CHECK-SD-NEXT: fmov d0, x8988; CHECK-SD-NEXT: ret989;990; CHECK-GI-LABEL: test_bitcastv8i8tov1f64:991; CHECK-GI: // %bb.0:992; CHECK-GI-NEXT: neg v0.8b, v0.8b993; CHECK-GI-NEXT: fcvtzs d0, d0994; CHECK-GI-NEXT: ret995 %sub.i = sub <8 x i8> zeroinitializer, %a996 %1 = bitcast <8 x i8> %sub.i to <1 x double>997 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>998 ret <1 x i64> %vcvt.i999}1000 1001define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {1002; CHECK-SD-LABEL: test_bitcastv4i16tov1f64:1003; CHECK-SD: // %bb.0:1004; CHECK-SD-NEXT: neg v0.4h, v0.4h1005; CHECK-SD-NEXT: fcvtzs x8, d01006; CHECK-SD-NEXT: fmov d0, x81007; CHECK-SD-NEXT: ret1008;1009; CHECK-GI-LABEL: test_bitcastv4i16tov1f64:1010; CHECK-GI: // %bb.0:1011; CHECK-GI-NEXT: neg v0.4h, v0.4h1012; CHECK-GI-NEXT: fcvtzs d0, d01013; CHECK-GI-NEXT: ret1014 %sub.i = sub <4 x i16> zeroinitializer, %a1015 %1 = bitcast <4 x i16> %sub.i to <1 x double>1016 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1017 ret <1 x i64> %vcvt.i1018}1019 1020define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 {1021; CHECK-SD-LABEL: test_bitcastv2i32tov1f64:1022; CHECK-SD: // %bb.0:1023; CHECK-SD-NEXT: neg v0.2s, v0.2s1024; CHECK-SD-NEXT: fcvtzs x8, d01025; CHECK-SD-NEXT: fmov d0, x81026; CHECK-SD-NEXT: ret1027;1028; CHECK-GI-LABEL: test_bitcastv2i32tov1f64:1029; CHECK-GI: // %bb.0:1030; CHECK-GI-NEXT: neg v0.2s, v0.2s1031; CHECK-GI-NEXT: fcvtzs d0, d01032; CHECK-GI-NEXT: ret1033 %sub.i = sub <2 x i32> zeroinitializer, %a1034 %1 = bitcast <2 x i32> %sub.i to <1 x double>1035 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1036 ret <1 x i64> %vcvt.i1037}1038 1039define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 {1040; CHECK-SD-LABEL: test_bitcastv1i64tov1f64:1041; CHECK-SD: // %bb.0:1042; CHECK-SD-NEXT: neg d0, d01043; CHECK-SD-NEXT: fcvtzs x8, d01044; CHECK-SD-NEXT: fmov d0, x81045; CHECK-SD-NEXT: ret1046;1047; CHECK-GI-LABEL: test_bitcastv1i64tov1f64:1048; CHECK-GI: // %bb.0:1049; CHECK-GI-NEXT: fmov x8, d01050; CHECK-GI-NEXT: neg x8, x81051; CHECK-GI-NEXT: fmov d0, x81052; CHECK-GI-NEXT: fcvtzs d0, d01053; CHECK-GI-NEXT: ret1054 %sub.i = sub <1 x i64> zeroinitializer, %a1055 %1 = bitcast <1 x i64> %sub.i to <1 x double>1056 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1057 ret <1 x i64> %vcvt.i1058}1059 1060define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 {1061; CHECK-LABEL: test_bitcastv2f32tov1f64:1062; CHECK: // %bb.0:1063; CHECK-NEXT: fneg v0.2s, v0.2s1064; CHECK-NEXT: fcvtzs x8, d01065; CHECK-NEXT: fmov d0, x81066; CHECK-NEXT: ret1067 %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a1068 %1 = bitcast <2 x float> %sub.i to <1 x double>1069 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1070 ret <1 x i64> %vcvt.i1071}1072 1073define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 {1074; CHECK-SD-LABEL: test_bitcastv1f64tov8i8:1075; CHECK-SD: // %bb.0:1076; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01077; CHECK-SD-NEXT: scvtf d0, d01078; CHECK-SD-NEXT: neg v0.8b, v0.8b1079; CHECK-SD-NEXT: ret1080;1081; CHECK-GI-LABEL: test_bitcastv1f64tov8i8:1082; CHECK-GI: // %bb.0:1083; CHECK-GI-NEXT: scvtf d0, d01084; CHECK-GI-NEXT: neg v0.8b, v0.8b1085; CHECK-GI-NEXT: ret1086 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1087 %1 = bitcast <1 x double> %vcvt.i to <8 x i8>1088 %sub.i = sub <8 x i8> zeroinitializer, %11089 ret <8 x i8> %sub.i1090}1091 1092define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 {1093; CHECK-SD-LABEL: test_bitcastv1f64tov4i16:1094; CHECK-SD: // %bb.0:1095; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01096; CHECK-SD-NEXT: scvtf d0, d01097; CHECK-SD-NEXT: neg v0.4h, v0.4h1098; CHECK-SD-NEXT: ret1099;1100; CHECK-GI-LABEL: test_bitcastv1f64tov4i16:1101; CHECK-GI: // %bb.0:1102; CHECK-GI-NEXT: scvtf d0, d01103; CHECK-GI-NEXT: neg v0.4h, v0.4h1104; CHECK-GI-NEXT: ret1105 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1106 %1 = bitcast <1 x double> %vcvt.i to <4 x i16>1107 %sub.i = sub <4 x i16> zeroinitializer, %11108 ret <4 x i16> %sub.i1109}1110 1111define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 {1112; CHECK-SD-LABEL: test_bitcastv1f64tov2i32:1113; CHECK-SD: // %bb.0:1114; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01115; CHECK-SD-NEXT: scvtf d0, d01116; CHECK-SD-NEXT: neg v0.2s, v0.2s1117; CHECK-SD-NEXT: ret1118;1119; CHECK-GI-LABEL: test_bitcastv1f64tov2i32:1120; CHECK-GI: // %bb.0:1121; CHECK-GI-NEXT: scvtf d0, d01122; CHECK-GI-NEXT: neg v0.2s, v0.2s1123; CHECK-GI-NEXT: ret1124 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1125 %1 = bitcast <1 x double> %vcvt.i to <2 x i32>1126 %sub.i = sub <2 x i32> zeroinitializer, %11127 ret <2 x i32> %sub.i1128}1129 1130define <1 x i64> @test_bitcastv1f64tov1i64(<1 x i64> %a) #0 {1131; CHECK-SD-LABEL: test_bitcastv1f64tov1i64:1132; CHECK-SD: // %bb.0:1133; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01134; CHECK-SD-NEXT: scvtf d0, d01135; CHECK-SD-NEXT: neg d0, d01136; CHECK-SD-NEXT: ret1137;1138; CHECK-GI-LABEL: test_bitcastv1f64tov1i64:1139; CHECK-GI: // %bb.0:1140; CHECK-GI-NEXT: scvtf d0, d01141; CHECK-GI-NEXT: fmov x8, d01142; CHECK-GI-NEXT: neg x8, x81143; CHECK-GI-NEXT: fmov d0, x81144; CHECK-GI-NEXT: ret1145 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1146 %1 = bitcast <1 x double> %vcvt.i to <1 x i64>1147 %sub.i = sub <1 x i64> zeroinitializer, %11148 ret <1 x i64> %sub.i1149}1150 1151define <2 x float> @test_bitcastv1f64tov2f32(<1 x i64> %a) #0 {1152; CHECK-LABEL: test_bitcastv1f64tov2f32:1153; CHECK: // %bb.0:1154; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01155; CHECK-NEXT: scvtf d0, d01156; CHECK-NEXT: fneg v0.2s, v0.2s1157; CHECK-NEXT: ret1158 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1159 %1 = bitcast <1 x double> %vcvt.i to <2 x float>1160 %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %11161 ret <2 x float> %sub.i1162}1163 1164; Test insert element into an undef vector1165define <8 x i8> @scalar_to_vector.v8i8(i8 %a) {1166; CHECK-LABEL: scalar_to_vector.v8i8:1167; CHECK: // %bb.0:1168; CHECK-NEXT: fmov s0, w01169; CHECK-NEXT: ret1170 %b = insertelement <8 x i8> undef, i8 %a, i32 01171 ret <8 x i8> %b1172}1173 1174define <16 x i8> @scalar_to_vector.v16i8(i8 %a) {1175; CHECK-LABEL: scalar_to_vector.v16i8:1176; CHECK: // %bb.0:1177; CHECK-NEXT: fmov s0, w01178; CHECK-NEXT: ret1179 %b = insertelement <16 x i8> undef, i8 %a, i32 01180 ret <16 x i8> %b1181}1182 1183define <4 x i16> @scalar_to_vector.v4i16(i16 %a) {1184; CHECK-LABEL: scalar_to_vector.v4i16:1185; CHECK: // %bb.0:1186; CHECK-NEXT: fmov s0, w01187; CHECK-NEXT: ret1188 %b = insertelement <4 x i16> undef, i16 %a, i32 01189 ret <4 x i16> %b1190}1191 1192define <8 x i16> @scalar_to_vector.v8i16(i16 %a) {1193; CHECK-LABEL: scalar_to_vector.v8i16:1194; CHECK: // %bb.0:1195; CHECK-NEXT: fmov s0, w01196; CHECK-NEXT: ret1197 %b = insertelement <8 x i16> undef, i16 %a, i32 01198 ret <8 x i16> %b1199}1200 1201define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {1202; CHECK-LABEL: scalar_to_vector.v2i32:1203; CHECK: // %bb.0:1204; CHECK-NEXT: fmov s0, w01205; CHECK-NEXT: ret1206 %b = insertelement <2 x i32> undef, i32 %a, i32 01207 ret <2 x i32> %b1208}1209 1210define <4 x i32> @scalar_to_vector.v4i32(i32 %a) {1211; CHECK-LABEL: scalar_to_vector.v4i32:1212; CHECK: // %bb.0:1213; CHECK-NEXT: fmov s0, w01214; CHECK-NEXT: ret1215 %b = insertelement <4 x i32> undef, i32 %a, i32 01216 ret <4 x i32> %b1217}1218 1219define <2 x i64> @scalar_to_vector.v2i64(i64 %a) {1220; CHECK-LABEL: scalar_to_vector.v2i64:1221; CHECK: // %bb.0:1222; CHECK-NEXT: fmov d0, x01223; CHECK-NEXT: ret1224 %b = insertelement <2 x i64> undef, i64 %a, i32 01225 ret <2 x i64> %b1226}1227 1228define <8 x i8> @testDUP.v1i8(<1 x i8> %a) {1229; CHECK-SD-LABEL: testDUP.v1i8:1230; CHECK-SD: // %bb.0:1231; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01232; CHECK-SD-NEXT: dup v0.8b, v0.b[0]1233; CHECK-SD-NEXT: ret1234;1235; CHECK-GI-LABEL: testDUP.v1i8:1236; CHECK-GI: // %bb.0:1237; CHECK-GI-NEXT: fmov w8, s01238; CHECK-GI-NEXT: dup v0.8b, w81239; CHECK-GI-NEXT: ret1240 %b = extractelement <1 x i8> %a, i32 01241 %c = insertelement <8 x i8> undef, i8 %b, i32 01242 %d = insertelement <8 x i8> %c, i8 %b, i32 11243 %e = insertelement <8 x i8> %d, i8 %b, i32 21244 %f = insertelement <8 x i8> %e, i8 %b, i32 31245 %g = insertelement <8 x i8> %f, i8 %b, i32 41246 %h = insertelement <8 x i8> %g, i8 %b, i32 51247 %i = insertelement <8 x i8> %h, i8 %b, i32 61248 %j = insertelement <8 x i8> %i, i8 %b, i32 71249 ret <8 x i8> %j1250}1251 1252define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {1253; CHECK-LABEL: testDUP.v1i16:1254; CHECK: // %bb.0:1255; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01256; CHECK-NEXT: dup v0.8h, v0.h[0]1257; CHECK-NEXT: ret1258 %b = extractelement <1 x i16> %a, i32 01259 %c = insertelement <8 x i16> undef, i16 %b, i32 01260 %d = insertelement <8 x i16> %c, i16 %b, i32 11261 %e = insertelement <8 x i16> %d, i16 %b, i32 21262 %f = insertelement <8 x i16> %e, i16 %b, i32 31263 %g = insertelement <8 x i16> %f, i16 %b, i32 41264 %h = insertelement <8 x i16> %g, i16 %b, i32 51265 %i = insertelement <8 x i16> %h, i16 %b, i32 61266 %j = insertelement <8 x i16> %i, i16 %b, i32 71267 ret <8 x i16> %j1268}1269 1270define <4 x i32> @testDUP.v1i32(<1 x i32> %a) {1271; CHECK-LABEL: testDUP.v1i32:1272; CHECK: // %bb.0:1273; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01274; CHECK-NEXT: dup v0.4s, v0.s[0]1275; CHECK-NEXT: ret1276 %b = extractelement <1 x i32> %a, i32 01277 %c = insertelement <4 x i32> undef, i32 %b, i32 01278 %d = insertelement <4 x i32> %c, i32 %b, i32 11279 %e = insertelement <4 x i32> %d, i32 %b, i32 21280 %f = insertelement <4 x i32> %e, i32 %b, i32 31281 ret <4 x i32> %f1282}1283 1284define <8 x i8> @getl(<16 x i8> %x) #0 {1285; CHECK-SD-LABEL: getl:1286; CHECK-SD: // %bb.0:1287; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q01288; CHECK-SD-NEXT: ret1289;1290; CHECK-GI-LABEL: getl:1291; CHECK-GI: // %bb.0:1292; CHECK-GI-NEXT: mov v1.b[0], v0.b[0]1293; CHECK-GI-NEXT: mov v1.b[1], v0.b[1]1294; CHECK-GI-NEXT: mov v1.b[2], v0.b[2]1295; CHECK-GI-NEXT: mov v1.b[3], v0.b[3]1296; CHECK-GI-NEXT: mov v1.b[4], v0.b[4]1297; CHECK-GI-NEXT: mov v1.b[5], v0.b[5]1298; CHECK-GI-NEXT: mov v1.b[6], v0.b[6]1299; CHECK-GI-NEXT: mov v1.b[7], v0.b[7]1300; CHECK-GI-NEXT: fmov d0, d11301; CHECK-GI-NEXT: ret1302 %vecext = extractelement <16 x i8> %x, i32 01303 %vecinit = insertelement <8 x i8> undef, i8 %vecext, i32 01304 %vecext1 = extractelement <16 x i8> %x, i32 11305 %vecinit2 = insertelement <8 x i8> %vecinit, i8 %vecext1, i32 11306 %vecext3 = extractelement <16 x i8> %x, i32 21307 %vecinit4 = insertelement <8 x i8> %vecinit2, i8 %vecext3, i32 21308 %vecext5 = extractelement <16 x i8> %x, i32 31309 %vecinit6 = insertelement <8 x i8> %vecinit4, i8 %vecext5, i32 31310 %vecext7 = extractelement <16 x i8> %x, i32 41311 %vecinit8 = insertelement <8 x i8> %vecinit6, i8 %vecext7, i32 41312 %vecext9 = extractelement <16 x i8> %x, i32 51313 %vecinit10 = insertelement <8 x i8> %vecinit8, i8 %vecext9, i32 51314 %vecext11 = extractelement <16 x i8> %x, i32 61315 %vecinit12 = insertelement <8 x i8> %vecinit10, i8 %vecext11, i32 61316 %vecext13 = extractelement <16 x i8> %x, i32 71317 %vecinit14 = insertelement <8 x i8> %vecinit12, i8 %vecext13, i32 71318 ret <8 x i8> %vecinit141319}1320 1321define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {1322; CHECK-SD-LABEL: test_extracts_inserts_varidx_extract:1323; CHECK-SD: // %bb.0:1324; CHECK-SD-NEXT: sub sp, sp, #161325; CHECK-SD-NEXT: .cfi_def_cfa_offset 161326; CHECK-SD-NEXT: mov x8, sp1327; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x01328; CHECK-SD-NEXT: str q0, [sp]1329; CHECK-SD-NEXT: bfi x8, x0, #1, #31330; CHECK-SD-NEXT: ldr h1, [x8]1331; CHECK-SD-NEXT: mov v1.h[1], v0.h[1]1332; CHECK-SD-NEXT: mov v1.h[2], v0.h[2]1333; CHECK-SD-NEXT: mov v1.h[3], v0.h[3]1334; CHECK-SD-NEXT: fmov d0, d11335; CHECK-SD-NEXT: add sp, sp, #161336; CHECK-SD-NEXT: ret1337;1338; CHECK-GI-LABEL: test_extracts_inserts_varidx_extract:1339; CHECK-GI: // %bb.0:1340; CHECK-GI-NEXT: sub sp, sp, #161341; CHECK-GI-NEXT: .cfi_def_cfa_offset 161342; CHECK-GI-NEXT: mov w9, w01343; CHECK-GI-NEXT: mov x8, sp1344; CHECK-GI-NEXT: str q0, [sp]1345; CHECK-GI-NEXT: and x9, x9, #0x71346; CHECK-GI-NEXT: ldr h1, [x8, x9, lsl #1]1347; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]1348; CHECK-GI-NEXT: mov v1.h[2], v0.h[2]1349; CHECK-GI-NEXT: mov v1.h[3], v0.h[3]1350; CHECK-GI-NEXT: fmov d0, d11351; CHECK-GI-NEXT: add sp, sp, #161352; CHECK-GI-NEXT: ret1353 %tmp = extractelement <8 x i16> %x, i32 %idx1354 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 01355 %tmp3 = extractelement <8 x i16> %x, i32 11356 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 11357 %tmp5 = extractelement <8 x i16> %x, i32 21358 %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 21359 %tmp7 = extractelement <8 x i16> %x, i32 31360 %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 31361 ret <4 x i16> %tmp81362}1363 1364define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {1365; CHECK-SD-LABEL: test_extracts_inserts_varidx_insert:1366; CHECK-SD: // %bb.0:1367; CHECK-SD-NEXT: sub sp, sp, #161368; CHECK-SD-NEXT: .cfi_def_cfa_offset 161369; CHECK-SD-NEXT: add x8, sp, #81370; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x01371; CHECK-SD-NEXT: bfi x8, x0, #1, #21372; CHECK-SD-NEXT: str h0, [x8]1373; CHECK-SD-NEXT: ldr d1, [sp, #8]1374; CHECK-SD-NEXT: mov v1.h[1], v0.h[1]1375; CHECK-SD-NEXT: mov v1.h[2], v0.h[2]1376; CHECK-SD-NEXT: mov v1.h[3], v0.h[3]1377; CHECK-SD-NEXT: fmov d0, d11378; CHECK-SD-NEXT: add sp, sp, #161379; CHECK-SD-NEXT: ret1380;1381; CHECK-GI-LABEL: test_extracts_inserts_varidx_insert:1382; CHECK-GI: // %bb.0:1383; CHECK-GI-NEXT: sub sp, sp, #161384; CHECK-GI-NEXT: .cfi_def_cfa_offset 161385; CHECK-GI-NEXT: mov w8, w01386; CHECK-GI-NEXT: add x9, sp, #81387; CHECK-GI-NEXT: str d0, [sp, #8]1388; CHECK-GI-NEXT: and x8, x8, #0x31389; CHECK-GI-NEXT: str h0, [x9, x8, lsl #1]1390; CHECK-GI-NEXT: ldr d1, [sp, #8]1391; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]1392; CHECK-GI-NEXT: mov v1.h[2], v0.h[2]1393; CHECK-GI-NEXT: mov v1.h[3], v0.h[3]1394; CHECK-GI-NEXT: fmov d0, d11395; CHECK-GI-NEXT: add sp, sp, #161396; CHECK-GI-NEXT: ret1397 %tmp = extractelement <8 x i16> %x, i32 01398 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx1399 %tmp3 = extractelement <8 x i16> %x, i32 11400 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 11401 %tmp5 = extractelement <8 x i16> %x, i32 21402 %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 21403 %tmp7 = extractelement <8 x i16> %x, i32 31404 %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 31405 ret <4 x i16> %tmp81406}1407 1408define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) {1409; CHECK-SD-LABEL: test_dup_v2i32_v4i16:1410; CHECK-SD: // %bb.0: // %entry1411; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01412; CHECK-SD-NEXT: dup v0.4h, v0.h[2]1413; CHECK-SD-NEXT: ret1414;1415; CHECK-GI-LABEL: test_dup_v2i32_v4i16:1416; CHECK-GI: // %bb.0: // %entry1417; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01418; CHECK-GI-NEXT: mov w8, v0.s[1]1419; CHECK-GI-NEXT: dup v0.4h, w81420; CHECK-GI-NEXT: ret1421entry:1422 %x = extractelement <2 x i32> %a, i32 11423 %vget_lane = trunc i32 %x to i161424 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01425 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11426 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21427 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31428 ret <4 x i16> %vecinit3.i1429}1430 1431define <8 x i16> @test_dup_v4i32_v8i16(<4 x i32> %a) {1432; CHECK-SD-LABEL: test_dup_v4i32_v8i16:1433; CHECK-SD: // %bb.0: // %entry1434; CHECK-SD-NEXT: dup v0.8h, v0.h[6]1435; CHECK-SD-NEXT: ret1436;1437; CHECK-GI-LABEL: test_dup_v4i32_v8i16:1438; CHECK-GI: // %bb.0: // %entry1439; CHECK-GI-NEXT: mov w8, v0.s[3]1440; CHECK-GI-NEXT: dup v0.8h, w81441; CHECK-GI-NEXT: ret1442entry:1443 %x = extractelement <4 x i32> %a, i32 31444 %vget_lane = trunc i32 %x to i161445 %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 01446 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 11447 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 21448 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 31449 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 41450 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 51451 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 61452 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 71453 ret <8 x i16> %vecinit7.i1454}1455 1456define <4 x i16> @test_dup_v1i64_v4i16(<1 x i64> %a) {1457; CHECK-SD-LABEL: test_dup_v1i64_v4i16:1458; CHECK-SD: // %bb.0: // %entry1459; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01460; CHECK-SD-NEXT: dup v0.4h, v0.h[0]1461; CHECK-SD-NEXT: ret1462;1463; CHECK-GI-LABEL: test_dup_v1i64_v4i16:1464; CHECK-GI: // %bb.0: // %entry1465; CHECK-GI-NEXT: fmov x8, d01466; CHECK-GI-NEXT: dup v0.4h, w81467; CHECK-GI-NEXT: ret1468entry:1469 %x = extractelement <1 x i64> %a, i32 01470 %vget_lane = trunc i64 %x to i161471 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01472 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11473 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21474 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31475 ret <4 x i16> %vecinit3.i1476}1477 1478define <2 x i32> @test_dup_v1i64_v2i32(<1 x i64> %a) {1479; CHECK-SD-LABEL: test_dup_v1i64_v2i32:1480; CHECK-SD: // %bb.0: // %entry1481; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01482; CHECK-SD-NEXT: dup v0.2s, v0.s[0]1483; CHECK-SD-NEXT: ret1484;1485; CHECK-GI-LABEL: test_dup_v1i64_v2i32:1486; CHECK-GI: // %bb.0: // %entry1487; CHECK-GI-NEXT: fmov x8, d01488; CHECK-GI-NEXT: dup v0.2s, w81489; CHECK-GI-NEXT: ret1490entry:1491 %x = extractelement <1 x i64> %a, i32 01492 %vget_lane = trunc i64 %x to i321493 %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 01494 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 11495 ret <2 x i32> %vecinit1.i1496}1497 1498define <8 x i16> @test_dup_v2i64_v8i16(<2 x i64> %a) {1499; CHECK-SD-LABEL: test_dup_v2i64_v8i16:1500; CHECK-SD: // %bb.0: // %entry1501; CHECK-SD-NEXT: dup v0.8h, v0.h[4]1502; CHECK-SD-NEXT: ret1503;1504; CHECK-GI-LABEL: test_dup_v2i64_v8i16:1505; CHECK-GI: // %bb.0: // %entry1506; CHECK-GI-NEXT: mov x8, v0.d[1]1507; CHECK-GI-NEXT: dup v0.8h, w81508; CHECK-GI-NEXT: ret1509entry:1510 %x = extractelement <2 x i64> %a, i32 11511 %vget_lane = trunc i64 %x to i161512 %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 01513 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 11514 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 21515 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 31516 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 41517 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 51518 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 61519 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 71520 ret <8 x i16> %vecinit7.i1521}1522 1523define <4 x i32> @test_dup_v2i64_v4i32(<2 x i64> %a) {1524; CHECK-SD-LABEL: test_dup_v2i64_v4i32:1525; CHECK-SD: // %bb.0: // %entry1526; CHECK-SD-NEXT: dup v0.4s, v0.s[2]1527; CHECK-SD-NEXT: ret1528;1529; CHECK-GI-LABEL: test_dup_v2i64_v4i32:1530; CHECK-GI: // %bb.0: // %entry1531; CHECK-GI-NEXT: mov d0, v0.d[1]1532; CHECK-GI-NEXT: fmov x8, d01533; CHECK-GI-NEXT: dup v0.4s, w81534; CHECK-GI-NEXT: ret1535entry:1536 %x = extractelement <2 x i64> %a, i32 11537 %vget_lane = trunc i64 %x to i321538 %vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 01539 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 11540 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 21541 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 31542 ret <4 x i32> %vecinit3.i1543}1544 1545define <4 x i16> @test_dup_v4i32_v4i16(<4 x i32> %a) {1546; CHECK-SD-LABEL: test_dup_v4i32_v4i16:1547; CHECK-SD: // %bb.0: // %entry1548; CHECK-SD-NEXT: dup v0.4h, v0.h[2]1549; CHECK-SD-NEXT: ret1550;1551; CHECK-GI-LABEL: test_dup_v4i32_v4i16:1552; CHECK-GI: // %bb.0: // %entry1553; CHECK-GI-NEXT: mov w8, v0.s[1]1554; CHECK-GI-NEXT: dup v0.4h, w81555; CHECK-GI-NEXT: ret1556entry:1557 %x = extractelement <4 x i32> %a, i32 11558 %vget_lane = trunc i32 %x to i161559 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01560 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11561 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21562 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31563 ret <4 x i16> %vecinit3.i1564}1565 1566define <4 x i16> @test_dup_v2i64_v4i16(<2 x i64> %a) {1567; CHECK-SD-LABEL: test_dup_v2i64_v4i16:1568; CHECK-SD: // %bb.0: // %entry1569; CHECK-SD-NEXT: dup v0.4h, v0.h[0]1570; CHECK-SD-NEXT: ret1571;1572; CHECK-GI-LABEL: test_dup_v2i64_v4i16:1573; CHECK-GI: // %bb.0: // %entry1574; CHECK-GI-NEXT: fmov x8, d01575; CHECK-GI-NEXT: dup v0.4h, w81576; CHECK-GI-NEXT: ret1577entry:1578 %x = extractelement <2 x i64> %a, i32 01579 %vget_lane = trunc i64 %x to i161580 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01581 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11582 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21583 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31584 ret <4 x i16> %vecinit3.i1585}1586 1587define <2 x i32> @test_dup_v2i64_v2i32(<2 x i64> %a) {1588; CHECK-SD-LABEL: test_dup_v2i64_v2i32:1589; CHECK-SD: // %bb.0: // %entry1590; CHECK-SD-NEXT: dup v0.2s, v0.s[0]1591; CHECK-SD-NEXT: ret1592;1593; CHECK-GI-LABEL: test_dup_v2i64_v2i32:1594; CHECK-GI: // %bb.0: // %entry1595; CHECK-GI-NEXT: fmov x8, d01596; CHECK-GI-NEXT: dup v0.2s, w81597; CHECK-GI-NEXT: ret1598entry:1599 %x = extractelement <2 x i64> %a, i32 01600 %vget_lane = trunc i64 %x to i321601 %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 01602 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 11603 ret <2 x i32> %vecinit1.i1604}1605 1606 1607define <2 x float> @test_scalar_to_vector_f32_to_v2f32(<2 x float> %a) {1608; CHECK-LABEL: test_scalar_to_vector_f32_to_v2f32:1609; CHECK: // %bb.0: // %entry1610; CHECK-NEXT: fmaxp s0, v0.2s1611; CHECK-NEXT: ret1612entry:1613 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)1614 %1 = insertelement <1 x float> undef, float %0, i32 01615 %2 = extractelement <1 x float> %1, i32 01616 %vecinit1.i = insertelement <2 x float> undef, float %2, i32 01617 ret <2 x float> %vecinit1.i1618}1619 1620define <4 x float> @test_scalar_to_vector_f32_to_v4f32(<2 x float> %a) {1621; CHECK-LABEL: test_scalar_to_vector_f32_to_v4f32:1622; CHECK: // %bb.0: // %entry1623; CHECK-NEXT: fmaxp s0, v0.2s1624; CHECK-NEXT: ret1625entry:1626 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)1627 %1 = insertelement <1 x float> undef, float %0, i32 01628 %2 = extractelement <1 x float> %1, i32 01629 %vecinit1.i = insertelement <4 x float> undef, float %2, i32 01630 ret <4 x float> %vecinit1.i1631}1632 1633declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)1634 1635define <2 x i32> @test_concat_undef_v1i32(<2 x i32> %a) {1636; CHECK-SD-LABEL: test_concat_undef_v1i32:1637; CHECK-SD: // %bb.0: // %entry1638; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01639; CHECK-SD-NEXT: dup v0.2s, v0.s[0]1640; CHECK-SD-NEXT: ret1641;1642; CHECK-GI-LABEL: test_concat_undef_v1i32:1643; CHECK-GI: // %bb.0: // %entry1644; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01645; CHECK-GI-NEXT: mov v0.s[1], v0.s[0]1646; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q01647; CHECK-GI-NEXT: ret1648entry:1649 %0 = extractelement <2 x i32> %a, i32 01650 %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 11651 ret <2 x i32> %vecinit1.i1652}1653 1654declare i32 @llvm.aarch64.neon.sqabs.i32(i32) #41655 1656define <2 x i32> @test_concat_v1i32_undef(i32 %a) {1657; CHECK-LABEL: test_concat_v1i32_undef:1658; CHECK: // %bb.0: // %entry1659; CHECK-NEXT: fmov s0, w01660; CHECK-NEXT: sqabs s0, s01661; CHECK-NEXT: ret1662entry:1663 %b = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)1664 %vecinit.i432 = insertelement <2 x i32> undef, i32 %b, i32 01665 ret <2 x i32> %vecinit.i4321666}1667 1668define <2 x i32> @test_concat_same_v1i32_v1i32(<2 x i32> %a) {1669; CHECK-LABEL: test_concat_same_v1i32_v1i32:1670; CHECK: // %bb.0: // %entry1671; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01672; CHECK-NEXT: dup v0.2s, v0.s[0]1673; CHECK-NEXT: ret1674entry:1675 %0 = extractelement <2 x i32> %a, i32 01676 %vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 01677 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 11678 ret <2 x i32> %vecinit1.i1679}1680 1681define <2 x i32> @test_concat_diff_v1i32_v1i32(i32 %a, i32 %b) {1682; CHECK-LABEL: test_concat_diff_v1i32_v1i32:1683; CHECK: // %bb.0: // %entry1684; CHECK-NEXT: fmov s0, w11685; CHECK-NEXT: fmov s1, w01686; CHECK-NEXT: sqabs s2, s01687; CHECK-NEXT: sqabs s0, s11688; CHECK-NEXT: fmov w8, s21689; CHECK-NEXT: mov v0.s[1], w81690; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01691; CHECK-NEXT: ret1692entry:1693 %c = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)1694 %d = insertelement <2 x i32> undef, i32 %c, i32 01695 %e = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %b)1696 %f = insertelement <2 x i32> undef, i32 %e, i32 01697 %h = shufflevector <2 x i32> %d, <2 x i32> %f, <2 x i32> <i32 0, i32 2>1698 ret <2 x i32> %h1699}1700 1701define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {1702; CHECK-SD-LABEL: test_concat_v16i8_v16i8_v16i8:1703; CHECK-SD: // %bb.0: // %entry1704; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1705; CHECK-SD-NEXT: ret1706;1707; CHECK-GI-LABEL: test_concat_v16i8_v16i8_v16i8:1708; CHECK-GI: // %bb.0: // %entry1709; CHECK-GI-NEXT: adrp x8, .LCPI126_01710; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q11711; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI126_0]1712; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q11713; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b1714; CHECK-GI-NEXT: ret1715entry:1716 %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>1717 ret <16 x i8> %vecinit301718}1719 1720define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {1721; CHECK-SD-LABEL: test_concat_v16i8_v8i8_v16i8:1722; CHECK-SD: // %bb.0: // %entry1723; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01724; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1725; CHECK-SD-NEXT: ret1726;1727; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v16i8:1728; CHECK-GI: // %bb.0: // %entry1729; CHECK-GI-NEXT: mov v2.16b, v1.16b1730; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01731; CHECK-GI-NEXT: adrp x8, .LCPI127_01732; CHECK-GI-NEXT: mov v1.b[0], v0.b[0]1733; CHECK-GI-NEXT: mov v1.b[1], v0.b[1]1734; CHECK-GI-NEXT: mov v1.b[2], v0.b[2]1735; CHECK-GI-NEXT: mov v1.b[3], v0.b[3]1736; CHECK-GI-NEXT: mov v1.b[4], v0.b[4]1737; CHECK-GI-NEXT: mov v1.b[5], v0.b[5]1738; CHECK-GI-NEXT: mov v1.b[6], v0.b[6]1739; CHECK-GI-NEXT: mov v1.b[7], v0.b[7]1740; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI127_0]1741; CHECK-GI-NEXT: tbl v0.16b, { v1.16b, v2.16b }, v0.16b1742; CHECK-GI-NEXT: ret1743entry:1744 %vecext = extractelement <8 x i8> %x, i32 01745 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 01746 %vecext1 = extractelement <8 x i8> %x, i32 11747 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 11748 %vecext3 = extractelement <8 x i8> %x, i32 21749 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 21750 %vecext5 = extractelement <8 x i8> %x, i32 31751 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 31752 %vecext7 = extractelement <8 x i8> %x, i32 41753 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 41754 %vecext9 = extractelement <8 x i8> %x, i32 51755 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 51756 %vecext11 = extractelement <8 x i8> %x, i32 61757 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 61758 %vecext13 = extractelement <8 x i8> %x, i32 71759 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 71760 %vecinit30 = shufflevector <16 x i8> %vecinit14, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>1761 ret <16 x i8> %vecinit301762}1763 1764define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {1765; CHECK-SD-LABEL: test_concat_v16i8_v16i8_v8i8:1766; CHECK-SD: // %bb.0: // %entry1767; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11768; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1769; CHECK-SD-NEXT: ret1770;1771; CHECK-GI-LABEL: test_concat_v16i8_v16i8_v8i8:1772; CHECK-GI: // %bb.0: // %entry1773; CHECK-GI-NEXT: mov b2, v0.b[0]1774; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11775; CHECK-GI-NEXT: mov v2.b[1], v0.b[1]1776; CHECK-GI-NEXT: mov v2.b[2], v0.b[2]1777; CHECK-GI-NEXT: mov v2.b[3], v0.b[3]1778; CHECK-GI-NEXT: mov v2.b[4], v0.b[4]1779; CHECK-GI-NEXT: mov v2.b[5], v0.b[5]1780; CHECK-GI-NEXT: mov v2.b[6], v0.b[6]1781; CHECK-GI-NEXT: mov v2.b[7], v0.b[7]1782; CHECK-GI-NEXT: mov v2.b[8], v1.b[0]1783; CHECK-GI-NEXT: mov v2.b[9], v1.b[1]1784; CHECK-GI-NEXT: mov v2.b[10], v1.b[2]1785; CHECK-GI-NEXT: mov v2.b[11], v1.b[3]1786; CHECK-GI-NEXT: mov v2.b[12], v1.b[4]1787; CHECK-GI-NEXT: mov v2.b[13], v1.b[5]1788; CHECK-GI-NEXT: mov v2.b[14], v1.b[6]1789; CHECK-GI-NEXT: mov v2.b[15], v1.b[7]1790; CHECK-GI-NEXT: mov v0.16b, v2.16b1791; CHECK-GI-NEXT: ret1792entry:1793 %vecext = extractelement <16 x i8> %x, i32 01794 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 01795 %vecext1 = extractelement <16 x i8> %x, i32 11796 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 11797 %vecext3 = extractelement <16 x i8> %x, i32 21798 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 21799 %vecext5 = extractelement <16 x i8> %x, i32 31800 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 31801 %vecext7 = extractelement <16 x i8> %x, i32 41802 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 41803 %vecext9 = extractelement <16 x i8> %x, i32 51804 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 51805 %vecext11 = extractelement <16 x i8> %x, i32 61806 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 61807 %vecext13 = extractelement <16 x i8> %x, i32 71808 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 71809 %vecext15 = extractelement <8 x i8> %y, i32 01810 %vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 81811 %vecext17 = extractelement <8 x i8> %y, i32 11812 %vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 91813 %vecext19 = extractelement <8 x i8> %y, i32 21814 %vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 101815 %vecext21 = extractelement <8 x i8> %y, i32 31816 %vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 111817 %vecext23 = extractelement <8 x i8> %y, i32 41818 %vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 121819 %vecext25 = extractelement <8 x i8> %y, i32 51820 %vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 131821 %vecext27 = extractelement <8 x i8> %y, i32 61822 %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 141823 %vecext29 = extractelement <8 x i8> %y, i32 71824 %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 151825 ret <16 x i8> %vecinit301826}1827 1828define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {1829; CHECK-SD-LABEL: test_concat_v16i8_v8i8_v8i8:1830; CHECK-SD: // %bb.0: // %entry1831; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01832; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11833; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1834; CHECK-SD-NEXT: ret1835;1836; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v8i8:1837; CHECK-GI: // %bb.0: // %entry1838; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01839; CHECK-GI-NEXT: mov v2.b[0], v0.b[0]1840; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11841; CHECK-GI-NEXT: mov v2.b[1], v0.b[1]1842; CHECK-GI-NEXT: mov v2.b[2], v0.b[2]1843; CHECK-GI-NEXT: mov v2.b[3], v0.b[3]1844; CHECK-GI-NEXT: mov v2.b[4], v0.b[4]1845; CHECK-GI-NEXT: mov v2.b[5], v0.b[5]1846; CHECK-GI-NEXT: mov v2.b[6], v0.b[6]1847; CHECK-GI-NEXT: mov v2.b[7], v0.b[7]1848; CHECK-GI-NEXT: mov v2.b[8], v1.b[0]1849; CHECK-GI-NEXT: mov v2.b[9], v1.b[1]1850; CHECK-GI-NEXT: mov v2.b[10], v1.b[2]1851; CHECK-GI-NEXT: mov v2.b[11], v1.b[3]1852; CHECK-GI-NEXT: mov v2.b[12], v1.b[4]1853; CHECK-GI-NEXT: mov v2.b[13], v1.b[5]1854; CHECK-GI-NEXT: mov v2.b[14], v1.b[6]1855; CHECK-GI-NEXT: mov v2.b[15], v1.b[7]1856; CHECK-GI-NEXT: mov v0.16b, v2.16b1857; CHECK-GI-NEXT: ret1858entry:1859 %vecext = extractelement <8 x i8> %x, i32 01860 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 01861 %vecext1 = extractelement <8 x i8> %x, i32 11862 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 11863 %vecext3 = extractelement <8 x i8> %x, i32 21864 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 21865 %vecext5 = extractelement <8 x i8> %x, i32 31866 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 31867 %vecext7 = extractelement <8 x i8> %x, i32 41868 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 41869 %vecext9 = extractelement <8 x i8> %x, i32 51870 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 51871 %vecext11 = extractelement <8 x i8> %x, i32 61872 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 61873 %vecext13 = extractelement <8 x i8> %x, i32 71874 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 71875 %vecext15 = extractelement <8 x i8> %y, i32 01876 %vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 81877 %vecext17 = extractelement <8 x i8> %y, i32 11878 %vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 91879 %vecext19 = extractelement <8 x i8> %y, i32 21880 %vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 101881 %vecext21 = extractelement <8 x i8> %y, i32 31882 %vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 111883 %vecext23 = extractelement <8 x i8> %y, i32 41884 %vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 121885 %vecext25 = extractelement <8 x i8> %y, i32 51886 %vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 131887 %vecext27 = extractelement <8 x i8> %y, i32 61888 %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 141889 %vecext29 = extractelement <8 x i8> %y, i32 71890 %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 151891 ret <16 x i8> %vecinit301892}1893 1894define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {1895; CHECK-SD-LABEL: test_concat_v8i16_v8i16_v8i16:1896; CHECK-SD: // %bb.0: // %entry1897; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1898; CHECK-SD-NEXT: ret1899;1900; CHECK-GI-LABEL: test_concat_v8i16_v8i16_v8i16:1901; CHECK-GI: // %bb.0: // %entry1902; CHECK-GI-NEXT: adrp x8, .LCPI130_01903; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q11904; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI130_0]1905; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q11906; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b1907; CHECK-GI-NEXT: ret1908entry:1909 %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>1910 ret <8 x i16> %vecinit141911}1912 1913define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {1914; CHECK-SD-LABEL: test_concat_v8i16_v4i16_v8i16:1915; CHECK-SD: // %bb.0: // %entry1916; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01917; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1918; CHECK-SD-NEXT: ret1919;1920; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v8i16:1921; CHECK-GI: // %bb.0: // %entry1922; CHECK-GI-NEXT: mov v2.16b, v1.16b1923; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01924; CHECK-GI-NEXT: adrp x8, .LCPI131_01925; CHECK-GI-NEXT: mov v1.h[0], v0.h[0]1926; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]1927; CHECK-GI-NEXT: mov v1.h[2], v0.h[2]1928; CHECK-GI-NEXT: mov v1.h[3], v0.h[3]1929; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI131_0]1930; CHECK-GI-NEXT: tbl v0.16b, { v1.16b, v2.16b }, v0.16b1931; CHECK-GI-NEXT: ret1932entry:1933 %vecext = extractelement <4 x i16> %x, i32 01934 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 01935 %vecext1 = extractelement <4 x i16> %x, i32 11936 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 11937 %vecext3 = extractelement <4 x i16> %x, i32 21938 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 21939 %vecext5 = extractelement <4 x i16> %x, i32 31940 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 31941 %vecinit14 = shufflevector <8 x i16> %vecinit6, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>1942 ret <8 x i16> %vecinit141943}1944 1945define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {1946; CHECK-SD-LABEL: test_concat_v8i16_v8i16_v4i16:1947; CHECK-SD: // %bb.0: // %entry1948; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11949; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1950; CHECK-SD-NEXT: ret1951;1952; CHECK-GI-LABEL: test_concat_v8i16_v8i16_v4i16:1953; CHECK-GI: // %bb.0: // %entry1954; CHECK-GI-NEXT: mov h2, v0.h[0]1955; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11956; CHECK-GI-NEXT: mov v2.h[1], v0.h[1]1957; CHECK-GI-NEXT: mov v2.h[2], v0.h[2]1958; CHECK-GI-NEXT: mov v2.h[3], v0.h[3]1959; CHECK-GI-NEXT: mov v2.h[4], v1.h[0]1960; CHECK-GI-NEXT: mov v2.h[5], v1.h[1]1961; CHECK-GI-NEXT: mov v2.h[6], v1.h[2]1962; CHECK-GI-NEXT: mov v2.h[7], v1.h[3]1963; CHECK-GI-NEXT: mov v0.16b, v2.16b1964; CHECK-GI-NEXT: ret1965entry:1966 %vecext = extractelement <8 x i16> %x, i32 01967 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 01968 %vecext1 = extractelement <8 x i16> %x, i32 11969 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 11970 %vecext3 = extractelement <8 x i16> %x, i32 21971 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 21972 %vecext5 = extractelement <8 x i16> %x, i32 31973 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 31974 %vecext7 = extractelement <4 x i16> %y, i32 01975 %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 41976 %vecext9 = extractelement <4 x i16> %y, i32 11977 %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 51978 %vecext11 = extractelement <4 x i16> %y, i32 21979 %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 61980 %vecext13 = extractelement <4 x i16> %y, i32 31981 %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 71982 ret <8 x i16> %vecinit141983}1984 1985define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {1986; CHECK-SD-LABEL: test_concat_v8i16_v4i16_v4i16:1987; CHECK-SD: // %bb.0: // %entry1988; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01989; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11990; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1991; CHECK-SD-NEXT: ret1992;1993; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v4i16:1994; CHECK-GI: // %bb.0: // %entry1995; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01996; CHECK-GI-NEXT: mov v2.h[0], v0.h[0]1997; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11998; CHECK-GI-NEXT: mov v2.h[1], v0.h[1]1999; CHECK-GI-NEXT: mov v2.h[2], v0.h[2]2000; CHECK-GI-NEXT: mov v2.h[3], v0.h[3]2001; CHECK-GI-NEXT: mov v2.h[4], v1.h[0]2002; CHECK-GI-NEXT: mov v2.h[5], v1.h[1]2003; CHECK-GI-NEXT: mov v2.h[6], v1.h[2]2004; CHECK-GI-NEXT: mov v2.h[7], v1.h[3]2005; CHECK-GI-NEXT: mov v0.16b, v2.16b2006; CHECK-GI-NEXT: ret2007entry:2008 %vecext = extractelement <4 x i16> %x, i32 02009 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 02010 %vecext1 = extractelement <4 x i16> %x, i32 12011 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 12012 %vecext3 = extractelement <4 x i16> %x, i32 22013 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 22014 %vecext5 = extractelement <4 x i16> %x, i32 32015 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 32016 %vecext7 = extractelement <4 x i16> %y, i32 02017 %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 42018 %vecext9 = extractelement <4 x i16> %y, i32 12019 %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 52020 %vecext11 = extractelement <4 x i16> %y, i32 22021 %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 62022 %vecext13 = extractelement <4 x i16> %y, i32 32023 %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 72024 ret <8 x i16> %vecinit142025}2026 2027define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {2028; CHECK-SD-LABEL: test_concat_v4i32_v4i32_v4i32:2029; CHECK-SD: // %bb.0: // %entry2030; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]2031; CHECK-SD-NEXT: ret2032;2033; CHECK-GI-LABEL: test_concat_v4i32_v4i32_v4i32:2034; CHECK-GI: // %bb.0: // %entry2035; CHECK-GI-NEXT: adrp x8, .LCPI134_02036; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q12037; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI134_0]2038; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q12039; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b2040; CHECK-GI-NEXT: ret2041entry:2042 %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>2043 ret <4 x i32> %vecinit62044}2045 2046define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {2047; CHECK-SD-LABEL: test_concat_v4i32_v2i32_v4i32:2048; CHECK-SD: // %bb.0: // %entry2049; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q02050; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]2051; CHECK-SD-NEXT: ret2052;2053; CHECK-GI-LABEL: test_concat_v4i32_v2i32_v4i32:2054; CHECK-GI: // %bb.0: // %entry2055; CHECK-GI-NEXT: mov v2.16b, v1.16b2056; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q02057; CHECK-GI-NEXT: adrp x8, .LCPI135_02058; CHECK-GI-NEXT: mov v1.s[0], v0.s[0]2059; CHECK-GI-NEXT: mov v1.s[1], v0.s[1]2060; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI135_0]2061; CHECK-GI-NEXT: tbl v0.16b, { v1.16b, v2.16b }, v0.16b2062; CHECK-GI-NEXT: ret2063entry:2064 %vecext = extractelement <2 x i32> %x, i32 02065 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 02066 %vecext1 = extractelement <2 x i32> %x, i32 12067 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 12068 %vecinit6 = shufflevector <4 x i32> %vecinit2, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>2069 ret <4 x i32> %vecinit62070}2071 2072define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {2073; CHECK-SD-LABEL: test_concat_v4i32_v4i32_v2i32:2074; CHECK-SD: // %bb.0: // %entry2075; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q12076; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]2077; CHECK-SD-NEXT: ret2078;2079; CHECK-GI-LABEL: test_concat_v4i32_v4i32_v2i32:2080; CHECK-GI: // %bb.0: // %entry2081; CHECK-GI-NEXT: mov s2, v0.s[0]2082; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q12083; CHECK-GI-NEXT: mov v2.s[1], v0.s[1]2084; CHECK-GI-NEXT: mov v2.s[2], v1.s[0]2085; CHECK-GI-NEXT: mov v2.s[3], v1.s[1]2086; CHECK-GI-NEXT: mov v0.16b, v2.16b2087; CHECK-GI-NEXT: ret2088entry:2089 %vecext = extractelement <4 x i32> %x, i32 02090 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 02091 %vecext1 = extractelement <4 x i32> %x, i32 12092 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 12093 %vecext3 = extractelement <2 x i32> %y, i32 02094 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 22095 %vecext5 = extractelement <2 x i32> %y, i32 12096 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 32097 ret <4 x i32> %vecinit62098}2099 2100define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {2101; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:2102; CHECK: // %bb.0: // %entry2103; CHECK-NEXT: // kill: def $d0 killed $d0 def $q02104; CHECK-NEXT: // kill: def $d1 killed $d1 def $q12105; CHECK-NEXT: mov v0.d[1], v1.d[0]2106; CHECK-NEXT: ret2107entry:2108 %vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2109 ret <4 x i32> %vecinit62110}2111 2112define <2 x i64> @test_concat_v2i64_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) #0 {2113; CHECK-LABEL: test_concat_v2i64_v2i64_v2i64:2114; CHECK: // %bb.0: // %entry2115; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d2116; CHECK-NEXT: ret2117entry:2118 %vecinit2 = shufflevector <2 x i64> %x, <2 x i64> %y, <2 x i32> <i32 0, i32 2>2119 ret <2 x i64> %vecinit22120}2121 2122define <2 x i64> @test_concat_v2i64_v1i64_v2i64(<1 x i64> %x, <2 x i64> %y) #0 {2123; CHECK-LABEL: test_concat_v2i64_v1i64_v2i64:2124; CHECK: // %bb.0: // %entry2125; CHECK-NEXT: // kill: def $d0 killed $d0 def $q02126; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d2127; CHECK-NEXT: ret2128entry:2129 %vecext = extractelement <1 x i64> %x, i32 02130 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 02131 %vecinit2 = shufflevector <2 x i64> %vecinit, <2 x i64> %y, <2 x i32> <i32 0, i32 2>2132 ret <2 x i64> %vecinit22133}2134 2135define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {2136; CHECK-SD-LABEL: test_concat_v2i64_v2i64_v1i64:2137; CHECK-SD: // %bb.0: // %entry2138; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q12139; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]2140; CHECK-SD-NEXT: ret2141;2142; CHECK-GI-LABEL: test_concat_v2i64_v2i64_v1i64:2143; CHECK-GI: // %bb.0: // %entry2144; CHECK-GI-NEXT: mov d0, v0.d[0]2145; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q12146; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]2147; CHECK-GI-NEXT: ret2148entry:2149 %vecext = extractelement <2 x i64> %x, i32 02150 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 02151 %vecext1 = extractelement <1 x i64> %y, i32 02152 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 12153 ret <2 x i64> %vecinit22154}2155 2156define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {2157; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:2158; CHECK: // %bb.0: // %entry2159; CHECK-NEXT: // kill: def $d0 killed $d0 def $q02160; CHECK-NEXT: // kill: def $d1 killed $d1 def $q12161; CHECK-NEXT: mov v0.d[1], v1.d[0]2162; CHECK-NEXT: ret2163entry:2164 %vecext = extractelement <1 x i64> %x, i32 02165 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 02166 %vecext1 = extractelement <1 x i64> %y, i32 02167 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 12168 ret <2 x i64> %vecinit22169}2170 2171 2172define <4 x i16> @concat_vector_v4i16_const() {2173; CHECK-LABEL: concat_vector_v4i16_const:2174; CHECK: // %bb.0:2175; CHECK-NEXT: movi v0.2d, #00000000000000002176; CHECK-NEXT: ret2177 %r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <4 x i32> zeroinitializer2178 ret <4 x i16> %r2179}2180 2181define <4 x i16> @concat_vector_v4i16_const_one() {2182; CHECK-LABEL: concat_vector_v4i16_const_one:2183; CHECK: // %bb.0:2184; CHECK-NEXT: movi v0.4h, #12185; CHECK-NEXT: ret2186 %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <4 x i32> zeroinitializer2187 ret <4 x i16> %r2188}2189 2190define <4 x i32> @concat_vector_v4i32_const() {2191; CHECK-LABEL: concat_vector_v4i32_const:2192; CHECK: // %bb.0:2193; CHECK-NEXT: movi v0.2d, #00000000000000002194; CHECK-NEXT: ret2195 %r = shufflevector <1 x i32> zeroinitializer, <1 x i32> undef, <4 x i32> zeroinitializer2196 ret <4 x i32> %r2197}2198 2199define <8 x i8> @concat_vector_v8i8_const() {2200; CHECK-LABEL: concat_vector_v8i8_const:2201; CHECK: // %bb.0:2202; CHECK-NEXT: movi v0.2d, #00000000000000002203; CHECK-NEXT: ret2204 %r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <8 x i32> zeroinitializer2205 ret <8 x i8> %r2206}2207 2208define <8 x i16> @concat_vector_v8i16_const() {2209; CHECK-LABEL: concat_vector_v8i16_const:2210; CHECK: // %bb.0:2211; CHECK-NEXT: movi v0.2d, #00000000000000002212; CHECK-NEXT: ret2213 %r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <8 x i32> zeroinitializer2214 ret <8 x i16> %r2215}2216 2217define <8 x i16> @concat_vector_v8i16_const_one() {2218; CHECK-LABEL: concat_vector_v8i16_const_one:2219; CHECK: // %bb.0:2220; CHECK-NEXT: movi v0.8h, #12221; CHECK-NEXT: ret2222 %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <8 x i32> zeroinitializer2223 ret <8 x i16> %r2224}2225 2226define <16 x i8> @concat_vector_v16i8_const() {2227; CHECK-LABEL: concat_vector_v16i8_const:2228; CHECK: // %bb.0:2229; CHECK-NEXT: movi v0.2d, #00000000000000002230; CHECK-NEXT: ret2231 %r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <16 x i32> zeroinitializer2232 ret <16 x i8> %r2233}2234 2235define <4 x i16> @concat_vector_v4i16(<1 x i16> %a) {2236; CHECK-LABEL: concat_vector_v4i16:2237; CHECK: // %bb.0:2238; CHECK-NEXT: // kill: def $d0 killed $d0 def $q02239; CHECK-NEXT: dup v0.4h, v0.h[0]2240; CHECK-NEXT: ret2241 %r = shufflevector <1 x i16> %a, <1 x i16> undef, <4 x i32> zeroinitializer2242 ret <4 x i16> %r2243}2244 2245define <4 x i32> @concat_vector_v4i32(<1 x i32> %a) {2246; CHECK-LABEL: concat_vector_v4i32:2247; CHECK: // %bb.0:2248; CHECK-NEXT: // kill: def $d0 killed $d0 def $q02249; CHECK-NEXT: dup v0.4s, v0.s[0]2250; CHECK-NEXT: ret2251 %r = shufflevector <1 x i32> %a, <1 x i32> undef, <4 x i32> zeroinitializer2252 ret <4 x i32> %r2253}2254 2255define <8 x i8> @concat_vector_v8i8(<1 x i8> %a) {2256; CHECK-SD-LABEL: concat_vector_v8i8:2257; CHECK-SD: // %bb.0:2258; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q02259; CHECK-SD-NEXT: dup v0.8b, v0.b[0]2260; CHECK-SD-NEXT: ret2261;2262; CHECK-GI-LABEL: concat_vector_v8i8:2263; CHECK-GI: // %bb.0:2264; CHECK-GI-NEXT: fmov w8, s02265; CHECK-GI-NEXT: dup v0.8b, w82266; CHECK-GI-NEXT: ret2267 %r = shufflevector <1 x i8> %a, <1 x i8> undef, <8 x i32> zeroinitializer2268 ret <8 x i8> %r2269}2270 2271define <8 x i16> @concat_vector_v8i16(<1 x i16> %a) {2272; CHECK-LABEL: concat_vector_v8i16:2273; CHECK: // %bb.0:2274; CHECK-NEXT: // kill: def $d0 killed $d0 def $q02275; CHECK-NEXT: dup v0.8h, v0.h[0]2276; CHECK-NEXT: ret2277 %r = shufflevector <1 x i16> %a, <1 x i16> undef, <8 x i32> zeroinitializer2278 ret <8 x i16> %r2279}2280 2281define <16 x i8> @concat_vector_v16i8(<1 x i8> %a) {2282; CHECK-SD-LABEL: concat_vector_v16i8:2283; CHECK-SD: // %bb.0:2284; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q02285; CHECK-SD-NEXT: dup v0.16b, v0.b[0]2286; CHECK-SD-NEXT: ret2287;2288; CHECK-GI-LABEL: concat_vector_v16i8:2289; CHECK-GI: // %bb.0:2290; CHECK-GI-NEXT: fmov w8, s02291; CHECK-GI-NEXT: dup v0.16b, w82292; CHECK-GI-NEXT: ret2293 %r = shufflevector <1 x i8> %a, <1 x i8> undef, <16 x i32> zeroinitializer2294 ret <16 x i8> %r2295}2296