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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s3; arm64 has a separate copy due to intrinsics4 5define <4 x i32> @copyTuple.QPair(ptr %a, ptr %b) {6; CHECK-LABEL: copyTuple.QPair:7; CHECK:       // %bb.0: // %entry8; CHECK-NEXT:    movi v3.4s, #29; CHECK-NEXT:    movi v2.2d, #0xffffffffffffffff10; CHECK-NEXT:    mov v1.16b, v3.16b11; CHECK-NEXT:    mov v0.16b, v2.16b12; CHECK-NEXT:    ld2 { v0.s, v1.s }[1], [x0]13; CHECK-NEXT:    mov v1.16b, v2.16b14; CHECK-NEXT:    ld2 { v0.s, v1.s }[1], [x1]15; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $q0_q116; CHECK-NEXT:    ret17entry:18  %vld = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i64 1, ptr %a)19  %extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 020  %vld1 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i64 1, ptr %b)21  %vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld1, 022  ret <4 x i32> %vld1.fca.0.extract23}24 25define <4 x i32> @copyTuple.QTriple(ptr %a, ptr %b, <4 x i32> %c) {26; CHECK-LABEL: copyTuple.QTriple:27; CHECK:       // %bb.0: // %entry28; CHECK-NEXT:    // kill: def $q0 killed $q0 def $q31_q0_q129; CHECK-NEXT:    movi v31.2d, #0xffffffffffffffff30; CHECK-NEXT:    mov v1.16b, v0.16b31; CHECK-NEXT:    mov v2.16b, v31.16b32; CHECK-NEXT:    mov v3.16b, v0.16b33; CHECK-NEXT:    mov v4.16b, v1.16b34; CHECK-NEXT:    ld3 { v2.s, v3.s, v4.s }[1], [x0]35; CHECK-NEXT:    mov v3.16b, v31.16b36; CHECK-NEXT:    mov v4.16b, v0.16b37; CHECK-NEXT:    ld3 { v2.s, v3.s, v4.s }[1], [x1]38; CHECK-NEXT:    mov v0.16b, v2.16b39; CHECK-NEXT:    ret40entry:41  %vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i64 1, ptr %a)42  %extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld, 043  %vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, i64 1, ptr %b)44  %vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld1, 045  ret <4 x i32> %vld1.fca.0.extract46}47 48define <4 x i32> @copyTuple.QQuad(ptr %a, ptr %b, <4 x i32> %c) {49; CHECK-LABEL: copyTuple.QQuad:50; CHECK:       // %bb.0: // %entry51; CHECK-NEXT:    // kill: def $q0 killed $q0 def $q31_q0_q1_q252; CHECK-NEXT:    movi v31.2d, #0xffffffffffffffff53; CHECK-NEXT:    mov v1.16b, v0.16b54; CHECK-NEXT:    mov v2.16b, v0.16b55; CHECK-NEXT:    mov v3.16b, v31.16b56; CHECK-NEXT:    mov v4.16b, v0.16b57; CHECK-NEXT:    mov v5.16b, v1.16b58; CHECK-NEXT:    mov v6.16b, v2.16b59; CHECK-NEXT:    ld4 { v3.s, v4.s, v5.s, v6.s }[1], [x0]60; CHECK-NEXT:    mov v4.16b, v31.16b61; CHECK-NEXT:    mov v5.16b, v0.16b62; CHECK-NEXT:    mov v6.16b, v0.16b63; CHECK-NEXT:    ld4 { v3.s, v4.s, v5.s, v6.s }[1], [x1]64; CHECK-NEXT:    mov v0.16b, v3.16b65; CHECK-NEXT:    ret66entry:67  %vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, <4 x i32> %c, i64 1, ptr %a)68  %extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld, 069  %vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i64 1, ptr %b)70  %vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld1, 071  ret <4 x i32> %vld1.fca.0.extract72}73 74declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0(<4 x i32>, <4 x i32>, i64, ptr)75declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, i64, ptr)76declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, ptr)77