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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <16 x i8> @div16xi8(<16 x i8> %x) {6; CHECK-SD-LABEL: div16xi8:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: movi v1.16b, #419; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b10; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b11; CHECK-SD-NEXT: uzp2 v0.16b, v0.16b, v2.16b12; CHECK-SD-NEXT: sshr v0.16b, v0.16b, #213; CHECK-SD-NEXT: usra v0.16b, v0.16b, #714; CHECK-SD-NEXT: ret15;16; CHECK-GI-LABEL: div16xi8:17; CHECK-GI: // %bb.0:18; CHECK-GI-NEXT: movi v1.16b, #4119; CHECK-GI-NEXT: smull2 v2.8h, v0.16b, v1.16b20; CHECK-GI-NEXT: smull v0.8h, v0.8b, v1.8b21; CHECK-GI-NEXT: uzp2 v1.16b, v0.16b, v2.16b22; CHECK-GI-NEXT: sshr v0.16b, v1.16b, #223; CHECK-GI-NEXT: ushr v0.16b, v0.16b, #724; CHECK-GI-NEXT: ssra v0.16b, v1.16b, #225; CHECK-GI-NEXT: ret26 %div = sdiv <16 x i8> %x, <i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25>27 ret <16 x i8> %div28}29 30define <8 x i16> @div8xi16(<8 x i16> %x) {31; CHECK-SD-LABEL: div8xi16:32; CHECK-SD: // %bb.0:33; CHECK-SD-NEXT: mov w8, #40815 // =0x9f6f34; CHECK-SD-NEXT: dup v1.8h, w835; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h36; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h37; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h38; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h39; CHECK-SD-NEXT: sshr v0.8h, v0.8h, #1240; CHECK-SD-NEXT: usra v0.8h, v0.8h, #1541; CHECK-SD-NEXT: ret42;43; CHECK-GI-LABEL: div8xi16:44; CHECK-GI: // %bb.0:45; CHECK-GI-NEXT: adrp x8, .LCPI1_046; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]47; CHECK-GI-NEXT: smull2 v2.4s, v0.8h, v1.8h48; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h49; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h50; CHECK-GI-NEXT: add v1.8h, v1.8h, v0.8h51; CHECK-GI-NEXT: sshr v0.8h, v1.8h, #1252; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #1553; CHECK-GI-NEXT: ssra v0.8h, v1.8h, #1254; CHECK-GI-NEXT: ret55 %div = sdiv <8 x i16> %x, <i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577>56 ret <8 x i16> %div57}58 59define <4 x i32> @div32xi4(<4 x i32> %x) {60; CHECK-SD-LABEL: div32xi4:61; CHECK-SD: // %bb.0:62; CHECK-SD-NEXT: mov w8, #7527 // =0x1d6763; CHECK-SD-NEXT: movk w8, #28805, lsl #1664; CHECK-SD-NEXT: dup v1.4s, w865; CHECK-SD-NEXT: smull2 v2.2d, v0.4s, v1.4s66; CHECK-SD-NEXT: smull v0.2d, v0.2s, v1.2s67; CHECK-SD-NEXT: uzp2 v1.4s, v0.4s, v2.4s68; CHECK-SD-NEXT: sshr v0.4s, v1.4s, #2269; CHECK-SD-NEXT: usra v0.4s, v1.4s, #3170; CHECK-SD-NEXT: ret71;72; CHECK-GI-LABEL: div32xi4:73; CHECK-GI: // %bb.0:74; CHECK-GI-NEXT: adrp x8, .LCPI2_075; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]76; CHECK-GI-NEXT: smull2 v2.2d, v0.4s, v1.4s77; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s78; CHECK-GI-NEXT: uzp2 v1.4s, v0.4s, v2.4s79; CHECK-GI-NEXT: sshr v0.4s, v1.4s, #2280; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #3181; CHECK-GI-NEXT: ssra v0.4s, v1.4s, #2282; CHECK-GI-NEXT: ret83 %div = sdiv <4 x i32> %x, <i32 9542677, i32 9542677, i32 9542677, i32 9542677>84 ret <4 x i32> %div85}86 87define <16 x i8> @udiv16xi8(<16 x i8> %x) {88; CHECK-LABEL: udiv16xi8:89; CHECK: // %bb.0:90; CHECK-NEXT: movi v1.16b, #12191; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b92; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b93; CHECK-NEXT: uzp2 v0.16b, v0.16b, v2.16b94; CHECK-NEXT: ushr v0.16b, v0.16b, #595; CHECK-NEXT: ret96 %div = udiv <16 x i8> %x, <i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68>97 ret <16 x i8> %div98}99 100define <8 x i16> @udiv8xi16(<8 x i16> %x) {101; CHECK-SD-LABEL: udiv8xi16:102; CHECK-SD: // %bb.0:103; CHECK-SD-NEXT: mov w8, #16593 // =0x40d1104; CHECK-SD-NEXT: dup v1.8h, w8105; CHECK-SD-NEXT: umull2 v2.4s, v0.8h, v1.8h106; CHECK-SD-NEXT: umull v1.4s, v0.4h, v1.4h107; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h108; CHECK-SD-NEXT: sub v0.8h, v0.8h, v1.8h109; CHECK-SD-NEXT: usra v1.8h, v0.8h, #1110; CHECK-SD-NEXT: ushr v0.8h, v1.8h, #12111; CHECK-SD-NEXT: ret112;113; CHECK-GI-LABEL: udiv8xi16:114; CHECK-GI: // %bb.0:115; CHECK-GI-NEXT: adrp x8, .LCPI4_0116; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]117; CHECK-GI-NEXT: umull2 v2.4s, v0.8h, v1.8h118; CHECK-GI-NEXT: umull v1.4s, v0.4h, v1.4h119; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h120; CHECK-GI-NEXT: sub v0.8h, v0.8h, v1.8h121; CHECK-GI-NEXT: usra v1.8h, v0.8h, #1122; CHECK-GI-NEXT: ushr v0.8h, v1.8h, #12123; CHECK-GI-NEXT: ret124 %div = udiv <8 x i16> %x, <i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537>125 ret <8 x i16> %div126}127 128define <4 x i32> @udiv32xi4(<4 x i32> %x) {129; CHECK-SD-LABEL: udiv32xi4:130; CHECK-SD: // %bb.0:131; CHECK-SD-NEXT: mov w8, #16747 // =0x416b132; CHECK-SD-NEXT: movk w8, #31439, lsl #16133; CHECK-SD-NEXT: dup v1.4s, w8134; CHECK-SD-NEXT: umull2 v2.2d, v0.4s, v1.4s135; CHECK-SD-NEXT: umull v0.2d, v0.2s, v1.2s136; CHECK-SD-NEXT: uzp2 v0.4s, v0.4s, v2.4s137; CHECK-SD-NEXT: ushr v0.4s, v0.4s, #22138; CHECK-SD-NEXT: ret139;140; CHECK-GI-LABEL: udiv32xi4:141; CHECK-GI: // %bb.0:142; CHECK-GI-NEXT: adrp x8, .LCPI5_0143; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]144; CHECK-GI-NEXT: umull2 v2.2d, v0.4s, v1.4s145; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s146; CHECK-GI-NEXT: uzp2 v0.4s, v0.4s, v2.4s147; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #22148; CHECK-GI-NEXT: ret149 %div = udiv <4 x i32> %x, <i32 8743143, i32 8743143, i32 8743143, i32 8743143>150 ret <4 x i32> %div151}152 153define <2 x i64> @udiv_v2i64(<2 x i64> %a) {154; CHECK-SD-LABEL: udiv_v2i64:155; CHECK-SD: // %bb.0:156; CHECK-SD-NEXT: mov x8, #9363 // =0x2493157; CHECK-SD-NEXT: fmov x10, d0158; CHECK-SD-NEXT: mov x9, v0.d[1]159; CHECK-SD-NEXT: movk x8, #37449, lsl #16160; CHECK-SD-NEXT: movk x8, #18724, lsl #32161; CHECK-SD-NEXT: movk x8, #9362, lsl #48162; CHECK-SD-NEXT: umulh x11, x10, x8163; CHECK-SD-NEXT: umulh x8, x9, x8164; CHECK-SD-NEXT: sub x10, x10, x11165; CHECK-SD-NEXT: add x10, x11, x10, lsr #1166; CHECK-SD-NEXT: sub x9, x9, x8167; CHECK-SD-NEXT: add x8, x8, x9, lsr #1168; CHECK-SD-NEXT: lsr x9, x10, #2169; CHECK-SD-NEXT: fmov d0, x9170; CHECK-SD-NEXT: lsr x8, x8, #2171; CHECK-SD-NEXT: mov v0.d[1], x8172; CHECK-SD-NEXT: ret173;174; CHECK-GI-LABEL: udiv_v2i64:175; CHECK-GI: // %bb.0:176; CHECK-GI-NEXT: mov x8, #9363 // =0x2493177; CHECK-GI-NEXT: fmov x10, d0178; CHECK-GI-NEXT: mov x9, v0.d[1]179; CHECK-GI-NEXT: movk x8, #37449, lsl #16180; CHECK-GI-NEXT: movk x8, #18724, lsl #32181; CHECK-GI-NEXT: movk x8, #9362, lsl #48182; CHECK-GI-NEXT: umulh x10, x10, x8183; CHECK-GI-NEXT: umulh x8, x9, x8184; CHECK-GI-NEXT: fmov d1, x10185; CHECK-GI-NEXT: mov v1.d[1], x8186; CHECK-GI-NEXT: sub v0.2d, v0.2d, v1.2d187; CHECK-GI-NEXT: usra v1.2d, v0.2d, #1188; CHECK-GI-NEXT: ushr v0.2d, v1.2d, #2189; CHECK-GI-NEXT: ret190 %r = udiv <2 x i64> %a, splat (i64 7)191 ret <2 x i64> %r192}193