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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s3; arm64 has its own copy of this because of the intrinsics4 5define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {6; CHECK-LABEL: mul8xi8:7; CHECK: // %bb.0:8; CHECK-NEXT: mul v0.8b, v0.8b, v1.8b9; CHECK-NEXT: ret10 %tmp3 = mul <8 x i8> %A, %B;11 ret <8 x i8> %tmp312}13 14define <16 x i8> @mul16xi8(<16 x i8> %A, <16 x i8> %B) {15; CHECK-LABEL: mul16xi8:16; CHECK: // %bb.0:17; CHECK-NEXT: mul v0.16b, v0.16b, v1.16b18; CHECK-NEXT: ret19 %tmp3 = mul <16 x i8> %A, %B;20 ret <16 x i8> %tmp321}22 23define <4 x i16> @mul4xi16(<4 x i16> %A, <4 x i16> %B) {24; CHECK-LABEL: mul4xi16:25; CHECK: // %bb.0:26; CHECK-NEXT: mul v0.4h, v0.4h, v1.4h27; CHECK-NEXT: ret28 %tmp3 = mul <4 x i16> %A, %B;29 ret <4 x i16> %tmp330}31 32define <8 x i16> @mul8xi16(<8 x i16> %A, <8 x i16> %B) {33; CHECK-LABEL: mul8xi16:34; CHECK: // %bb.0:35; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h36; CHECK-NEXT: ret37 %tmp3 = mul <8 x i16> %A, %B;38 ret <8 x i16> %tmp339}40 41define <2 x i32> @mul2xi32(<2 x i32> %A, <2 x i32> %B) {42; CHECK-LABEL: mul2xi32:43; CHECK: // %bb.0:44; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s45; CHECK-NEXT: ret46 %tmp3 = mul <2 x i32> %A, %B;47 ret <2 x i32> %tmp348}49 50define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {51; CHECK-LABEL: mul4x32:52; CHECK: // %bb.0:53; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s54; CHECK-NEXT: ret55 %tmp3 = mul <4 x i32> %A, %B;56 ret <4 x i32> %tmp357}58 59define <1 x i64> @mul1xi64(<1 x i64> %A, <1 x i64> %B) {60; CHECK-LABEL: mul1xi64:61; CHECK: // %bb.0:62; CHECK-NEXT: // kill: def $d1 killed $d1 def $q163; CHECK-NEXT: // kill: def $d0 killed $d0 def $q064; CHECK-NEXT: fmov x8, d165; CHECK-NEXT: fmov x9, d066; CHECK-NEXT: mul x8, x9, x867; CHECK-NEXT: fmov d0, x868; CHECK-NEXT: ret69 %tmp3 = mul <1 x i64> %A, %B;70 ret <1 x i64> %tmp371}72 73define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) {74; CHECK-LABEL: mul2xi64:75; CHECK: // %bb.0:76; CHECK-NEXT: fmov x10, d177; CHECK-NEXT: fmov x11, d078; CHECK-NEXT: mov x8, v1.d[1]79; CHECK-NEXT: mov x9, v0.d[1]80; CHECK-NEXT: mul x10, x11, x1081; CHECK-NEXT: mul x8, x9, x882; CHECK-NEXT: fmov d0, x1083; CHECK-NEXT: mov v0.d[1], x884; CHECK-NEXT: ret85 %tmp3 = mul <2 x i64> %A, %B;86 ret <2 x i64> %tmp387}88 89 define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {90; CHECK-LABEL: mul2xfloat:91; CHECK: // %bb.0:92; CHECK-NEXT: fmul v0.2s, v0.2s, v1.2s93; CHECK-NEXT: ret94 %tmp3 = fmul <2 x float> %A, %B;95 ret <2 x float> %tmp396}97 98define <4 x float> @mul4xfloat(<4 x float> %A, <4 x float> %B) {99; CHECK-LABEL: mul4xfloat:100; CHECK: // %bb.0:101; CHECK-NEXT: fmul v0.4s, v0.4s, v1.4s102; CHECK-NEXT: ret103 %tmp3 = fmul <4 x float> %A, %B;104 ret <4 x float> %tmp3105}106define <2 x double> @mul2xdouble(<2 x double> %A, <2 x double> %B) {107; CHECK-LABEL: mul2xdouble:108; CHECK: // %bb.0:109; CHECK-NEXT: fmul v0.2d, v0.2d, v1.2d110; CHECK-NEXT: ret111 %tmp3 = fmul <2 x double> %A, %B;112 ret <2 x double> %tmp3113}114 115 116 define <2 x float> @div2xfloat(<2 x float> %A, <2 x float> %B) {117; CHECK-LABEL: div2xfloat:118; CHECK: // %bb.0:119; CHECK-NEXT: fdiv v0.2s, v0.2s, v1.2s120; CHECK-NEXT: ret121 %tmp3 = fdiv <2 x float> %A, %B;122 ret <2 x float> %tmp3123}124 125define <4 x float> @div4xfloat(<4 x float> %A, <4 x float> %B) {126; CHECK-LABEL: div4xfloat:127; CHECK: // %bb.0:128; CHECK-NEXT: fdiv v0.4s, v0.4s, v1.4s129; CHECK-NEXT: ret130 %tmp3 = fdiv <4 x float> %A, %B;131 ret <4 x float> %tmp3132}133define <2 x double> @div2xdouble(<2 x double> %A, <2 x double> %B) {134; CHECK-LABEL: div2xdouble:135; CHECK: // %bb.0:136; CHECK-NEXT: fdiv v0.2d, v0.2d, v1.2d137; CHECK-NEXT: ret138 %tmp3 = fdiv <2 x double> %A, %B;139 ret <2 x double> %tmp3140}141 142define <1 x i8> @sdiv1x8(<1 x i8> %A, <1 x i8> %B) {143; CHECK-LABEL: sdiv1x8:144; CHECK: // %bb.0:145; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1146; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0147; CHECK-NEXT: smov w8, v1.b[0]148; CHECK-NEXT: smov w9, v0.b[0]149; CHECK-NEXT: sdiv w8, w9, w8150; CHECK-NEXT: fmov s0, w8151; CHECK-NEXT: ret152 %tmp3 = sdiv <1 x i8> %A, %B;153 ret <1 x i8> %tmp3154}155 156define <8 x i8> @sdiv8x8(<8 x i8> %A, <8 x i8> %B) {157; CHECK-LABEL: sdiv8x8:158; CHECK: // %bb.0:159; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1160; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0161; CHECK-NEXT: smov w8, v1.b[1]162; CHECK-NEXT: smov w9, v0.b[1]163; CHECK-NEXT: smov w10, v0.b[0]164; CHECK-NEXT: smov w11, v0.b[2]165; CHECK-NEXT: smov w12, v0.b[3]166; CHECK-NEXT: smov w13, v0.b[4]167; CHECK-NEXT: smov w14, v0.b[5]168; CHECK-NEXT: sdiv w8, w9, w8169; CHECK-NEXT: smov w9, v1.b[0]170; CHECK-NEXT: sdiv w9, w10, w9171; CHECK-NEXT: smov w10, v1.b[2]172; CHECK-NEXT: sdiv w10, w11, w10173; CHECK-NEXT: smov w11, v1.b[3]174; CHECK-NEXT: fmov s2, w9175; CHECK-NEXT: smov w9, v1.b[6]176; CHECK-NEXT: mov v2.b[1], w8177; CHECK-NEXT: sdiv w11, w12, w11178; CHECK-NEXT: smov w12, v1.b[4]179; CHECK-NEXT: mov v2.b[2], w10180; CHECK-NEXT: smov w10, v0.b[6]181; CHECK-NEXT: sdiv w12, w13, w12182; CHECK-NEXT: smov w13, v1.b[5]183; CHECK-NEXT: mov v2.b[3], w11184; CHECK-NEXT: smov w11, v0.b[7]185; CHECK-NEXT: sdiv w8, w14, w13186; CHECK-NEXT: mov v2.b[4], w12187; CHECK-NEXT: sdiv w9, w10, w9188; CHECK-NEXT: smov w10, v1.b[7]189; CHECK-NEXT: mov v2.b[5], w8190; CHECK-NEXT: sdiv w8, w11, w10191; CHECK-NEXT: mov v2.b[6], w9192; CHECK-NEXT: mov v2.b[7], w8193; CHECK-NEXT: fmov d0, d2194; CHECK-NEXT: ret195 %tmp3 = sdiv <8 x i8> %A, %B;196 ret <8 x i8> %tmp3197}198 199define <16 x i8> @sdiv16x8(<16 x i8> %A, <16 x i8> %B) {200; CHECK-LABEL: sdiv16x8:201; CHECK: // %bb.0:202; CHECK-NEXT: smov w8, v1.b[1]203; CHECK-NEXT: smov w9, v0.b[1]204; CHECK-NEXT: smov w10, v0.b[0]205; CHECK-NEXT: smov w11, v0.b[2]206; CHECK-NEXT: smov w12, v0.b[3]207; CHECK-NEXT: smov w13, v0.b[4]208; CHECK-NEXT: smov w14, v0.b[5]209; CHECK-NEXT: smov w15, v0.b[6]210; CHECK-NEXT: smov w16, v0.b[7]211; CHECK-NEXT: smov w17, v0.b[8]212; CHECK-NEXT: smov w18, v0.b[9]213; CHECK-NEXT: sdiv w8, w9, w8214; CHECK-NEXT: smov w9, v1.b[0]215; CHECK-NEXT: sdiv w9, w10, w9216; CHECK-NEXT: smov w10, v1.b[2]217; CHECK-NEXT: sdiv w10, w11, w10218; CHECK-NEXT: smov w11, v1.b[3]219; CHECK-NEXT: fmov s2, w9220; CHECK-NEXT: smov w9, v1.b[10]221; CHECK-NEXT: mov v2.b[1], w8222; CHECK-NEXT: sdiv w11, w12, w11223; CHECK-NEXT: smov w12, v1.b[4]224; CHECK-NEXT: mov v2.b[2], w10225; CHECK-NEXT: smov w10, v0.b[10]226; CHECK-NEXT: sdiv w12, w13, w12227; CHECK-NEXT: smov w13, v1.b[5]228; CHECK-NEXT: mov v2.b[3], w11229; CHECK-NEXT: smov w11, v0.b[11]230; CHECK-NEXT: sdiv w13, w14, w13231; CHECK-NEXT: smov w14, v1.b[6]232; CHECK-NEXT: mov v2.b[4], w12233; CHECK-NEXT: smov w12, v0.b[12]234; CHECK-NEXT: sdiv w14, w15, w14235; CHECK-NEXT: smov w15, v1.b[7]236; CHECK-NEXT: mov v2.b[5], w13237; CHECK-NEXT: smov w13, v0.b[13]238; CHECK-NEXT: sdiv w15, w16, w15239; CHECK-NEXT: smov w16, v1.b[8]240; CHECK-NEXT: mov v2.b[6], w14241; CHECK-NEXT: sdiv w16, w17, w16242; CHECK-NEXT: smov w17, v1.b[9]243; CHECK-NEXT: mov v2.b[7], w15244; CHECK-NEXT: sdiv w8, w18, w17245; CHECK-NEXT: mov v2.b[8], w16246; CHECK-NEXT: sdiv w9, w10, w9247; CHECK-NEXT: smov w10, v1.b[11]248; CHECK-NEXT: mov v2.b[9], w8249; CHECK-NEXT: sdiv w10, w11, w10250; CHECK-NEXT: smov w11, v1.b[12]251; CHECK-NEXT: mov v2.b[10], w9252; CHECK-NEXT: smov w9, v1.b[14]253; CHECK-NEXT: sdiv w11, w12, w11254; CHECK-NEXT: smov w12, v1.b[13]255; CHECK-NEXT: mov v2.b[11], w10256; CHECK-NEXT: smov w10, v1.b[15]257; CHECK-NEXT: sdiv w8, w13, w12258; CHECK-NEXT: smov w12, v0.b[14]259; CHECK-NEXT: mov v2.b[12], w11260; CHECK-NEXT: smov w11, v0.b[15]261; CHECK-NEXT: sdiv w9, w12, w9262; CHECK-NEXT: mov v2.b[13], w8263; CHECK-NEXT: sdiv w8, w11, w10264; CHECK-NEXT: mov v2.b[14], w9265; CHECK-NEXT: mov v2.b[15], w8266; CHECK-NEXT: mov v0.16b, v2.16b267; CHECK-NEXT: ret268 %tmp3 = sdiv <16 x i8> %A, %B;269 ret <16 x i8> %tmp3270}271 272define <1 x i16> @sdiv1x16(<1 x i16> %A, <1 x i16> %B) {273; CHECK-LABEL: sdiv1x16:274; CHECK: // %bb.0:275; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1276; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0277; CHECK-NEXT: smov w8, v1.h[0]278; CHECK-NEXT: smov w9, v0.h[0]279; CHECK-NEXT: sdiv w8, w9, w8280; CHECK-NEXT: fmov s0, w8281; CHECK-NEXT: ret282 %tmp3 = sdiv <1 x i16> %A, %B;283 ret <1 x i16> %tmp3284}285 286define <4 x i16> @sdiv4x16(<4 x i16> %A, <4 x i16> %B) {287; CHECK-LABEL: sdiv4x16:288; CHECK: // %bb.0:289; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1290; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0291; CHECK-NEXT: smov w8, v1.h[1]292; CHECK-NEXT: smov w9, v0.h[1]293; CHECK-NEXT: smov w10, v0.h[0]294; CHECK-NEXT: smov w11, v0.h[2]295; CHECK-NEXT: smov w12, v0.h[3]296; CHECK-NEXT: sdiv w8, w9, w8297; CHECK-NEXT: smov w9, v1.h[0]298; CHECK-NEXT: sdiv w9, w10, w9299; CHECK-NEXT: smov w10, v1.h[2]300; CHECK-NEXT: sdiv w10, w11, w10301; CHECK-NEXT: smov w11, v1.h[3]302; CHECK-NEXT: fmov s0, w9303; CHECK-NEXT: mov v0.h[1], w8304; CHECK-NEXT: sdiv w8, w12, w11305; CHECK-NEXT: mov v0.h[2], w10306; CHECK-NEXT: mov v0.h[3], w8307; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0308; CHECK-NEXT: ret309 %tmp3 = sdiv <4 x i16> %A, %B;310 ret <4 x i16> %tmp3311}312 313define <8 x i16> @sdiv8x16(<8 x i16> %A, <8 x i16> %B) {314; CHECK-LABEL: sdiv8x16:315; CHECK: // %bb.0:316; CHECK-NEXT: smov w8, v1.h[1]317; CHECK-NEXT: smov w9, v0.h[1]318; CHECK-NEXT: smov w10, v0.h[0]319; CHECK-NEXT: smov w11, v0.h[2]320; CHECK-NEXT: smov w12, v0.h[3]321; CHECK-NEXT: smov w13, v0.h[4]322; CHECK-NEXT: smov w14, v0.h[5]323; CHECK-NEXT: sdiv w8, w9, w8324; CHECK-NEXT: smov w9, v1.h[0]325; CHECK-NEXT: sdiv w9, w10, w9326; CHECK-NEXT: smov w10, v1.h[2]327; CHECK-NEXT: sdiv w10, w11, w10328; CHECK-NEXT: smov w11, v1.h[3]329; CHECK-NEXT: fmov s2, w9330; CHECK-NEXT: smov w9, v1.h[6]331; CHECK-NEXT: mov v2.h[1], w8332; CHECK-NEXT: sdiv w11, w12, w11333; CHECK-NEXT: smov w12, v1.h[4]334; CHECK-NEXT: mov v2.h[2], w10335; CHECK-NEXT: smov w10, v0.h[6]336; CHECK-NEXT: sdiv w12, w13, w12337; CHECK-NEXT: smov w13, v1.h[5]338; CHECK-NEXT: mov v2.h[3], w11339; CHECK-NEXT: smov w11, v0.h[7]340; CHECK-NEXT: sdiv w8, w14, w13341; CHECK-NEXT: mov v2.h[4], w12342; CHECK-NEXT: sdiv w9, w10, w9343; CHECK-NEXT: smov w10, v1.h[7]344; CHECK-NEXT: mov v2.h[5], w8345; CHECK-NEXT: sdiv w8, w11, w10346; CHECK-NEXT: mov v2.h[6], w9347; CHECK-NEXT: mov v2.h[7], w8348; CHECK-NEXT: mov v0.16b, v2.16b349; CHECK-NEXT: ret350 %tmp3 = sdiv <8 x i16> %A, %B;351 ret <8 x i16> %tmp3352}353 354define <1 x i32> @sdiv1x32(<1 x i32> %A, <1 x i32> %B) {355; CHECK-LABEL: sdiv1x32:356; CHECK: // %bb.0:357; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1358; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0359; CHECK-NEXT: fmov w8, s1360; CHECK-NEXT: fmov w9, s0361; CHECK-NEXT: sdiv w8, w9, w8362; CHECK-NEXT: fmov s0, w8363; CHECK-NEXT: ret364 %tmp3 = sdiv <1 x i32> %A, %B;365 ret <1 x i32> %tmp3366}367 368define <2 x i32> @sdiv2x32(<2 x i32> %A, <2 x i32> %B) {369; CHECK-LABEL: sdiv2x32:370; CHECK: // %bb.0:371; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1372; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0373; CHECK-NEXT: fmov w8, s1374; CHECK-NEXT: fmov w9, s0375; CHECK-NEXT: mov w10, v0.s[1]376; CHECK-NEXT: sdiv w8, w9, w8377; CHECK-NEXT: mov w9, v1.s[1]378; CHECK-NEXT: sdiv w9, w10, w9379; CHECK-NEXT: fmov s0, w8380; CHECK-NEXT: mov v0.s[1], w9381; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0382; CHECK-NEXT: ret383 %tmp3 = sdiv <2 x i32> %A, %B;384 ret <2 x i32> %tmp3385}386 387define <4 x i32> @sdiv4x32(<4 x i32> %A, <4 x i32> %B) {388; CHECK-LABEL: sdiv4x32:389; CHECK: // %bb.0:390; CHECK-NEXT: mov w8, v1.s[1]391; CHECK-NEXT: mov w9, v0.s[1]392; CHECK-NEXT: fmov w10, s0393; CHECK-NEXT: mov w11, v0.s[2]394; CHECK-NEXT: mov w12, v0.s[3]395; CHECK-NEXT: sdiv w8, w9, w8396; CHECK-NEXT: fmov w9, s1397; CHECK-NEXT: sdiv w9, w10, w9398; CHECK-NEXT: mov w10, v1.s[2]399; CHECK-NEXT: sdiv w10, w11, w10400; CHECK-NEXT: mov w11, v1.s[3]401; CHECK-NEXT: fmov s0, w9402; CHECK-NEXT: mov v0.s[1], w8403; CHECK-NEXT: sdiv w8, w12, w11404; CHECK-NEXT: mov v0.s[2], w10405; CHECK-NEXT: mov v0.s[3], w8406; CHECK-NEXT: ret407 %tmp3 = sdiv <4 x i32> %A, %B;408 ret <4 x i32> %tmp3409}410 411define <1 x i64> @sdiv1x64(<1 x i64> %A, <1 x i64> %B) {412; CHECK-LABEL: sdiv1x64:413; CHECK: // %bb.0:414; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1415; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0416; CHECK-NEXT: fmov x8, d1417; CHECK-NEXT: fmov x9, d0418; CHECK-NEXT: sdiv x8, x9, x8419; CHECK-NEXT: fmov d0, x8420; CHECK-NEXT: ret421 %tmp3 = sdiv <1 x i64> %A, %B;422 ret <1 x i64> %tmp3423}424 425define <2 x i64> @sdiv2x64(<2 x i64> %A, <2 x i64> %B) {426; CHECK-LABEL: sdiv2x64:427; CHECK: // %bb.0:428; CHECK-NEXT: fmov x8, d1429; CHECK-NEXT: fmov x9, d0430; CHECK-NEXT: mov x10, v0.d[1]431; CHECK-NEXT: sdiv x8, x9, x8432; CHECK-NEXT: mov x9, v1.d[1]433; CHECK-NEXT: sdiv x9, x10, x9434; CHECK-NEXT: fmov d0, x8435; CHECK-NEXT: mov v0.d[1], x9436; CHECK-NEXT: ret437 %tmp3 = sdiv <2 x i64> %A, %B;438 ret <2 x i64> %tmp3439}440 441define <1 x i8> @udiv1x8(<1 x i8> %A, <1 x i8> %B) {442; CHECK-LABEL: udiv1x8:443; CHECK: // %bb.0:444; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1445; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0446; CHECK-NEXT: umov w8, v1.b[0]447; CHECK-NEXT: umov w9, v0.b[0]448; CHECK-NEXT: udiv w8, w9, w8449; CHECK-NEXT: fmov s0, w8450; CHECK-NEXT: ret451 %tmp3 = udiv <1 x i8> %A, %B;452 ret <1 x i8> %tmp3453}454 455define <8 x i8> @udiv8x8(<8 x i8> %A, <8 x i8> %B) {456; CHECK-LABEL: udiv8x8:457; CHECK: // %bb.0:458; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1459; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0460; CHECK-NEXT: umov w8, v1.b[1]461; CHECK-NEXT: umov w9, v0.b[1]462; CHECK-NEXT: umov w10, v0.b[0]463; CHECK-NEXT: umov w11, v0.b[2]464; CHECK-NEXT: umov w12, v0.b[3]465; CHECK-NEXT: umov w13, v0.b[4]466; CHECK-NEXT: umov w14, v0.b[5]467; CHECK-NEXT: udiv w8, w9, w8468; CHECK-NEXT: umov w9, v1.b[0]469; CHECK-NEXT: udiv w9, w10, w9470; CHECK-NEXT: umov w10, v1.b[2]471; CHECK-NEXT: udiv w10, w11, w10472; CHECK-NEXT: umov w11, v1.b[3]473; CHECK-NEXT: fmov s2, w9474; CHECK-NEXT: umov w9, v1.b[6]475; CHECK-NEXT: mov v2.b[1], w8476; CHECK-NEXT: udiv w11, w12, w11477; CHECK-NEXT: umov w12, v1.b[4]478; CHECK-NEXT: mov v2.b[2], w10479; CHECK-NEXT: umov w10, v0.b[6]480; CHECK-NEXT: udiv w12, w13, w12481; CHECK-NEXT: umov w13, v1.b[5]482; CHECK-NEXT: mov v2.b[3], w11483; CHECK-NEXT: umov w11, v0.b[7]484; CHECK-NEXT: udiv w8, w14, w13485; CHECK-NEXT: mov v2.b[4], w12486; CHECK-NEXT: udiv w9, w10, w9487; CHECK-NEXT: umov w10, v1.b[7]488; CHECK-NEXT: mov v2.b[5], w8489; CHECK-NEXT: udiv w8, w11, w10490; CHECK-NEXT: mov v2.b[6], w9491; CHECK-NEXT: mov v2.b[7], w8492; CHECK-NEXT: fmov d0, d2493; CHECK-NEXT: ret494 %tmp3 = udiv <8 x i8> %A, %B;495 ret <8 x i8> %tmp3496}497 498define <16 x i8> @udiv16x8(<16 x i8> %A, <16 x i8> %B) {499; CHECK-LABEL: udiv16x8:500; CHECK: // %bb.0:501; CHECK-NEXT: umov w8, v1.b[1]502; CHECK-NEXT: umov w9, v0.b[1]503; CHECK-NEXT: umov w10, v0.b[0]504; CHECK-NEXT: umov w11, v0.b[2]505; CHECK-NEXT: umov w12, v0.b[3]506; CHECK-NEXT: umov w13, v0.b[4]507; CHECK-NEXT: umov w14, v0.b[5]508; CHECK-NEXT: umov w15, v0.b[6]509; CHECK-NEXT: umov w16, v0.b[7]510; CHECK-NEXT: umov w17, v0.b[8]511; CHECK-NEXT: umov w18, v0.b[9]512; CHECK-NEXT: udiv w8, w9, w8513; CHECK-NEXT: umov w9, v1.b[0]514; CHECK-NEXT: udiv w9, w10, w9515; CHECK-NEXT: umov w10, v1.b[2]516; CHECK-NEXT: udiv w10, w11, w10517; CHECK-NEXT: umov w11, v1.b[3]518; CHECK-NEXT: fmov s2, w9519; CHECK-NEXT: umov w9, v1.b[10]520; CHECK-NEXT: mov v2.b[1], w8521; CHECK-NEXT: udiv w11, w12, w11522; CHECK-NEXT: umov w12, v1.b[4]523; CHECK-NEXT: mov v2.b[2], w10524; CHECK-NEXT: umov w10, v0.b[10]525; CHECK-NEXT: udiv w12, w13, w12526; CHECK-NEXT: umov w13, v1.b[5]527; CHECK-NEXT: mov v2.b[3], w11528; CHECK-NEXT: umov w11, v0.b[11]529; CHECK-NEXT: udiv w13, w14, w13530; CHECK-NEXT: umov w14, v1.b[6]531; CHECK-NEXT: mov v2.b[4], w12532; CHECK-NEXT: umov w12, v0.b[12]533; CHECK-NEXT: udiv w14, w15, w14534; CHECK-NEXT: umov w15, v1.b[7]535; CHECK-NEXT: mov v2.b[5], w13536; CHECK-NEXT: umov w13, v0.b[13]537; CHECK-NEXT: udiv w15, w16, w15538; CHECK-NEXT: umov w16, v1.b[8]539; CHECK-NEXT: mov v2.b[6], w14540; CHECK-NEXT: udiv w16, w17, w16541; CHECK-NEXT: umov w17, v1.b[9]542; CHECK-NEXT: mov v2.b[7], w15543; CHECK-NEXT: udiv w8, w18, w17544; CHECK-NEXT: mov v2.b[8], w16545; CHECK-NEXT: udiv w9, w10, w9546; CHECK-NEXT: umov w10, v1.b[11]547; CHECK-NEXT: mov v2.b[9], w8548; CHECK-NEXT: udiv w10, w11, w10549; CHECK-NEXT: umov w11, v1.b[12]550; CHECK-NEXT: mov v2.b[10], w9551; CHECK-NEXT: umov w9, v1.b[14]552; CHECK-NEXT: udiv w11, w12, w11553; CHECK-NEXT: umov w12, v1.b[13]554; CHECK-NEXT: mov v2.b[11], w10555; CHECK-NEXT: umov w10, v1.b[15]556; CHECK-NEXT: udiv w8, w13, w12557; CHECK-NEXT: umov w12, v0.b[14]558; CHECK-NEXT: mov v2.b[12], w11559; CHECK-NEXT: umov w11, v0.b[15]560; CHECK-NEXT: udiv w9, w12, w9561; CHECK-NEXT: mov v2.b[13], w8562; CHECK-NEXT: udiv w8, w11, w10563; CHECK-NEXT: mov v2.b[14], w9564; CHECK-NEXT: mov v2.b[15], w8565; CHECK-NEXT: mov v0.16b, v2.16b566; CHECK-NEXT: ret567 %tmp3 = udiv <16 x i8> %A, %B;568 ret <16 x i8> %tmp3569}570 571define <1 x i16> @udiv1x16(<1 x i16> %A, <1 x i16> %B) {572; CHECK-LABEL: udiv1x16:573; CHECK: // %bb.0:574; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1575; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0576; CHECK-NEXT: umov w8, v1.h[0]577; CHECK-NEXT: umov w9, v0.h[0]578; CHECK-NEXT: udiv w8, w9, w8579; CHECK-NEXT: fmov s0, w8580; CHECK-NEXT: ret581 %tmp3 = udiv <1 x i16> %A, %B;582 ret <1 x i16> %tmp3583}584 585define <4 x i16> @udiv4x16(<4 x i16> %A, <4 x i16> %B) {586; CHECK-LABEL: udiv4x16:587; CHECK: // %bb.0:588; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1589; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0590; CHECK-NEXT: umov w8, v1.h[1]591; CHECK-NEXT: umov w9, v0.h[1]592; CHECK-NEXT: umov w10, v0.h[0]593; CHECK-NEXT: umov w11, v0.h[2]594; CHECK-NEXT: umov w12, v0.h[3]595; CHECK-NEXT: udiv w8, w9, w8596; CHECK-NEXT: umov w9, v1.h[0]597; CHECK-NEXT: udiv w9, w10, w9598; CHECK-NEXT: umov w10, v1.h[2]599; CHECK-NEXT: udiv w10, w11, w10600; CHECK-NEXT: umov w11, v1.h[3]601; CHECK-NEXT: fmov s0, w9602; CHECK-NEXT: mov v0.h[1], w8603; CHECK-NEXT: udiv w8, w12, w11604; CHECK-NEXT: mov v0.h[2], w10605; CHECK-NEXT: mov v0.h[3], w8606; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0607; CHECK-NEXT: ret608 %tmp3 = udiv <4 x i16> %A, %B;609 ret <4 x i16> %tmp3610}611 612define <8 x i16> @udiv8x16(<8 x i16> %A, <8 x i16> %B) {613; CHECK-LABEL: udiv8x16:614; CHECK: // %bb.0:615; CHECK-NEXT: umov w8, v1.h[1]616; CHECK-NEXT: umov w9, v0.h[1]617; CHECK-NEXT: umov w10, v0.h[0]618; CHECK-NEXT: umov w11, v0.h[2]619; CHECK-NEXT: umov w12, v0.h[3]620; CHECK-NEXT: umov w13, v0.h[4]621; CHECK-NEXT: umov w14, v0.h[5]622; CHECK-NEXT: udiv w8, w9, w8623; CHECK-NEXT: umov w9, v1.h[0]624; CHECK-NEXT: udiv w9, w10, w9625; CHECK-NEXT: umov w10, v1.h[2]626; CHECK-NEXT: udiv w10, w11, w10627; CHECK-NEXT: umov w11, v1.h[3]628; CHECK-NEXT: fmov s2, w9629; CHECK-NEXT: umov w9, v1.h[6]630; CHECK-NEXT: mov v2.h[1], w8631; CHECK-NEXT: udiv w11, w12, w11632; CHECK-NEXT: umov w12, v1.h[4]633; CHECK-NEXT: mov v2.h[2], w10634; CHECK-NEXT: umov w10, v0.h[6]635; CHECK-NEXT: udiv w12, w13, w12636; CHECK-NEXT: umov w13, v1.h[5]637; CHECK-NEXT: mov v2.h[3], w11638; CHECK-NEXT: umov w11, v0.h[7]639; CHECK-NEXT: udiv w8, w14, w13640; CHECK-NEXT: mov v2.h[4], w12641; CHECK-NEXT: udiv w9, w10, w9642; CHECK-NEXT: umov w10, v1.h[7]643; CHECK-NEXT: mov v2.h[5], w8644; CHECK-NEXT: udiv w8, w11, w10645; CHECK-NEXT: mov v2.h[6], w9646; CHECK-NEXT: mov v2.h[7], w8647; CHECK-NEXT: mov v0.16b, v2.16b648; CHECK-NEXT: ret649 %tmp3 = udiv <8 x i16> %A, %B;650 ret <8 x i16> %tmp3651}652 653define <1 x i32> @udiv1x32(<1 x i32> %A, <1 x i32> %B) {654; CHECK-LABEL: udiv1x32:655; CHECK: // %bb.0:656; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1657; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0658; CHECK-NEXT: fmov w8, s1659; CHECK-NEXT: fmov w9, s0660; CHECK-NEXT: udiv w8, w9, w8661; CHECK-NEXT: fmov s0, w8662; CHECK-NEXT: ret663 %tmp3 = udiv <1 x i32> %A, %B;664 ret <1 x i32> %tmp3665}666 667define <2 x i32> @udiv2x32(<2 x i32> %A, <2 x i32> %B) {668; CHECK-LABEL: udiv2x32:669; CHECK: // %bb.0:670; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1671; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0672; CHECK-NEXT: fmov w8, s1673; CHECK-NEXT: fmov w9, s0674; CHECK-NEXT: mov w10, v0.s[1]675; CHECK-NEXT: udiv w8, w9, w8676; CHECK-NEXT: mov w9, v1.s[1]677; CHECK-NEXT: udiv w9, w10, w9678; CHECK-NEXT: fmov s0, w8679; CHECK-NEXT: mov v0.s[1], w9680; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0681; CHECK-NEXT: ret682 %tmp3 = udiv <2 x i32> %A, %B;683 ret <2 x i32> %tmp3684}685 686define <4 x i32> @udiv4x32(<4 x i32> %A, <4 x i32> %B) {687; CHECK-LABEL: udiv4x32:688; CHECK: // %bb.0:689; CHECK-NEXT: mov w8, v1.s[1]690; CHECK-NEXT: mov w9, v0.s[1]691; CHECK-NEXT: fmov w10, s0692; CHECK-NEXT: mov w11, v0.s[2]693; CHECK-NEXT: mov w12, v0.s[3]694; CHECK-NEXT: udiv w8, w9, w8695; CHECK-NEXT: fmov w9, s1696; CHECK-NEXT: udiv w9, w10, w9697; CHECK-NEXT: mov w10, v1.s[2]698; CHECK-NEXT: udiv w10, w11, w10699; CHECK-NEXT: mov w11, v1.s[3]700; CHECK-NEXT: fmov s0, w9701; CHECK-NEXT: mov v0.s[1], w8702; CHECK-NEXT: udiv w8, w12, w11703; CHECK-NEXT: mov v0.s[2], w10704; CHECK-NEXT: mov v0.s[3], w8705; CHECK-NEXT: ret706 %tmp3 = udiv <4 x i32> %A, %B;707 ret <4 x i32> %tmp3708}709 710define <1 x i64> @udiv1x64(<1 x i64> %A, <1 x i64> %B) {711; CHECK-LABEL: udiv1x64:712; CHECK: // %bb.0:713; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1714; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0715; CHECK-NEXT: fmov x8, d1716; CHECK-NEXT: fmov x9, d0717; CHECK-NEXT: udiv x8, x9, x8718; CHECK-NEXT: fmov d0, x8719; CHECK-NEXT: ret720 %tmp3 = udiv <1 x i64> %A, %B;721 ret <1 x i64> %tmp3722}723 724define <2 x i64> @udiv2x64(<2 x i64> %A, <2 x i64> %B) {725; CHECK-LABEL: udiv2x64:726; CHECK: // %bb.0:727; CHECK-NEXT: fmov x8, d1728; CHECK-NEXT: fmov x9, d0729; CHECK-NEXT: mov x10, v0.d[1]730; CHECK-NEXT: udiv x8, x9, x8731; CHECK-NEXT: mov x9, v1.d[1]732; CHECK-NEXT: udiv x9, x10, x9733; CHECK-NEXT: fmov d0, x8734; CHECK-NEXT: mov v0.d[1], x9735; CHECK-NEXT: ret736 %tmp3 = udiv <2 x i64> %A, %B;737 ret <2 x i64> %tmp3738}739 740define <1 x i8> @srem1x8(<1 x i8> %A, <1 x i8> %B) {741; CHECK-LABEL: srem1x8:742; CHECK: // %bb.0:743; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1744; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0745; CHECK-NEXT: smov w8, v1.b[0]746; CHECK-NEXT: smov w9, v0.b[0]747; CHECK-NEXT: sdiv w10, w9, w8748; CHECK-NEXT: msub w8, w10, w8, w9749; CHECK-NEXT: fmov s0, w8750; CHECK-NEXT: ret751 %tmp3 = srem <1 x i8> %A, %B;752 ret <1 x i8> %tmp3753}754 755define <8 x i8> @srem8x8(<8 x i8> %A, <8 x i8> %B) {756; CHECK-LABEL: srem8x8:757; CHECK: // %bb.0:758; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1759; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0760; CHECK-NEXT: smov w11, v1.b[0]761; CHECK-NEXT: smov w12, v0.b[0]762; CHECK-NEXT: smov w8, v1.b[1]763; CHECK-NEXT: smov w9, v0.b[1]764; CHECK-NEXT: smov w14, v1.b[2]765; CHECK-NEXT: smov w15, v0.b[2]766; CHECK-NEXT: smov w17, v1.b[3]767; CHECK-NEXT: smov w18, v0.b[3]768; CHECK-NEXT: smov w1, v1.b[4]769; CHECK-NEXT: smov w2, v0.b[4]770; CHECK-NEXT: smov w4, v1.b[5]771; CHECK-NEXT: smov w5, v0.b[5]772; CHECK-NEXT: sdiv w13, w12, w11773; CHECK-NEXT: sdiv w10, w9, w8774; CHECK-NEXT: msub w11, w13, w11, w12775; CHECK-NEXT: smov w13, v1.b[7]776; CHECK-NEXT: fmov s2, w11777; CHECK-NEXT: smov w11, v0.b[6]778; CHECK-NEXT: sdiv w16, w15, w14779; CHECK-NEXT: msub w8, w10, w8, w9780; CHECK-NEXT: smov w10, v1.b[6]781; CHECK-NEXT: mov v2.b[1], w8782; CHECK-NEXT: sdiv w0, w18, w17783; CHECK-NEXT: msub w8, w16, w14, w15784; CHECK-NEXT: smov w14, v0.b[7]785; CHECK-NEXT: mov v2.b[2], w8786; CHECK-NEXT: sdiv w3, w2, w1787; CHECK-NEXT: msub w8, w0, w17, w18788; CHECK-NEXT: mov v2.b[3], w8789; CHECK-NEXT: sdiv w9, w5, w4790; CHECK-NEXT: msub w8, w3, w1, w2791; CHECK-NEXT: mov v2.b[4], w8792; CHECK-NEXT: sdiv w12, w11, w10793; CHECK-NEXT: msub w8, w9, w4, w5794; CHECK-NEXT: mov v2.b[5], w8795; CHECK-NEXT: sdiv w9, w14, w13796; CHECK-NEXT: msub w8, w12, w10, w11797; CHECK-NEXT: mov v2.b[6], w8798; CHECK-NEXT: msub w8, w9, w13, w14799; CHECK-NEXT: mov v2.b[7], w8800; CHECK-NEXT: fmov d0, d2801; CHECK-NEXT: ret802 %tmp3 = srem <8 x i8> %A, %B;803 ret <8 x i8> %tmp3804}805 806define <16 x i8> @srem16x8(<16 x i8> %A, <16 x i8> %B) {807; CHECK-LABEL: srem16x8:808; CHECK: // %bb.0:809; CHECK-NEXT: stp x28, x27, [sp, #-80]! // 16-byte Folded Spill810; CHECK-NEXT: stp x26, x25, [sp, #16] // 16-byte Folded Spill811; CHECK-NEXT: stp x24, x23, [sp, #32] // 16-byte Folded Spill812; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill813; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill814; CHECK-NEXT: .cfi_def_cfa_offset 80815; CHECK-NEXT: .cfi_offset w19, -8816; CHECK-NEXT: .cfi_offset w20, -16817; CHECK-NEXT: .cfi_offset w21, -24818; CHECK-NEXT: .cfi_offset w22, -32819; CHECK-NEXT: .cfi_offset w23, -40820; CHECK-NEXT: .cfi_offset w24, -48821; CHECK-NEXT: .cfi_offset w25, -56822; CHECK-NEXT: .cfi_offset w26, -64823; CHECK-NEXT: .cfi_offset w27, -72824; CHECK-NEXT: .cfi_offset w28, -80825; CHECK-NEXT: smov w11, v1.b[0]826; CHECK-NEXT: smov w12, v0.b[0]827; CHECK-NEXT: smov w8, v1.b[1]828; CHECK-NEXT: smov w9, v0.b[1]829; CHECK-NEXT: smov w14, v1.b[2]830; CHECK-NEXT: smov w15, v0.b[2]831; CHECK-NEXT: smov w17, v1.b[3]832; CHECK-NEXT: smov w18, v0.b[3]833; CHECK-NEXT: smov w1, v1.b[4]834; CHECK-NEXT: smov w2, v0.b[4]835; CHECK-NEXT: smov w4, v1.b[5]836; CHECK-NEXT: smov w5, v0.b[5]837; CHECK-NEXT: sdiv w13, w12, w11838; CHECK-NEXT: smov w7, v1.b[6]839; CHECK-NEXT: smov w19, v0.b[6]840; CHECK-NEXT: smov w21, v1.b[7]841; CHECK-NEXT: smov w22, v0.b[7]842; CHECK-NEXT: smov w24, v1.b[8]843; CHECK-NEXT: smov w25, v0.b[8]844; CHECK-NEXT: smov w27, v1.b[9]845; CHECK-NEXT: smov w28, v0.b[9]846; CHECK-NEXT: sdiv w10, w9, w8847; CHECK-NEXT: msub w11, w13, w11, w12848; CHECK-NEXT: smov w13, v1.b[11]849; CHECK-NEXT: fmov s2, w11850; CHECK-NEXT: smov w11, v0.b[10]851; CHECK-NEXT: sdiv w16, w15, w14852; CHECK-NEXT: msub w8, w10, w8, w9853; CHECK-NEXT: smov w10, v1.b[10]854; CHECK-NEXT: mov v2.b[1], w8855; CHECK-NEXT: sdiv w0, w18, w17856; CHECK-NEXT: msub w8, w16, w14, w15857; CHECK-NEXT: smov w14, v0.b[11]858; CHECK-NEXT: smov w16, v1.b[12]859; CHECK-NEXT: mov v2.b[2], w8860; CHECK-NEXT: sdiv w3, w2, w1861; CHECK-NEXT: msub w8, w0, w17, w18862; CHECK-NEXT: smov w17, v0.b[12]863; CHECK-NEXT: smov w0, v1.b[13]864; CHECK-NEXT: mov v2.b[3], w8865; CHECK-NEXT: sdiv w6, w5, w4866; CHECK-NEXT: msub w8, w3, w1, w2867; CHECK-NEXT: smov w1, v0.b[13]868; CHECK-NEXT: mov v2.b[4], w8869; CHECK-NEXT: sdiv w20, w19, w7870; CHECK-NEXT: msub w8, w6, w4, w5871; CHECK-NEXT: mov v2.b[5], w8872; CHECK-NEXT: sdiv w23, w22, w21873; CHECK-NEXT: msub w8, w20, w7, w19874; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload875; CHECK-NEXT: mov v2.b[6], w8876; CHECK-NEXT: sdiv w26, w25, w24877; CHECK-NEXT: msub w8, w23, w21, w22878; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload879; CHECK-NEXT: mov v2.b[7], w8880; CHECK-NEXT: sdiv w9, w28, w27881; CHECK-NEXT: msub w8, w26, w24, w25882; CHECK-NEXT: ldp x24, x23, [sp, #32] // 16-byte Folded Reload883; CHECK-NEXT: ldp x26, x25, [sp, #16] // 16-byte Folded Reload884; CHECK-NEXT: mov v2.b[8], w8885; CHECK-NEXT: sdiv w12, w11, w10886; CHECK-NEXT: msub w8, w9, w27, w28887; CHECK-NEXT: mov v2.b[9], w8888; CHECK-NEXT: sdiv w15, w14, w13889; CHECK-NEXT: msub w8, w12, w10, w11890; CHECK-NEXT: smov w10, v1.b[14]891; CHECK-NEXT: smov w11, v0.b[14]892; CHECK-NEXT: mov v2.b[10], w8893; CHECK-NEXT: sdiv w18, w17, w16894; CHECK-NEXT: msub w8, w15, w13, w14895; CHECK-NEXT: smov w13, v1.b[15]896; CHECK-NEXT: smov w14, v0.b[15]897; CHECK-NEXT: mov v2.b[11], w8898; CHECK-NEXT: sdiv w9, w1, w0899; CHECK-NEXT: msub w8, w18, w16, w17900; CHECK-NEXT: mov v2.b[12], w8901; CHECK-NEXT: sdiv w12, w11, w10902; CHECK-NEXT: msub w8, w9, w0, w1903; CHECK-NEXT: mov v2.b[13], w8904; CHECK-NEXT: sdiv w9, w14, w13905; CHECK-NEXT: msub w8, w12, w10, w11906; CHECK-NEXT: mov v2.b[14], w8907; CHECK-NEXT: msub w8, w9, w13, w14908; CHECK-NEXT: mov v2.b[15], w8909; CHECK-NEXT: mov v0.16b, v2.16b910; CHECK-NEXT: ldp x28, x27, [sp], #80 // 16-byte Folded Reload911; CHECK-NEXT: ret912 %tmp3 = srem <16 x i8> %A, %B;913 ret <16 x i8> %tmp3914}915 916define <1 x i16> @srem1x16(<1 x i16> %A, <1 x i16> %B) {917; CHECK-LABEL: srem1x16:918; CHECK: // %bb.0:919; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1920; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0921; CHECK-NEXT: smov w8, v1.h[0]922; CHECK-NEXT: smov w9, v0.h[0]923; CHECK-NEXT: sdiv w10, w9, w8924; CHECK-NEXT: msub w8, w10, w8, w9925; CHECK-NEXT: fmov s0, w8926; CHECK-NEXT: ret927 %tmp3 = srem <1 x i16> %A, %B;928 ret <1 x i16> %tmp3929}930 931define <4 x i16> @srem4x16(<4 x i16> %A, <4 x i16> %B) {932; CHECK-LABEL: srem4x16:933; CHECK: // %bb.0:934; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1935; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0936; CHECK-NEXT: smov w11, v1.h[0]937; CHECK-NEXT: smov w12, v0.h[0]938; CHECK-NEXT: smov w8, v1.h[1]939; CHECK-NEXT: smov w9, v0.h[1]940; CHECK-NEXT: smov w14, v1.h[2]941; CHECK-NEXT: smov w15, v0.h[2]942; CHECK-NEXT: smov w17, v1.h[3]943; CHECK-NEXT: smov w18, v0.h[3]944; CHECK-NEXT: sdiv w13, w12, w11945; CHECK-NEXT: sdiv w10, w9, w8946; CHECK-NEXT: msub w11, w13, w11, w12947; CHECK-NEXT: fmov s0, w11948; CHECK-NEXT: sdiv w16, w15, w14949; CHECK-NEXT: msub w8, w10, w8, w9950; CHECK-NEXT: mov v0.h[1], w8951; CHECK-NEXT: sdiv w9, w18, w17952; CHECK-NEXT: msub w8, w16, w14, w15953; CHECK-NEXT: mov v0.h[2], w8954; CHECK-NEXT: msub w8, w9, w17, w18955; CHECK-NEXT: mov v0.h[3], w8956; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0957; CHECK-NEXT: ret958 %tmp3 = srem <4 x i16> %A, %B;959 ret <4 x i16> %tmp3960}961 962define <8 x i16> @srem8x16(<8 x i16> %A, <8 x i16> %B) {963; CHECK-LABEL: srem8x16:964; CHECK: // %bb.0:965; CHECK-NEXT: smov w11, v1.h[0]966; CHECK-NEXT: smov w12, v0.h[0]967; CHECK-NEXT: smov w8, v1.h[1]968; CHECK-NEXT: smov w9, v0.h[1]969; CHECK-NEXT: smov w14, v1.h[2]970; CHECK-NEXT: smov w15, v0.h[2]971; CHECK-NEXT: smov w17, v1.h[3]972; CHECK-NEXT: smov w18, v0.h[3]973; CHECK-NEXT: smov w1, v1.h[4]974; CHECK-NEXT: smov w2, v0.h[4]975; CHECK-NEXT: smov w4, v1.h[5]976; CHECK-NEXT: smov w5, v0.h[5]977; CHECK-NEXT: sdiv w13, w12, w11978; CHECK-NEXT: sdiv w10, w9, w8979; CHECK-NEXT: msub w11, w13, w11, w12980; CHECK-NEXT: smov w13, v1.h[7]981; CHECK-NEXT: fmov s2, w11982; CHECK-NEXT: smov w11, v0.h[6]983; CHECK-NEXT: sdiv w16, w15, w14984; CHECK-NEXT: msub w8, w10, w8, w9985; CHECK-NEXT: smov w10, v1.h[6]986; CHECK-NEXT: mov v2.h[1], w8987; CHECK-NEXT: sdiv w0, w18, w17988; CHECK-NEXT: msub w8, w16, w14, w15989; CHECK-NEXT: smov w14, v0.h[7]990; CHECK-NEXT: mov v2.h[2], w8991; CHECK-NEXT: sdiv w3, w2, w1992; CHECK-NEXT: msub w8, w0, w17, w18993; CHECK-NEXT: mov v2.h[3], w8994; CHECK-NEXT: sdiv w9, w5, w4995; CHECK-NEXT: msub w8, w3, w1, w2996; CHECK-NEXT: mov v2.h[4], w8997; CHECK-NEXT: sdiv w12, w11, w10998; CHECK-NEXT: msub w8, w9, w4, w5999; CHECK-NEXT: mov v2.h[5], w81000; CHECK-NEXT: sdiv w9, w14, w131001; CHECK-NEXT: msub w8, w12, w10, w111002; CHECK-NEXT: mov v2.h[6], w81003; CHECK-NEXT: msub w8, w9, w13, w141004; CHECK-NEXT: mov v2.h[7], w81005; CHECK-NEXT: mov v0.16b, v2.16b1006; CHECK-NEXT: ret1007 %tmp3 = srem <8 x i16> %A, %B;1008 ret <8 x i16> %tmp31009}1010 1011define <1 x i32> @srem1x32(<1 x i32> %A, <1 x i32> %B) {1012; CHECK-LABEL: srem1x32:1013; CHECK: // %bb.0:1014; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11015; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01016; CHECK-NEXT: fmov w8, s11017; CHECK-NEXT: fmov w9, s01018; CHECK-NEXT: sdiv w10, w9, w81019; CHECK-NEXT: msub w8, w10, w8, w91020; CHECK-NEXT: fmov s0, w81021; CHECK-NEXT: ret1022 %tmp3 = srem <1 x i32> %A, %B;1023 ret <1 x i32> %tmp31024}1025 1026define <2 x i32> @srem2x32(<2 x i32> %A, <2 x i32> %B) {1027; CHECK-LABEL: srem2x32:1028; CHECK: // %bb.0:1029; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11030; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01031; CHECK-NEXT: fmov w8, s11032; CHECK-NEXT: fmov w9, s01033; CHECK-NEXT: mov w11, v1.s[1]1034; CHECK-NEXT: mov w12, v0.s[1]1035; CHECK-NEXT: sdiv w10, w9, w81036; CHECK-NEXT: sdiv w13, w12, w111037; CHECK-NEXT: msub w8, w10, w8, w91038; CHECK-NEXT: fmov s0, w81039; CHECK-NEXT: msub w9, w13, w11, w121040; CHECK-NEXT: mov v0.s[1], w91041; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01042; CHECK-NEXT: ret1043 %tmp3 = srem <2 x i32> %A, %B;1044 ret <2 x i32> %tmp31045}1046 1047define <4 x i32> @srem4x32(<4 x i32> %A, <4 x i32> %B) {1048; CHECK-LABEL: srem4x32:1049; CHECK: // %bb.0:1050; CHECK-NEXT: fmov w11, s11051; CHECK-NEXT: fmov w12, s01052; CHECK-NEXT: mov w8, v1.s[1]1053; CHECK-NEXT: mov w9, v0.s[1]1054; CHECK-NEXT: mov w14, v1.s[2]1055; CHECK-NEXT: mov w15, v0.s[2]1056; CHECK-NEXT: mov w17, v1.s[3]1057; CHECK-NEXT: mov w18, v0.s[3]1058; CHECK-NEXT: sdiv w13, w12, w111059; CHECK-NEXT: sdiv w10, w9, w81060; CHECK-NEXT: msub w11, w13, w11, w121061; CHECK-NEXT: fmov s0, w111062; CHECK-NEXT: sdiv w16, w15, w141063; CHECK-NEXT: msub w8, w10, w8, w91064; CHECK-NEXT: mov v0.s[1], w81065; CHECK-NEXT: sdiv w9, w18, w171066; CHECK-NEXT: msub w8, w16, w14, w151067; CHECK-NEXT: mov v0.s[2], w81068; CHECK-NEXT: msub w8, w9, w17, w181069; CHECK-NEXT: mov v0.s[3], w81070; CHECK-NEXT: ret1071 %tmp3 = srem <4 x i32> %A, %B;1072 ret <4 x i32> %tmp31073}1074 1075define <1 x i64> @srem1x64(<1 x i64> %A, <1 x i64> %B) {1076; CHECK-LABEL: srem1x64:1077; CHECK: // %bb.0:1078; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11079; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01080; CHECK-NEXT: fmov x8, d11081; CHECK-NEXT: fmov x9, d01082; CHECK-NEXT: sdiv x10, x9, x81083; CHECK-NEXT: msub x8, x10, x8, x91084; CHECK-NEXT: fmov d0, x81085; CHECK-NEXT: ret1086 %tmp3 = srem <1 x i64> %A, %B;1087 ret <1 x i64> %tmp31088}1089 1090define <2 x i64> @srem2x64(<2 x i64> %A, <2 x i64> %B) {1091; CHECK-LABEL: srem2x64:1092; CHECK: // %bb.0:1093; CHECK-NEXT: fmov x8, d11094; CHECK-NEXT: fmov x9, d01095; CHECK-NEXT: mov x11, v1.d[1]1096; CHECK-NEXT: mov x12, v0.d[1]1097; CHECK-NEXT: sdiv x10, x9, x81098; CHECK-NEXT: sdiv x13, x12, x111099; CHECK-NEXT: msub x8, x10, x8, x91100; CHECK-NEXT: fmov d0, x81101; CHECK-NEXT: msub x9, x13, x11, x121102; CHECK-NEXT: mov v0.d[1], x91103; CHECK-NEXT: ret1104 %tmp3 = srem <2 x i64> %A, %B;1105 ret <2 x i64> %tmp31106}1107 1108define <1 x i8> @urem1x8(<1 x i8> %A, <1 x i8> %B) {1109; CHECK-LABEL: urem1x8:1110; CHECK: // %bb.0:1111; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11112; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01113; CHECK-NEXT: umov w8, v1.b[0]1114; CHECK-NEXT: umov w9, v0.b[0]1115; CHECK-NEXT: udiv w10, w9, w81116; CHECK-NEXT: msub w8, w10, w8, w91117; CHECK-NEXT: fmov s0, w81118; CHECK-NEXT: ret1119 %tmp3 = urem <1 x i8> %A, %B;1120 ret <1 x i8> %tmp31121}1122 1123define <8 x i8> @urem8x8(<8 x i8> %A, <8 x i8> %B) {1124; CHECK-LABEL: urem8x8:1125; CHECK: // %bb.0:1126; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11127; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01128; CHECK-NEXT: umov w11, v1.b[0]1129; CHECK-NEXT: umov w12, v0.b[0]1130; CHECK-NEXT: umov w8, v1.b[1]1131; CHECK-NEXT: umov w9, v0.b[1]1132; CHECK-NEXT: umov w14, v1.b[2]1133; CHECK-NEXT: umov w15, v0.b[2]1134; CHECK-NEXT: umov w17, v1.b[3]1135; CHECK-NEXT: umov w18, v0.b[3]1136; CHECK-NEXT: umov w1, v1.b[4]1137; CHECK-NEXT: umov w2, v0.b[4]1138; CHECK-NEXT: umov w4, v1.b[5]1139; CHECK-NEXT: umov w5, v0.b[5]1140; CHECK-NEXT: udiv w13, w12, w111141; CHECK-NEXT: udiv w10, w9, w81142; CHECK-NEXT: msub w11, w13, w11, w121143; CHECK-NEXT: umov w13, v1.b[7]1144; CHECK-NEXT: fmov s2, w111145; CHECK-NEXT: umov w11, v0.b[6]1146; CHECK-NEXT: udiv w16, w15, w141147; CHECK-NEXT: msub w8, w10, w8, w91148; CHECK-NEXT: umov w10, v1.b[6]1149; CHECK-NEXT: mov v2.b[1], w81150; CHECK-NEXT: udiv w0, w18, w171151; CHECK-NEXT: msub w8, w16, w14, w151152; CHECK-NEXT: umov w14, v0.b[7]1153; CHECK-NEXT: mov v2.b[2], w81154; CHECK-NEXT: udiv w3, w2, w11155; CHECK-NEXT: msub w8, w0, w17, w181156; CHECK-NEXT: mov v2.b[3], w81157; CHECK-NEXT: udiv w9, w5, w41158; CHECK-NEXT: msub w8, w3, w1, w21159; CHECK-NEXT: mov v2.b[4], w81160; CHECK-NEXT: udiv w12, w11, w101161; CHECK-NEXT: msub w8, w9, w4, w51162; CHECK-NEXT: mov v2.b[5], w81163; CHECK-NEXT: udiv w9, w14, w131164; CHECK-NEXT: msub w8, w12, w10, w111165; CHECK-NEXT: mov v2.b[6], w81166; CHECK-NEXT: msub w8, w9, w13, w141167; CHECK-NEXT: mov v2.b[7], w81168; CHECK-NEXT: fmov d0, d21169; CHECK-NEXT: ret1170 %tmp3 = urem <8 x i8> %A, %B;1171 ret <8 x i8> %tmp31172}1173 1174define <16 x i8> @urem16x8(<16 x i8> %A, <16 x i8> %B) {1175; CHECK-LABEL: urem16x8:1176; CHECK: // %bb.0:1177; CHECK-NEXT: stp x28, x27, [sp, #-80]! // 16-byte Folded Spill1178; CHECK-NEXT: stp x26, x25, [sp, #16] // 16-byte Folded Spill1179; CHECK-NEXT: stp x24, x23, [sp, #32] // 16-byte Folded Spill1180; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill1181; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill1182; CHECK-NEXT: .cfi_def_cfa_offset 801183; CHECK-NEXT: .cfi_offset w19, -81184; CHECK-NEXT: .cfi_offset w20, -161185; CHECK-NEXT: .cfi_offset w21, -241186; CHECK-NEXT: .cfi_offset w22, -321187; CHECK-NEXT: .cfi_offset w23, -401188; CHECK-NEXT: .cfi_offset w24, -481189; CHECK-NEXT: .cfi_offset w25, -561190; CHECK-NEXT: .cfi_offset w26, -641191; CHECK-NEXT: .cfi_offset w27, -721192; CHECK-NEXT: .cfi_offset w28, -801193; CHECK-NEXT: umov w11, v1.b[0]1194; CHECK-NEXT: umov w12, v0.b[0]1195; CHECK-NEXT: umov w8, v1.b[1]1196; CHECK-NEXT: umov w9, v0.b[1]1197; CHECK-NEXT: umov w14, v1.b[2]1198; CHECK-NEXT: umov w15, v0.b[2]1199; CHECK-NEXT: umov w17, v1.b[3]1200; CHECK-NEXT: umov w18, v0.b[3]1201; CHECK-NEXT: umov w1, v1.b[4]1202; CHECK-NEXT: umov w2, v0.b[4]1203; CHECK-NEXT: umov w4, v1.b[5]1204; CHECK-NEXT: umov w5, v0.b[5]1205; CHECK-NEXT: udiv w13, w12, w111206; CHECK-NEXT: umov w7, v1.b[6]1207; CHECK-NEXT: umov w19, v0.b[6]1208; CHECK-NEXT: umov w21, v1.b[7]1209; CHECK-NEXT: umov w22, v0.b[7]1210; CHECK-NEXT: umov w24, v1.b[8]1211; CHECK-NEXT: umov w25, v0.b[8]1212; CHECK-NEXT: umov w27, v1.b[9]1213; CHECK-NEXT: umov w28, v0.b[9]1214; CHECK-NEXT: udiv w10, w9, w81215; CHECK-NEXT: msub w11, w13, w11, w121216; CHECK-NEXT: umov w13, v1.b[11]1217; CHECK-NEXT: fmov s2, w111218; CHECK-NEXT: umov w11, v0.b[10]1219; CHECK-NEXT: udiv w16, w15, w141220; CHECK-NEXT: msub w8, w10, w8, w91221; CHECK-NEXT: umov w10, v1.b[10]1222; CHECK-NEXT: mov v2.b[1], w81223; CHECK-NEXT: udiv w0, w18, w171224; CHECK-NEXT: msub w8, w16, w14, w151225; CHECK-NEXT: umov w14, v0.b[11]1226; CHECK-NEXT: umov w16, v1.b[12]1227; CHECK-NEXT: mov v2.b[2], w81228; CHECK-NEXT: udiv w3, w2, w11229; CHECK-NEXT: msub w8, w0, w17, w181230; CHECK-NEXT: umov w17, v0.b[12]1231; CHECK-NEXT: umov w0, v1.b[13]1232; CHECK-NEXT: mov v2.b[3], w81233; CHECK-NEXT: udiv w6, w5, w41234; CHECK-NEXT: msub w8, w3, w1, w21235; CHECK-NEXT: umov w1, v0.b[13]1236; CHECK-NEXT: mov v2.b[4], w81237; CHECK-NEXT: udiv w20, w19, w71238; CHECK-NEXT: msub w8, w6, w4, w51239; CHECK-NEXT: mov v2.b[5], w81240; CHECK-NEXT: udiv w23, w22, w211241; CHECK-NEXT: msub w8, w20, w7, w191242; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload1243; CHECK-NEXT: mov v2.b[6], w81244; CHECK-NEXT: udiv w26, w25, w241245; CHECK-NEXT: msub w8, w23, w21, w221246; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload1247; CHECK-NEXT: mov v2.b[7], w81248; CHECK-NEXT: udiv w9, w28, w271249; CHECK-NEXT: msub w8, w26, w24, w251250; CHECK-NEXT: ldp x24, x23, [sp, #32] // 16-byte Folded Reload1251; CHECK-NEXT: ldp x26, x25, [sp, #16] // 16-byte Folded Reload1252; CHECK-NEXT: mov v2.b[8], w81253; CHECK-NEXT: udiv w12, w11, w101254; CHECK-NEXT: msub w8, w9, w27, w281255; CHECK-NEXT: mov v2.b[9], w81256; CHECK-NEXT: udiv w15, w14, w131257; CHECK-NEXT: msub w8, w12, w10, w111258; CHECK-NEXT: umov w10, v1.b[14]1259; CHECK-NEXT: umov w11, v0.b[14]1260; CHECK-NEXT: mov v2.b[10], w81261; CHECK-NEXT: udiv w18, w17, w161262; CHECK-NEXT: msub w8, w15, w13, w141263; CHECK-NEXT: umov w13, v1.b[15]1264; CHECK-NEXT: umov w14, v0.b[15]1265; CHECK-NEXT: mov v2.b[11], w81266; CHECK-NEXT: udiv w9, w1, w01267; CHECK-NEXT: msub w8, w18, w16, w171268; CHECK-NEXT: mov v2.b[12], w81269; CHECK-NEXT: udiv w12, w11, w101270; CHECK-NEXT: msub w8, w9, w0, w11271; CHECK-NEXT: mov v2.b[13], w81272; CHECK-NEXT: udiv w9, w14, w131273; CHECK-NEXT: msub w8, w12, w10, w111274; CHECK-NEXT: mov v2.b[14], w81275; CHECK-NEXT: msub w8, w9, w13, w141276; CHECK-NEXT: mov v2.b[15], w81277; CHECK-NEXT: mov v0.16b, v2.16b1278; CHECK-NEXT: ldp x28, x27, [sp], #80 // 16-byte Folded Reload1279; CHECK-NEXT: ret1280 %tmp3 = urem <16 x i8> %A, %B;1281 ret <16 x i8> %tmp31282}1283 1284define <1 x i16> @urem1x16(<1 x i16> %A, <1 x i16> %B) {1285; CHECK-LABEL: urem1x16:1286; CHECK: // %bb.0:1287; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11288; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01289; CHECK-NEXT: umov w8, v1.h[0]1290; CHECK-NEXT: umov w9, v0.h[0]1291; CHECK-NEXT: udiv w10, w9, w81292; CHECK-NEXT: msub w8, w10, w8, w91293; CHECK-NEXT: fmov s0, w81294; CHECK-NEXT: ret1295 %tmp3 = urem <1 x i16> %A, %B;1296 ret <1 x i16> %tmp31297}1298 1299define <4 x i16> @urem4x16(<4 x i16> %A, <4 x i16> %B) {1300; CHECK-LABEL: urem4x16:1301; CHECK: // %bb.0:1302; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11303; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01304; CHECK-NEXT: umov w11, v1.h[0]1305; CHECK-NEXT: umov w12, v0.h[0]1306; CHECK-NEXT: umov w8, v1.h[1]1307; CHECK-NEXT: umov w9, v0.h[1]1308; CHECK-NEXT: umov w14, v1.h[2]1309; CHECK-NEXT: umov w15, v0.h[2]1310; CHECK-NEXT: umov w17, v1.h[3]1311; CHECK-NEXT: umov w18, v0.h[3]1312; CHECK-NEXT: udiv w13, w12, w111313; CHECK-NEXT: udiv w10, w9, w81314; CHECK-NEXT: msub w11, w13, w11, w121315; CHECK-NEXT: fmov s0, w111316; CHECK-NEXT: udiv w16, w15, w141317; CHECK-NEXT: msub w8, w10, w8, w91318; CHECK-NEXT: mov v0.h[1], w81319; CHECK-NEXT: udiv w9, w18, w171320; CHECK-NEXT: msub w8, w16, w14, w151321; CHECK-NEXT: mov v0.h[2], w81322; CHECK-NEXT: msub w8, w9, w17, w181323; CHECK-NEXT: mov v0.h[3], w81324; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01325; CHECK-NEXT: ret1326 %tmp3 = urem <4 x i16> %A, %B;1327 ret <4 x i16> %tmp31328}1329 1330define <8 x i16> @urem8x16(<8 x i16> %A, <8 x i16> %B) {1331; CHECK-LABEL: urem8x16:1332; CHECK: // %bb.0:1333; CHECK-NEXT: umov w11, v1.h[0]1334; CHECK-NEXT: umov w12, v0.h[0]1335; CHECK-NEXT: umov w8, v1.h[1]1336; CHECK-NEXT: umov w9, v0.h[1]1337; CHECK-NEXT: umov w14, v1.h[2]1338; CHECK-NEXT: umov w15, v0.h[2]1339; CHECK-NEXT: umov w17, v1.h[3]1340; CHECK-NEXT: umov w18, v0.h[3]1341; CHECK-NEXT: umov w1, v1.h[4]1342; CHECK-NEXT: umov w2, v0.h[4]1343; CHECK-NEXT: umov w4, v1.h[5]1344; CHECK-NEXT: umov w5, v0.h[5]1345; CHECK-NEXT: udiv w13, w12, w111346; CHECK-NEXT: udiv w10, w9, w81347; CHECK-NEXT: msub w11, w13, w11, w121348; CHECK-NEXT: umov w13, v1.h[7]1349; CHECK-NEXT: fmov s2, w111350; CHECK-NEXT: umov w11, v0.h[6]1351; CHECK-NEXT: udiv w16, w15, w141352; CHECK-NEXT: msub w8, w10, w8, w91353; CHECK-NEXT: umov w10, v1.h[6]1354; CHECK-NEXT: mov v2.h[1], w81355; CHECK-NEXT: udiv w0, w18, w171356; CHECK-NEXT: msub w8, w16, w14, w151357; CHECK-NEXT: umov w14, v0.h[7]1358; CHECK-NEXT: mov v2.h[2], w81359; CHECK-NEXT: udiv w3, w2, w11360; CHECK-NEXT: msub w8, w0, w17, w181361; CHECK-NEXT: mov v2.h[3], w81362; CHECK-NEXT: udiv w9, w5, w41363; CHECK-NEXT: msub w8, w3, w1, w21364; CHECK-NEXT: mov v2.h[4], w81365; CHECK-NEXT: udiv w12, w11, w101366; CHECK-NEXT: msub w8, w9, w4, w51367; CHECK-NEXT: mov v2.h[5], w81368; CHECK-NEXT: udiv w9, w14, w131369; CHECK-NEXT: msub w8, w12, w10, w111370; CHECK-NEXT: mov v2.h[6], w81371; CHECK-NEXT: msub w8, w9, w13, w141372; CHECK-NEXT: mov v2.h[7], w81373; CHECK-NEXT: mov v0.16b, v2.16b1374; CHECK-NEXT: ret1375 %tmp3 = urem <8 x i16> %A, %B;1376 ret <8 x i16> %tmp31377}1378 1379define <1 x i32> @urem1x32(<1 x i32> %A, <1 x i32> %B) {1380; CHECK-LABEL: urem1x32:1381; CHECK: // %bb.0:1382; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11383; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01384; CHECK-NEXT: fmov w8, s11385; CHECK-NEXT: fmov w9, s01386; CHECK-NEXT: udiv w10, w9, w81387; CHECK-NEXT: msub w8, w10, w8, w91388; CHECK-NEXT: fmov s0, w81389; CHECK-NEXT: ret1390 %tmp3 = urem <1 x i32> %A, %B;1391 ret <1 x i32> %tmp31392}1393 1394define <2 x i32> @urem2x32(<2 x i32> %A, <2 x i32> %B) {1395; CHECK-LABEL: urem2x32:1396; CHECK: // %bb.0:1397; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11398; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01399; CHECK-NEXT: fmov w8, s11400; CHECK-NEXT: fmov w9, s01401; CHECK-NEXT: mov w11, v1.s[1]1402; CHECK-NEXT: mov w12, v0.s[1]1403; CHECK-NEXT: udiv w10, w9, w81404; CHECK-NEXT: udiv w13, w12, w111405; CHECK-NEXT: msub w8, w10, w8, w91406; CHECK-NEXT: fmov s0, w81407; CHECK-NEXT: msub w9, w13, w11, w121408; CHECK-NEXT: mov v0.s[1], w91409; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01410; CHECK-NEXT: ret1411 %tmp3 = urem <2 x i32> %A, %B;1412 ret <2 x i32> %tmp31413}1414 1415define <4 x i32> @urem4x32(<4 x i32> %A, <4 x i32> %B) {1416; CHECK-LABEL: urem4x32:1417; CHECK: // %bb.0:1418; CHECK-NEXT: fmov w11, s11419; CHECK-NEXT: fmov w12, s01420; CHECK-NEXT: mov w8, v1.s[1]1421; CHECK-NEXT: mov w9, v0.s[1]1422; CHECK-NEXT: mov w14, v1.s[2]1423; CHECK-NEXT: mov w15, v0.s[2]1424; CHECK-NEXT: mov w17, v1.s[3]1425; CHECK-NEXT: mov w18, v0.s[3]1426; CHECK-NEXT: udiv w13, w12, w111427; CHECK-NEXT: udiv w10, w9, w81428; CHECK-NEXT: msub w11, w13, w11, w121429; CHECK-NEXT: fmov s0, w111430; CHECK-NEXT: udiv w16, w15, w141431; CHECK-NEXT: msub w8, w10, w8, w91432; CHECK-NEXT: mov v0.s[1], w81433; CHECK-NEXT: udiv w9, w18, w171434; CHECK-NEXT: msub w8, w16, w14, w151435; CHECK-NEXT: mov v0.s[2], w81436; CHECK-NEXT: msub w8, w9, w17, w181437; CHECK-NEXT: mov v0.s[3], w81438; CHECK-NEXT: ret1439 %tmp3 = urem <4 x i32> %A, %B;1440 ret <4 x i32> %tmp31441}1442 1443define <1 x i64> @urem1x64(<1 x i64> %A, <1 x i64> %B) {1444; CHECK-LABEL: urem1x64:1445; CHECK: // %bb.0:1446; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11447; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01448; CHECK-NEXT: fmov x8, d11449; CHECK-NEXT: fmov x9, d01450; CHECK-NEXT: udiv x10, x9, x81451; CHECK-NEXT: msub x8, x10, x8, x91452; CHECK-NEXT: fmov d0, x81453; CHECK-NEXT: ret1454 %tmp3 = urem <1 x i64> %A, %B;1455 ret <1 x i64> %tmp31456}1457 1458define <2 x i64> @urem2x64(<2 x i64> %A, <2 x i64> %B) {1459; CHECK-LABEL: urem2x64:1460; CHECK: // %bb.0:1461; CHECK-NEXT: fmov x8, d11462; CHECK-NEXT: fmov x9, d01463; CHECK-NEXT: mov x11, v1.d[1]1464; CHECK-NEXT: mov x12, v0.d[1]1465; CHECK-NEXT: udiv x10, x9, x81466; CHECK-NEXT: udiv x13, x12, x111467; CHECK-NEXT: msub x8, x10, x8, x91468; CHECK-NEXT: fmov d0, x81469; CHECK-NEXT: msub x9, x13, x11, x121470; CHECK-NEXT: mov v0.d[1], x91471; CHECK-NEXT: ret1472 %tmp3 = urem <2 x i64> %A, %B;1473 ret <2 x i64> %tmp31474}1475 1476define <2 x float> @frem2f32(<2 x float> %A, <2 x float> %B) {1477; CHECK-LABEL: frem2f32:1478; CHECK: // %bb.0:1479; CHECK-NEXT: sub sp, sp, #641480; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill1481; CHECK-NEXT: .cfi_def_cfa_offset 641482; CHECK-NEXT: .cfi_offset w30, -161483; CHECK-NEXT: // kill: def $d1 killed $d1 def $q11484; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01485; CHECK-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill1486; CHECK-NEXT: mov s0, v0.s[1]1487; CHECK-NEXT: mov s1, v1.s[1]1488; CHECK-NEXT: bl fmodf1489; CHECK-NEXT: // kill: def $s0 killed $s0 def $q01490; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill1491; CHECK-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload1492; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q01493; CHECK-NEXT: // kill: def $s1 killed $s1 killed $q11494; CHECK-NEXT: bl fmodf1495; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload1496; CHECK-NEXT: // kill: def $s0 killed $s0 def $q01497; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload1498; CHECK-NEXT: mov v0.s[1], v1.s[0]1499; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01500; CHECK-NEXT: add sp, sp, #641501; CHECK-NEXT: ret1502 %tmp3 = frem <2 x float> %A, %B;1503 ret <2 x float> %tmp31504}1505 1506define <4 x float> @frem4f32(<4 x float> %A, <4 x float> %B) {1507; CHECK-LABEL: frem4f32:1508; CHECK: // %bb.0:1509; CHECK-NEXT: sub sp, sp, #641510; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill1511; CHECK-NEXT: .cfi_def_cfa_offset 641512; CHECK-NEXT: .cfi_offset w30, -161513; CHECK-NEXT: stp q0, q1, [sp, #16] // 32-byte Folded Spill1514; CHECK-NEXT: mov s0, v0.s[1]1515; CHECK-NEXT: mov s1, v1.s[1]1516; CHECK-NEXT: bl fmodf1517; CHECK-NEXT: // kill: def $s0 killed $s0 def $q01518; CHECK-NEXT: str q0, [sp] // 16-byte Spill1519; CHECK-NEXT: ldp q0, q1, [sp, #16] // 32-byte Folded Reload1520; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q01521; CHECK-NEXT: // kill: def $s1 killed $s1 killed $q11522; CHECK-NEXT: bl fmodf1523; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload1524; CHECK-NEXT: // kill: def $s0 killed $s0 def $q01525; CHECK-NEXT: mov v0.s[1], v1.s[0]1526; CHECK-NEXT: str q0, [sp] // 16-byte Spill1527; CHECK-NEXT: ldp q0, q1, [sp, #16] // 32-byte Folded Reload1528; CHECK-NEXT: mov s0, v0.s[2]1529; CHECK-NEXT: mov s1, v1.s[2]1530; CHECK-NEXT: bl fmodf1531; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload1532; CHECK-NEXT: // kill: def $s0 killed $s0 def $q01533; CHECK-NEXT: mov v1.s[2], v0.s[0]1534; CHECK-NEXT: str q1, [sp] // 16-byte Spill1535; CHECK-NEXT: ldp q0, q1, [sp, #16] // 32-byte Folded Reload1536; CHECK-NEXT: mov s0, v0.s[3]1537; CHECK-NEXT: mov s1, v1.s[3]1538; CHECK-NEXT: bl fmodf1539; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload1540; CHECK-NEXT: // kill: def $s0 killed $s0 def $q01541; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload1542; CHECK-NEXT: mov v1.s[3], v0.s[0]1543; CHECK-NEXT: mov v0.16b, v1.16b1544; CHECK-NEXT: add sp, sp, #641545; CHECK-NEXT: ret1546 %tmp3 = frem <4 x float> %A, %B;1547 ret <4 x float> %tmp31548}1549 1550define <1 x double> @frem1d64(<1 x double> %A, <1 x double> %B) {1551; CHECK-LABEL: frem1d64:1552; CHECK: // %bb.0:1553; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1554; CHECK-NEXT: .cfi_def_cfa_offset 161555; CHECK-NEXT: .cfi_offset w30, -161556; CHECK-NEXT: bl fmod1557; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1558; CHECK-NEXT: ret1559 %tmp3 = frem <1 x double> %A, %B;1560 ret <1 x double> %tmp31561}1562 1563define <2 x double> @frem2d64(<2 x double> %A, <2 x double> %B) {1564; CHECK-LABEL: frem2d64:1565; CHECK: // %bb.0:1566; CHECK-NEXT: sub sp, sp, #641567; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill1568; CHECK-NEXT: .cfi_def_cfa_offset 641569; CHECK-NEXT: .cfi_offset w30, -161570; CHECK-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill1571; CHECK-NEXT: mov d0, v0.d[1]1572; CHECK-NEXT: mov d1, v1.d[1]1573; CHECK-NEXT: bl fmod1574; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01575; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill1576; CHECK-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload1577; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q01578; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q11579; CHECK-NEXT: bl fmod1580; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload1581; CHECK-NEXT: // kill: def $d0 killed $d0 def $q01582; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload1583; CHECK-NEXT: mov v0.d[1], v1.d[0]1584; CHECK-NEXT: add sp, sp, #641585; CHECK-NEXT: ret1586 %tmp3 = frem <2 x double> %A, %B;1587 ret <2 x double> %tmp31588}1589 1590declare <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8>, <8 x i8>)1591declare <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8>, <16 x i8>)1592 1593define <8 x i8> @poly_mulv8i8(<8 x i8> %lhs, <8 x i8> %rhs) {1594; CHECK-LABEL: poly_mulv8i8:1595; CHECK: // %bb.0:1596; CHECK-NEXT: pmul v0.8b, v0.8b, v1.8b1597; CHECK-NEXT: ret1598 %prod = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)1599 ret <8 x i8> %prod1600}1601 1602define <16 x i8> @poly_mulv16i8(<16 x i8> %lhs, <16 x i8> %rhs) {1603; CHECK-LABEL: poly_mulv16i8:1604; CHECK: // %bb.0:1605; CHECK-NEXT: pmul v0.16b, v0.16b, v1.16b1606; CHECK-NEXT: ret1607 %prod = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)1608 ret <16 x i8> %prod1609}1610 1611define <16 x i8> @commutable_poly_mul(<16 x i8> %lhs, <16 x i8> %rhs) {1612; CHECK-LABEL: commutable_poly_mul:1613; CHECK: // %bb.0:1614; CHECK-NEXT: pmul v0.16b, v0.16b, v1.16b1615; CHECK-NEXT: add v0.16b, v0.16b, v0.16b1616; CHECK-NEXT: ret1617 %1 = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)1618 %2 = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> %rhs, <16 x i8> %lhs)1619 %3 = add <16 x i8> %1, %21620 ret <16 x i8> %31621}1622 1623declare <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>)1624declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>)1625declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)1626declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)1627 1628define <4 x i16> @test_sqdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {1629; CHECK-LABEL: test_sqdmulh_v4i16:1630; CHECK: // %bb.0:1631; CHECK-NEXT: sqdmulh v0.4h, v0.4h, v1.4h1632; CHECK-NEXT: ret1633 %prod = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)1634 ret <4 x i16> %prod1635}1636 1637define <8 x i16> @test_sqdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {1638; CHECK-LABEL: test_sqdmulh_v8i16:1639; CHECK: // %bb.0:1640; CHECK-NEXT: sqdmulh v0.8h, v0.8h, v1.8h1641; CHECK-NEXT: ret1642 %prod = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)1643 ret <8 x i16> %prod1644}1645 1646define <2 x i32> @test_sqdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {1647; CHECK-LABEL: test_sqdmulh_v2i32:1648; CHECK: // %bb.0:1649; CHECK-NEXT: sqdmulh v0.2s, v0.2s, v1.2s1650; CHECK-NEXT: ret1651 %prod = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1652 ret <2 x i32> %prod1653}1654 1655define <4 x i32> @test_sqdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {1656; CHECK-LABEL: test_sqdmulh_v4i32:1657; CHECK: // %bb.0:1658; CHECK-NEXT: sqdmulh v0.4s, v0.4s, v1.4s1659; CHECK-NEXT: ret1660 %prod = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1661 ret <4 x i32> %prod1662}1663 1664declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)1665declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)1666declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)1667declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)1668 1669define <4 x i16> @test_sqrdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {1670; CHECK-LABEL: test_sqrdmulh_v4i16:1671; CHECK: // %bb.0:1672; CHECK-NEXT: sqrdmulh v0.4h, v0.4h, v1.4h1673; CHECK-NEXT: ret1674 %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)1675 ret <4 x i16> %prod1676}1677 1678define <8 x i16> @test_sqrdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {1679; CHECK-LABEL: test_sqrdmulh_v8i16:1680; CHECK: // %bb.0:1681; CHECK-NEXT: sqrdmulh v0.8h, v0.8h, v1.8h1682; CHECK-NEXT: ret1683 %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)1684 ret <8 x i16> %prod1685}1686 1687define <2 x i32> @test_sqrdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {1688; CHECK-LABEL: test_sqrdmulh_v2i32:1689; CHECK: // %bb.0:1690; CHECK-NEXT: sqrdmulh v0.2s, v0.2s, v1.2s1691; CHECK-NEXT: ret1692 %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1693 ret <2 x i32> %prod1694}1695 1696define <4 x i32> @test_sqrdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {1697; CHECK-LABEL: test_sqrdmulh_v4i32:1698; CHECK: // %bb.0:1699; CHECK-NEXT: sqrdmulh v0.4s, v0.4s, v1.4s1700; CHECK-NEXT: ret1701 %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1702 ret <4 x i32> %prod1703}1704 1705declare <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float>, <2 x float>)1706declare <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float>, <4 x float>)1707declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)1708 1709define <2 x float> @fmulx_v2f32(<2 x float> %lhs, <2 x float> %rhs) {1710; CHECK-LABEL: fmulx_v2f32:1711; CHECK: // %bb.0:1712; CHECK-NEXT: fmulx v0.2s, v0.2s, v1.2s1713; CHECK-NEXT: ret1714; Using registers other than v0, v1 and v2 are possible, but would be odd.1715 %val = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %lhs, <2 x float> %rhs)1716 ret <2 x float> %val1717}1718 1719define <4 x float> @fmulx_v4f32(<4 x float> %lhs, <4 x float> %rhs) {1720; CHECK-LABEL: fmulx_v4f32:1721; CHECK: // %bb.0:1722; CHECK-NEXT: fmulx v0.4s, v0.4s, v1.4s1723; CHECK-NEXT: ret1724; Using registers other than v0, v1 and v2 are possible, but would be odd.1725 %val = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %lhs, <4 x float> %rhs)1726 ret <4 x float> %val1727}1728 1729define <2 x double> @fmulx_v2f64(<2 x double> %lhs, <2 x double> %rhs) {1730; CHECK-LABEL: fmulx_v2f64:1731; CHECK: // %bb.0:1732; CHECK-NEXT: fmulx v0.2d, v0.2d, v1.2d1733; CHECK-NEXT: ret1734; Using registers other than v0, v1 and v2 are possible, but would be odd.1735 %val = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %lhs, <2 x double> %rhs)1736 ret <2 x double> %val1737}1738