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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s3 4define float @test_fmul_lane_ss2S_0(float %a, <2 x float> %v) {5; CHECK-LABEL: test_fmul_lane_ss2S_0:6; CHECK: // %bb.0:7; CHECK-NEXT: // kill: def $d1 killed $d1 def $q18; CHECK-NEXT: fmul s0, s0, s19; CHECK-NEXT: ret10 %tmp1 = extractelement <2 x float> %v, i32 011 %tmp2 = fmul float %a, %tmp112 ret float %tmp213}14 15define float @test_fmul_lane_ss2S_1(float %a, <2 x float> %v) {16; CHECK-LABEL: test_fmul_lane_ss2S_1:17; CHECK: // %bb.0:18; CHECK-NEXT: // kill: def $d1 killed $d1 def $q119; CHECK-NEXT: fmul s0, s0, v1.s[1]20; CHECK-NEXT: ret21 %tmp1 = extractelement <2 x float> %v, i32 122 %tmp2 = fmul float %a, %tmp1;23 ret float %tmp2;24}25 26define float @test_fmul_lane_ss2S_1_swap(float %a, <2 x float> %v) {27; CHECK-LABEL: test_fmul_lane_ss2S_1_swap:28; CHECK: // %bb.0:29; CHECK-NEXT: // kill: def $d1 killed $d1 def $q130; CHECK-NEXT: fmul s0, s0, v1.s[1]31; CHECK-NEXT: ret32 %tmp1 = extractelement <2 x float> %v, i32 133 %tmp2 = fmul float %tmp1, %a;34 ret float %tmp2;35}36 37define float @test_fmul_lane_ss4S_0(float %a, <4 x float> %v) {38; CHECK-LABEL: test_fmul_lane_ss4S_0:39; CHECK: // %bb.0:40; CHECK-NEXT: fmul s0, s0, s141; CHECK-NEXT: ret42 %tmp1 = extractelement <4 x float> %v, i32 043 %tmp2 = fmul float %a, %tmp144 ret float %tmp245}46 47define float @test_fmul_lane_ss4S_3(float %a, <4 x float> %v) {48; CHECK-LABEL: test_fmul_lane_ss4S_3:49; CHECK: // %bb.0:50; CHECK-NEXT: fmul s0, s0, v1.s[3]51; CHECK-NEXT: ret52 %tmp1 = extractelement <4 x float> %v, i32 353 %tmp2 = fmul float %a, %tmp1;54 ret float %tmp2;55}56 57define float @test_fmul_lane_ss4S_3_swap(float %a, <4 x float> %v) {58; CHECK-LABEL: test_fmul_lane_ss4S_3_swap:59; CHECK: // %bb.0:60; CHECK-NEXT: fmul s0, s0, v1.s[3]61; CHECK-NEXT: ret62 %tmp1 = extractelement <4 x float> %v, i32 363 %tmp2 = fmul float %tmp1, %a;64 ret float %tmp2;65}66 67 68define double @test_fmul_lane_ddD(double %a, <1 x double> %v) {69; CHECK-LABEL: test_fmul_lane_ddD:70; CHECK: // %bb.0:71; CHECK-NEXT: fmul d0, d0, d172; CHECK-NEXT: ret73 %tmp1 = extractelement <1 x double> %v, i32 074 %tmp2 = fmul double %a, %tmp1;75 ret double %tmp2;76}77 78 79define double @test_fmul_lane_dd2D_0(double %a, <2 x double> %v) {80; CHECK-LABEL: test_fmul_lane_dd2D_0:81; CHECK: // %bb.0:82; CHECK-NEXT: fmul d0, d0, d183; CHECK-NEXT: ret84 %tmp1 = extractelement <2 x double> %v, i32 085 %tmp2 = fmul double %a, %tmp186 ret double %tmp287}88 89define double @test_fmul_lane_dd2D_1(double %a, <2 x double> %v) {90; CHECK-LABEL: test_fmul_lane_dd2D_1:91; CHECK: // %bb.0:92; CHECK-NEXT: fmul d0, d0, v1.d[1]93; CHECK-NEXT: ret94 %tmp1 = extractelement <2 x double> %v, i32 195 %tmp2 = fmul double %a, %tmp1;96 ret double %tmp2;97}98 99 100define double @test_fmul_lane_dd2D_1_swap(double %a, <2 x double> %v) {101; CHECK-LABEL: test_fmul_lane_dd2D_1_swap:102; CHECK: // %bb.0:103; CHECK-NEXT: fmul d0, d0, v1.d[1]104; CHECK-NEXT: ret105 %tmp1 = extractelement <2 x double> %v, i32 1106 %tmp2 = fmul double %tmp1, %a;107 ret double %tmp2;108}109 110declare float @llvm.aarch64.neon.fmulx.f32(float, float)111 112define float @test_fmulx_lane_f32_0(float %a, <2 x float> %v) {113; CHECK-LABEL: test_fmulx_lane_f32_0:114; CHECK: // %bb.0:115; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1116; CHECK-NEXT: fmulx s0, s0, s1117; CHECK-NEXT: ret118 %tmp1 = extractelement <2 x float> %v, i32 0119 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %a, float %tmp1)120 ret float %tmp2;121}122 123define float @test_fmulx_lane_f32_1(float %a, <2 x float> %v) {124; CHECK-LABEL: test_fmulx_lane_f32_1:125; CHECK: // %bb.0:126; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1127; CHECK-NEXT: fmulx s0, s0, v1.s[1]128; CHECK-NEXT: ret129 %tmp1 = extractelement <2 x float> %v, i32 1130 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %a, float %tmp1)131 ret float %tmp2;132}133 134define float @test_fmulx_laneq_f32_0(float %a, <4 x float> %v) {135; CHECK-LABEL: test_fmulx_laneq_f32_0:136; CHECK: // %bb.0:137; CHECK-NEXT: fmulx s0, s0, s1138; CHECK-NEXT: ret139 %tmp1 = extractelement <4 x float> %v, i32 0140 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %a, float %tmp1)141 ret float %tmp2;142}143 144define float @test_fmulx_laneq_f32_3(float %a, <4 x float> %v) {145; CHECK-LABEL: test_fmulx_laneq_f32_3:146; CHECK: // %bb.0:147; CHECK-NEXT: fmulx s0, s0, v1.s[3]148; CHECK-NEXT: ret149 %tmp1 = extractelement <4 x float> %v, i32 3150 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %a, float %tmp1)151 ret float %tmp2;152}153 154define float @test_fmulx_laneq_f32_3_swap(float %a, <4 x float> %v) {155; CHECK-LABEL: test_fmulx_laneq_f32_3_swap:156; CHECK: // %bb.0:157; CHECK-NEXT: fmulx s0, s0, v1.s[3]158; CHECK-NEXT: ret159 %tmp1 = extractelement <4 x float> %v, i32 3160 %tmp2 = call float @llvm.aarch64.neon.fmulx.f32(float %tmp1, float %a)161 ret float %tmp2;162}163 164declare double @llvm.aarch64.neon.fmulx.f64(double, double)165 166define double @test_fmulx_lane_f64(double %a, <1 x double> %v) {167; CHECK-LABEL: test_fmulx_lane_f64:168; CHECK: // %bb.0:169; CHECK-NEXT: fmulx d0, d0, d1170; CHECK-NEXT: ret171 %tmp1 = extractelement <1 x double> %v, i32 0172 %tmp2 = call double @llvm.aarch64.neon.fmulx.f64(double %a, double %tmp1)173 ret double %tmp2;174}175 176define double @test_fmulx_laneq_f64_0(double %a, <2 x double> %v) {177; CHECK-LABEL: test_fmulx_laneq_f64_0:178; CHECK: // %bb.0:179; CHECK-NEXT: fmulx d0, d0, d1180; CHECK-NEXT: ret181 %tmp1 = extractelement <2 x double> %v, i32 0182 %tmp2 = call double @llvm.aarch64.neon.fmulx.f64(double %a, double %tmp1)183 ret double %tmp2;184}185 186 187define double @test_fmulx_laneq_f64_1(double %a, <2 x double> %v) {188; CHECK-LABEL: test_fmulx_laneq_f64_1:189; CHECK: // %bb.0:190; CHECK-NEXT: fmulx d0, d0, v1.d[1]191; CHECK-NEXT: ret192 %tmp1 = extractelement <2 x double> %v, i32 1193 %tmp2 = call double @llvm.aarch64.neon.fmulx.f64(double %a, double %tmp1)194 ret double %tmp2;195}196 197define double @test_fmulx_laneq_f64_1_swap(double %a, <2 x double> %v) {198; CHECK-LABEL: test_fmulx_laneq_f64_1_swap:199; CHECK: // %bb.0:200; CHECK-NEXT: fmulx d0, d0, v1.d[1]201; CHECK-NEXT: ret202 %tmp1 = extractelement <2 x double> %v, i32 1203 %tmp2 = call double @llvm.aarch64.neon.fmulx.f64(double %tmp1, double %a)204 ret double %tmp2;205}206 207define float @test_fmulx_horizontal_f32(<2 x float> %v) {208; CHECK-LABEL: test_fmulx_horizontal_f32:209; CHECK: // %bb.0: // %entry210; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0211; CHECK-NEXT: fmulx s0, s0, v0.s[1]212; CHECK-NEXT: ret213entry:214 %0 = extractelement <2 x float> %v, i32 0215 %1 = extractelement <2 x float> %v, i32 1216 %2 = call float @llvm.aarch64.neon.fmulx.f32(float %0, float %1)217 ret float %2218}219 220define double @test_fmulx_horizontal_f64(<2 x double> %v) {221; CHECK-LABEL: test_fmulx_horizontal_f64:222; CHECK: // %bb.0: // %entry223; CHECK-NEXT: fmulx d0, d0, v0.d[1]224; CHECK-NEXT: ret225entry:226 %0 = extractelement <2 x double> %v, i32 0227 %1 = extractelement <2 x double> %v, i32 1228 %2 = call double @llvm.aarch64.neon.fmulx.f64(double %0, double %1)229 ret double %2230}231