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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-GI3; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD4 5 6%struct.uint8x16x2_t = type { [2 x <16 x i8>] }7%struct.poly8x16x2_t = type { [2 x <16 x i8>] }8%struct.uint8x16x3_t = type { [3 x <16 x i8>] }9%struct.int8x16x2_t = type { [2 x <16 x i8>] }10%struct.int16x8x2_t = type { [2 x <8 x i16>] }11%struct.int32x4x2_t = type { [2 x <4 x i32>] }12%struct.int64x2x2_t = type { [2 x <2 x i64>] }13%struct.float32x4x2_t = type { [2 x <4 x float>] }14%struct.float64x2x2_t = type { [2 x <2 x double>] }15%struct.int8x8x2_t = type { [2 x <8 x i8>] }16%struct.int16x4x2_t = type { [2 x <4 x i16>] }17%struct.int32x2x2_t = type { [2 x <2 x i32>] }18%struct.int64x1x2_t = type { [2 x <1 x i64>] }19%struct.float32x2x2_t = type { [2 x <2 x float>] }20%struct.float64x1x2_t = type { [2 x <1 x double>] }21%struct.int8x16x3_t = type { [3 x <16 x i8>] }22%struct.int16x8x3_t = type { [3 x <8 x i16>] }23%struct.int32x4x3_t = type { [3 x <4 x i32>] }24%struct.int64x2x3_t = type { [3 x <2 x i64>] }25%struct.float32x4x3_t = type { [3 x <4 x float>] }26%struct.float64x2x3_t = type { [3 x <2 x double>] }27%struct.int8x8x3_t = type { [3 x <8 x i8>] }28%struct.int16x4x3_t = type { [3 x <4 x i16>] }29%struct.int32x2x3_t = type { [3 x <2 x i32>] }30%struct.int64x1x3_t = type { [3 x <1 x i64>] }31%struct.float32x2x3_t = type { [3 x <2 x float>] }32%struct.float64x1x3_t = type { [3 x <1 x double>] }33%struct.int8x16x4_t = type { [4 x <16 x i8>] }34%struct.int16x8x4_t = type { [4 x <8 x i16>] }35%struct.int32x4x4_t = type { [4 x <4 x i32>] }36%struct.int64x2x4_t = type { [4 x <2 x i64>] }37%struct.float32x4x4_t = type { [4 x <4 x float>] }38%struct.float64x2x4_t = type { [4 x <2 x double>] }39%struct.int8x8x4_t = type { [4 x <8 x i8>] }40%struct.int16x4x4_t = type { [4 x <4 x i16>] }41%struct.int32x2x4_t = type { [4 x <2 x i32>] }42%struct.int64x1x4_t = type { [4 x <1 x i64>] }43%struct.float32x2x4_t = type { [4 x <2 x float>] }44%struct.float64x1x4_t = type { [4 x <1 x double>] }45 46define <16 x i8> @test_ld_from_poll_v16i8(<16 x i8> %a) {47; CHECK-LABEL: test_ld_from_poll_v16i8:48; CHECK: // %bb.0: // %entry49; CHECK-NEXT: adrp x8, .LCPI0_050; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]51; CHECK-NEXT: add v0.16b, v0.16b, v1.16b52; CHECK-NEXT: ret53entry:54 %b = add <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 2, i8 13, i8 14, i8 15, i8 16>55 ret <16 x i8> %b56}57 58define <8 x i16> @test_ld_from_poll_v8i16(<8 x i16> %a) {59; CHECK-LABEL: test_ld_from_poll_v8i16:60; CHECK: // %bb.0: // %entry61; CHECK-NEXT: adrp x8, .LCPI1_062; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]63; CHECK-NEXT: add v0.8h, v0.8h, v1.8h64; CHECK-NEXT: ret65entry:66 %b = add <8 x i16> %a, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>67 ret <8 x i16> %b68}69 70define <4 x i32> @test_ld_from_poll_v4i32(<4 x i32> %a) {71; CHECK-LABEL: test_ld_from_poll_v4i32:72; CHECK: // %bb.0: // %entry73; CHECK-NEXT: adrp x8, .LCPI2_074; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]75; CHECK-NEXT: add v0.4s, v0.4s, v1.4s76; CHECK-NEXT: ret77entry:78 %b = add <4 x i32> %a, <i32 1, i32 2, i32 3, i32 4>79 ret <4 x i32> %b80}81 82define <2 x i64> @test_ld_from_poll_v2i64(<2 x i64> %a) {83; CHECK-LABEL: test_ld_from_poll_v2i64:84; CHECK: // %bb.0: // %entry85; CHECK-NEXT: adrp x8, .LCPI3_086; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]87; CHECK-NEXT: add v0.2d, v0.2d, v1.2d88; CHECK-NEXT: ret89entry:90 %b = add <2 x i64> %a, <i64 1, i64 2>91 ret <2 x i64> %b92}93 94define <4 x float> @test_ld_from_poll_v4f32(<4 x float> %a) {95; CHECK-LABEL: test_ld_from_poll_v4f32:96; CHECK: // %bb.0: // %entry97; CHECK-NEXT: adrp x8, .LCPI4_098; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]99; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s100; CHECK-NEXT: ret101entry:102 %b = fadd <4 x float> %a, <float 1.0, float 2.0, float 3.0, float 4.0>103 ret <4 x float> %b104}105 106define <2 x double> @test_ld_from_poll_v2f64(<2 x double> %a) {107; CHECK-LABEL: test_ld_from_poll_v2f64:108; CHECK: // %bb.0: // %entry109; CHECK-NEXT: adrp x8, .LCPI5_0110; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]111; CHECK-NEXT: fadd v0.2d, v0.2d, v1.2d112; CHECK-NEXT: ret113entry:114 %b = fadd <2 x double> %a, <double 1.0, double 2.0>115 ret <2 x double> %b116}117 118define <8 x i8> @test_ld_from_poll_v8i8(<8 x i8> %a) {119; CHECK-LABEL: test_ld_from_poll_v8i8:120; CHECK: // %bb.0: // %entry121; CHECK-NEXT: adrp x8, .LCPI6_0122; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI6_0]123; CHECK-NEXT: add v0.8b, v0.8b, v1.8b124; CHECK-NEXT: ret125entry:126 %b = add <8 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>127 ret <8 x i8> %b128}129 130define <4 x i16> @test_ld_from_poll_v4i16(<4 x i16> %a) {131; CHECK-LABEL: test_ld_from_poll_v4i16:132; CHECK: // %bb.0: // %entry133; CHECK-NEXT: adrp x8, .LCPI7_0134; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI7_0]135; CHECK-NEXT: add v0.4h, v0.4h, v1.4h136; CHECK-NEXT: ret137entry:138 %b = add <4 x i16> %a, <i16 1, i16 2, i16 3, i16 4>139 ret <4 x i16> %b140}141 142define <2 x i32> @test_ld_from_poll_v2i32(<2 x i32> %a) {143; CHECK-LABEL: test_ld_from_poll_v2i32:144; CHECK: // %bb.0: // %entry145; CHECK-NEXT: adrp x8, .LCPI8_0146; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI8_0]147; CHECK-NEXT: add v0.2s, v0.2s, v1.2s148; CHECK-NEXT: ret149entry:150 %b = add <2 x i32> %a, <i32 1, i32 2>151 ret <2 x i32> %b152}153 154define <16 x i8> @test_vld1q_dup_s8(ptr %a) {155; CHECK-LABEL: test_vld1q_dup_s8:156; CHECK: // %bb.0: // %entry157; CHECK-NEXT: ld1r { v0.16b }, [x0]158; CHECK-NEXT: ret159entry:160 %0 = load i8, ptr %a, align 1161 %1 = insertelement <16 x i8> undef, i8 %0, i32 0162 %lane = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer163 ret <16 x i8> %lane164}165 166define <8 x i16> @test_vld1q_dup_s16(ptr %a) {167; CHECK-LABEL: test_vld1q_dup_s16:168; CHECK: // %bb.0: // %entry169; CHECK-NEXT: ld1r { v0.8h }, [x0]170; CHECK-NEXT: ret171entry:172 %0 = load i16, ptr %a, align 2173 %1 = insertelement <8 x i16> undef, i16 %0, i32 0174 %lane = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> zeroinitializer175 ret <8 x i16> %lane176}177 178define <4 x i32> @test_vld1q_dup_s32(ptr %a) {179; CHECK-LABEL: test_vld1q_dup_s32:180; CHECK: // %bb.0: // %entry181; CHECK-NEXT: ld1r { v0.4s }, [x0]182; CHECK-NEXT: ret183entry:184 %0 = load i32, ptr %a, align 4185 %1 = insertelement <4 x i32> undef, i32 %0, i32 0186 %lane = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer187 ret <4 x i32> %lane188}189 190define <2 x i64> @test_vld1q_dup_s64(ptr %a) {191; CHECK-LABEL: test_vld1q_dup_s64:192; CHECK: // %bb.0: // %entry193; CHECK-NEXT: ld1r { v0.2d }, [x0]194; CHECK-NEXT: ret195entry:196 %0 = load i64, ptr %a, align 8197 %1 = insertelement <2 x i64> undef, i64 %0, i32 0198 %lane = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> zeroinitializer199 ret <2 x i64> %lane200}201 202define <4 x float> @test_vld1q_dup_f32(ptr %a) {203; CHECK-LABEL: test_vld1q_dup_f32:204; CHECK: // %bb.0: // %entry205; CHECK-NEXT: ld1r { v0.4s }, [x0]206; CHECK-NEXT: ret207entry:208 %0 = load float, ptr %a, align 4209 %1 = insertelement <4 x float> undef, float %0, i32 0210 %lane = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer211 ret <4 x float> %lane212}213 214define <2 x double> @test_vld1q_dup_f64(ptr %a) {215; CHECK-LABEL: test_vld1q_dup_f64:216; CHECK: // %bb.0: // %entry217; CHECK-NEXT: ld1r { v0.2d }, [x0]218; CHECK-NEXT: ret219entry:220 %0 = load double, ptr %a, align 8221 %1 = insertelement <2 x double> undef, double %0, i32 0222 %lane = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> zeroinitializer223 ret <2 x double> %lane224}225 226define <8 x i8> @test_vld1_dup_s8(ptr %a) {227; CHECK-LABEL: test_vld1_dup_s8:228; CHECK: // %bb.0: // %entry229; CHECK-NEXT: ld1r { v0.8b }, [x0]230; CHECK-NEXT: ret231entry:232 %0 = load i8, ptr %a, align 1233 %1 = insertelement <8 x i8> undef, i8 %0, i32 0234 %lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer235 ret <8 x i8> %lane236}237 238define <4 x i16> @test_vld1_dup_s16(ptr %a) {239; CHECK-LABEL: test_vld1_dup_s16:240; CHECK: // %bb.0: // %entry241; CHECK-NEXT: ld1r { v0.4h }, [x0]242; CHECK-NEXT: ret243entry:244 %0 = load i16, ptr %a, align 2245 %1 = insertelement <4 x i16> undef, i16 %0, i32 0246 %lane = shufflevector <4 x i16> %1, <4 x i16> undef, <4 x i32> zeroinitializer247 ret <4 x i16> %lane248}249 250define <2 x i32> @test_vld1_dup_s32(ptr %a) {251; CHECK-LABEL: test_vld1_dup_s32:252; CHECK: // %bb.0: // %entry253; CHECK-NEXT: ld1r { v0.2s }, [x0]254; CHECK-NEXT: ret255entry:256 %0 = load i32, ptr %a, align 4257 %1 = insertelement <2 x i32> undef, i32 %0, i32 0258 %lane = shufflevector <2 x i32> %1, <2 x i32> undef, <2 x i32> zeroinitializer259 ret <2 x i32> %lane260}261 262define <1 x i64> @test_vld1_dup_s64(ptr %a) {263; CHECK-LABEL: test_vld1_dup_s64:264; CHECK: // %bb.0: // %entry265; CHECK-NEXT: ldr d0, [x0]266; CHECK-NEXT: ret267entry:268 %0 = load i64, ptr %a, align 8269 %1 = insertelement <1 x i64> undef, i64 %0, i32 0270 ret <1 x i64> %1271}272 273define <2 x float> @test_vld1_dup_f32(ptr %a) {274; CHECK-LABEL: test_vld1_dup_f32:275; CHECK: // %bb.0: // %entry276; CHECK-NEXT: ld1r { v0.2s }, [x0]277; CHECK-NEXT: ret278entry:279 %0 = load float, ptr %a, align 4280 %1 = insertelement <2 x float> undef, float %0, i32 0281 %lane = shufflevector <2 x float> %1, <2 x float> undef, <2 x i32> zeroinitializer282 ret <2 x float> %lane283}284 285define <1 x double> @test_vld1_dup_f64(ptr %a) {286; CHECK-LABEL: test_vld1_dup_f64:287; CHECK: // %bb.0: // %entry288; CHECK-NEXT: ldr d0, [x0]289; CHECK-NEXT: ret290entry:291 %0 = load double, ptr %a, align 8292 %1 = insertelement <1 x double> undef, double %0, i32 0293 ret <1 x double> %1294}295 296define <1 x i64> @testDUP.v1i64(ptr %a, ptr %b) #0 {297; As there is a store operation depending on %1, LD1R pattern can't be selected.298; So LDR and FMOV should be emitted.299; CHECK-GI-LABEL: testDUP.v1i64:300; CHECK-GI: // %bb.0:301; CHECK-GI-NEXT: ldr x8, [x0]302; CHECK-GI-NEXT: fmov d0, x8303; CHECK-GI-NEXT: str x8, [x1]304; CHECK-GI-NEXT: ret305;306; CHECK-SD-LABEL: testDUP.v1i64:307; CHECK-SD: // %bb.0:308; CHECK-SD-NEXT: ldr d0, [x0]309; CHECK-SD-NEXT: str d0, [x1]310; CHECK-SD-NEXT: ret311 %1 = load i64, ptr %a, align 8312 store i64 %1, ptr %b, align 8313 %vecinit.i = insertelement <1 x i64> undef, i64 %1, i32 0314 ret <1 x i64> %vecinit.i315}316 317define <1 x double> @testDUP.v1f64(ptr %a, ptr %b) #0 {318; As there is a store operation depending on %1, LD1R pattern can't be selected.319; So LDR and FMOV should be emitted.320; CHECK-LABEL: testDUP.v1f64:321; CHECK: // %bb.0:322; CHECK-NEXT: ldr d0, [x0]323; CHECK-NEXT: str d0, [x1]324; CHECK-NEXT: ret325 %1 = load double, ptr %a, align 8326 store double %1, ptr %b, align 8327 %vecinit.i = insertelement <1 x double> undef, double %1, i32 0328 ret <1 x double> %vecinit.i329}330 331define <16 x i8> @test_vld1q_lane_s8(ptr %a, <16 x i8> %b) {332; CHECK-LABEL: test_vld1q_lane_s8:333; CHECK: // %bb.0: // %entry334; CHECK-NEXT: ld1 { v0.b }[15], [x0]335; CHECK-NEXT: ret336entry:337 %0 = load i8, ptr %a, align 1338 %vld1_lane = insertelement <16 x i8> %b, i8 %0, i32 15339 ret <16 x i8> %vld1_lane340}341 342define <8 x i16> @test_vld1q_lane_s16(ptr %a, <8 x i16> %b) {343; CHECK-LABEL: test_vld1q_lane_s16:344; CHECK: // %bb.0: // %entry345; CHECK-NEXT: ld1 { v0.h }[7], [x0]346; CHECK-NEXT: ret347entry:348 %0 = load i16, ptr %a, align 2349 %vld1_lane = insertelement <8 x i16> %b, i16 %0, i32 7350 ret <8 x i16> %vld1_lane351}352 353define <4 x i32> @test_vld1q_lane_s32(ptr %a, <4 x i32> %b) {354; CHECK-LABEL: test_vld1q_lane_s32:355; CHECK: // %bb.0: // %entry356; CHECK-NEXT: ld1 { v0.s }[3], [x0]357; CHECK-NEXT: ret358entry:359 %0 = load i32, ptr %a, align 4360 %vld1_lane = insertelement <4 x i32> %b, i32 %0, i32 3361 ret <4 x i32> %vld1_lane362}363 364define <2 x i64> @test_vld1q_lane_s64(ptr %a, <2 x i64> %b) {365; CHECK-LABEL: test_vld1q_lane_s64:366; CHECK: // %bb.0: // %entry367; CHECK-NEXT: ld1 { v0.d }[1], [x0]368; CHECK-NEXT: ret369entry:370 %0 = load i64, ptr %a, align 8371 %vld1_lane = insertelement <2 x i64> %b, i64 %0, i32 1372 ret <2 x i64> %vld1_lane373}374 375define <4 x float> @test_vld1q_lane_f32(ptr %a, <4 x float> %b) {376; CHECK-LABEL: test_vld1q_lane_f32:377; CHECK: // %bb.0: // %entry378; CHECK-NEXT: ld1 { v0.s }[3], [x0]379; CHECK-NEXT: ret380entry:381 %0 = load float, ptr %a, align 4382 %vld1_lane = insertelement <4 x float> %b, float %0, i32 3383 ret <4 x float> %vld1_lane384}385 386define <2 x double> @test_vld1q_lane_f64(ptr %a, <2 x double> %b) {387; CHECK-LABEL: test_vld1q_lane_f64:388; CHECK: // %bb.0: // %entry389; CHECK-NEXT: ld1 { v0.d }[1], [x0]390; CHECK-NEXT: ret391entry:392 %0 = load double, ptr %a, align 8393 %vld1_lane = insertelement <2 x double> %b, double %0, i32 1394 ret <2 x double> %vld1_lane395}396 397define <8 x i8> @test_vld1_lane_s8(ptr %a, <8 x i8> %b) {398; CHECK-LABEL: test_vld1_lane_s8:399; CHECK: // %bb.0: // %entry400; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0401; CHECK-NEXT: ld1 { v0.b }[7], [x0]402; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0403; CHECK-NEXT: ret404entry:405 %0 = load i8, ptr %a, align 1406 %vld1_lane = insertelement <8 x i8> %b, i8 %0, i32 7407 ret <8 x i8> %vld1_lane408}409 410define <4 x i16> @test_vld1_lane_s16(ptr %a, <4 x i16> %b) {411; CHECK-LABEL: test_vld1_lane_s16:412; CHECK: // %bb.0: // %entry413; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0414; CHECK-NEXT: ld1 { v0.h }[3], [x0]415; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0416; CHECK-NEXT: ret417entry:418 %0 = load i16, ptr %a, align 2419 %vld1_lane = insertelement <4 x i16> %b, i16 %0, i32 3420 ret <4 x i16> %vld1_lane421}422 423define <2 x i32> @test_vld1_lane_s32(ptr %a, <2 x i32> %b) {424; CHECK-LABEL: test_vld1_lane_s32:425; CHECK: // %bb.0: // %entry426; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0427; CHECK-NEXT: ld1 { v0.s }[1], [x0]428; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0429; CHECK-NEXT: ret430entry:431 %0 = load i32, ptr %a, align 4432 %vld1_lane = insertelement <2 x i32> %b, i32 %0, i32 1433 ret <2 x i32> %vld1_lane434}435 436define <1 x i64> @test_vld1_lane_s64(ptr %a, <1 x i64> %b) {437; CHECK-LABEL: test_vld1_lane_s64:438; CHECK: // %bb.0: // %entry439; CHECK-NEXT: ldr d0, [x0]440; CHECK-NEXT: ret441entry:442 %0 = load i64, ptr %a, align 8443 %vld1_lane = insertelement <1 x i64> undef, i64 %0, i32 0444 ret <1 x i64> %vld1_lane445}446 447define <2 x float> @test_vld1_lane_f32(ptr %a, <2 x float> %b) {448; CHECK-LABEL: test_vld1_lane_f32:449; CHECK: // %bb.0: // %entry450; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0451; CHECK-NEXT: ld1 { v0.s }[1], [x0]452; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0453; CHECK-NEXT: ret454entry:455 %0 = load float, ptr %a, align 4456 %vld1_lane = insertelement <2 x float> %b, float %0, i32 1457 ret <2 x float> %vld1_lane458}459 460define <1 x double> @test_vld1_lane_f64(ptr %a, <1 x double> %b) {461; CHECK-LABEL: test_vld1_lane_f64:462; CHECK: // %bb.0: // %entry463; CHECK-NEXT: ldr d0, [x0]464; CHECK-NEXT: ret465entry:466 %0 = load double, ptr %a, align 8467 %vld1_lane = insertelement <1 x double> undef, double %0, i32 0468 ret <1 x double> %vld1_lane469}470 471define void @test_vst1q_lane_s8(ptr %a, <16 x i8> %b) {472; CHECK-LABEL: test_vst1q_lane_s8:473; CHECK: // %bb.0: // %entry474; CHECK-NEXT: st1 { v0.b }[15], [x0]475; CHECK-NEXT: ret476entry:477 %0 = extractelement <16 x i8> %b, i32 15478 store i8 %0, ptr %a, align 1479 ret void480}481 482define void @test_vst1q_lane_s16(ptr %a, <8 x i16> %b) {483; CHECK-LABEL: test_vst1q_lane_s16:484; CHECK: // %bb.0: // %entry485; CHECK-NEXT: st1 { v0.h }[7], [x0]486; CHECK-NEXT: ret487entry:488 %0 = extractelement <8 x i16> %b, i32 7489 store i16 %0, ptr %a, align 2490 ret void491}492 493define void @test_vst1q_lane0_s16(ptr %a, <8 x i16> %b) {494; CHECK-LABEL: test_vst1q_lane0_s16:495; CHECK: // %bb.0: // %entry496; CHECK-NEXT: str h0, [x0]497; CHECK-NEXT: ret498entry:499 %0 = extractelement <8 x i16> %b, i32 0500 store i16 %0, ptr %a, align 2501 ret void502}503 504define void @test_vst1q_lane_s32(ptr %a, <4 x i32> %b) {505; CHECK-LABEL: test_vst1q_lane_s32:506; CHECK: // %bb.0: // %entry507; CHECK-NEXT: st1 { v0.s }[3], [x0]508; CHECK-NEXT: ret509entry:510 %0 = extractelement <4 x i32> %b, i32 3511 store i32 %0, ptr %a, align 4512 ret void513}514 515define void @test_vst1q_lane0_s32(ptr %a, <4 x i32> %b) {516; CHECK-LABEL: test_vst1q_lane0_s32:517; CHECK: // %bb.0: // %entry518; CHECK-NEXT: str s0, [x0]519; CHECK-NEXT: ret520entry:521 %0 = extractelement <4 x i32> %b, i32 0522 store i32 %0, ptr %a, align 4523 ret void524}525 526define void @test_vst1q_lane_s64(ptr %a, <2 x i64> %b) {527; CHECK-LABEL: test_vst1q_lane_s64:528; CHECK: // %bb.0: // %entry529; CHECK-NEXT: st1 { v0.d }[1], [x0]530; CHECK-NEXT: ret531entry:532 %0 = extractelement <2 x i64> %b, i32 1533 store i64 %0, ptr %a, align 8534 ret void535}536 537define void @test_vst1q_lane0_s64(ptr %a, <2 x i64> %b) {538; CHECK-LABEL: test_vst1q_lane0_s64:539; CHECK: // %bb.0: // %entry540; CHECK-NEXT: str d0, [x0]541; CHECK-NEXT: ret542entry:543 %0 = extractelement <2 x i64> %b, i32 0544 store i64 %0, ptr %a, align 8545 ret void546}547 548define void @test_vst1q_lane_f32(ptr %a, <4 x float> %b) {549; CHECK-LABEL: test_vst1q_lane_f32:550; CHECK: // %bb.0: // %entry551; CHECK-NEXT: st1 { v0.s }[3], [x0]552; CHECK-NEXT: ret553entry:554 %0 = extractelement <4 x float> %b, i32 3555 store float %0, ptr %a, align 4556 ret void557}558 559define void @test_vst1q_lane0_f32(ptr %a, <4 x float> %b) {560; CHECK-LABEL: test_vst1q_lane0_f32:561; CHECK: // %bb.0: // %entry562; CHECK-NEXT: str s0, [x0]563; CHECK-NEXT: ret564entry:565 %0 = extractelement <4 x float> %b, i32 0566 store float %0, ptr %a, align 4567 ret void568}569 570define void @test_vst1q_lane_f64(ptr %a, <2 x double> %b) {571; CHECK-LABEL: test_vst1q_lane_f64:572; CHECK: // %bb.0: // %entry573; CHECK-NEXT: st1 { v0.d }[1], [x0]574; CHECK-NEXT: ret575entry:576 %0 = extractelement <2 x double> %b, i32 1577 store double %0, ptr %a, align 8578 ret void579}580 581define void @test_vst1q_lane0_f64(ptr %a, <2 x double> %b) {582; CHECK-LABEL: test_vst1q_lane0_f64:583; CHECK: // %bb.0: // %entry584; CHECK-NEXT: str d0, [x0]585; CHECK-NEXT: ret586entry:587 %0 = extractelement <2 x double> %b, i32 0588 store double %0, ptr %a, align 8589 ret void590}591 592define void @test_vst1_lane_s8(ptr %a, <8 x i8> %b) {593; CHECK-LABEL: test_vst1_lane_s8:594; CHECK: // %bb.0: // %entry595; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0596; CHECK-NEXT: st1 { v0.b }[7], [x0]597; CHECK-NEXT: ret598entry:599 %0 = extractelement <8 x i8> %b, i32 7600 store i8 %0, ptr %a, align 1601 ret void602}603 604define void @test_vst1_lane_s16(ptr %a, <4 x i16> %b) {605; CHECK-LABEL: test_vst1_lane_s16:606; CHECK: // %bb.0: // %entry607; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0608; CHECK-NEXT: st1 { v0.h }[3], [x0]609; CHECK-NEXT: ret610entry:611 %0 = extractelement <4 x i16> %b, i32 3612 store i16 %0, ptr %a, align 2613 ret void614}615 616define void @test_vst1_lane0_s16(ptr %a, <4 x i16> %b) {617; CHECK-GI-LABEL: test_vst1_lane0_s16:618; CHECK-GI: // %bb.0: // %entry619; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0620; CHECK-GI-NEXT: str h0, [x0]621; CHECK-GI-NEXT: ret622;623; CHECK-SD-LABEL: test_vst1_lane0_s16:624; CHECK-SD: // %bb.0: // %entry625; CHECK-SD-NEXT: str h0, [x0]626; CHECK-SD-NEXT: ret627entry:628 %0 = extractelement <4 x i16> %b, i32 0629 store i16 %0, ptr %a, align 2630 ret void631}632 633define void @test_vst1_lane_s32(ptr %a, <2 x i32> %b) {634; CHECK-LABEL: test_vst1_lane_s32:635; CHECK: // %bb.0: // %entry636; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0637; CHECK-NEXT: st1 { v0.s }[1], [x0]638; CHECK-NEXT: ret639entry:640 %0 = extractelement <2 x i32> %b, i32 1641 store i32 %0, ptr %a, align 4642 ret void643}644 645define void @test_vst1_lane0_s32(ptr %a, <2 x i32> %b) {646; CHECK-GI-LABEL: test_vst1_lane0_s32:647; CHECK-GI: // %bb.0: // %entry648; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0649; CHECK-GI-NEXT: str s0, [x0]650; CHECK-GI-NEXT: ret651;652; CHECK-SD-LABEL: test_vst1_lane0_s32:653; CHECK-SD: // %bb.0: // %entry654; CHECK-SD-NEXT: str s0, [x0]655; CHECK-SD-NEXT: ret656entry:657 %0 = extractelement <2 x i32> %b, i32 0658 store i32 %0, ptr %a, align 4659 ret void660}661 662define void @test_vst1_lane_s64(ptr %a, <1 x i64> %b) {663; CHECK-LABEL: test_vst1_lane_s64:664; CHECK: // %bb.0: // %entry665; CHECK-NEXT: str d0, [x0]666; CHECK-NEXT: ret667entry:668 %0 = extractelement <1 x i64> %b, i32 0669 store i64 %0, ptr %a, align 8670 ret void671}672 673define void @test_vst1_lane_f32(ptr %a, <2 x float> %b) {674; CHECK-LABEL: test_vst1_lane_f32:675; CHECK: // %bb.0: // %entry676; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0677; CHECK-NEXT: st1 { v0.s }[1], [x0]678; CHECK-NEXT: ret679entry:680 %0 = extractelement <2 x float> %b, i32 1681 store float %0, ptr %a, align 4682 ret void683}684 685define void @test_vst1_lane0_f32(ptr %a, <2 x float> %b) {686; CHECK-GI-LABEL: test_vst1_lane0_f32:687; CHECK-GI: // %bb.0: // %entry688; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0689; CHECK-GI-NEXT: str s0, [x0]690; CHECK-GI-NEXT: ret691;692; CHECK-SD-LABEL: test_vst1_lane0_f32:693; CHECK-SD: // %bb.0: // %entry694; CHECK-SD-NEXT: str s0, [x0]695; CHECK-SD-NEXT: ret696entry:697 %0 = extractelement <2 x float> %b, i32 0698 store float %0, ptr %a, align 4699 ret void700}701 702define void @test_vst1_lane_f64(ptr %a, <1 x double> %b) {703; CHECK-LABEL: test_vst1_lane_f64:704; CHECK: // %bb.0: // %entry705; CHECK-NEXT: str d0, [x0]706; CHECK-NEXT: ret707entry:708 %0 = extractelement <1 x double> %b, i32 0709 store double %0, ptr %a, align 8710 ret void711}712