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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s3 4define <8 x i8> @test_vshr_n_s8(<8 x i8> %a) {5; CHECK-LABEL: test_vshr_n_s8:6; CHECK: // %bb.0:7; CHECK-NEXT: sshr v0.8b, v0.8b, #38; CHECK-NEXT: ret9 %vshr_n = ashr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>10 ret <8 x i8> %vshr_n11}12 13define <4 x i16> @test_vshr_n_s16(<4 x i16> %a) {14; CHECK-LABEL: test_vshr_n_s16:15; CHECK: // %bb.0:16; CHECK-NEXT: sshr v0.4h, v0.4h, #317; CHECK-NEXT: ret18 %vshr_n = ashr <4 x i16> %a, <i16 3, i16 3, i16 3, i16 3>19 ret <4 x i16> %vshr_n20}21 22define <2 x i32> @test_vshr_n_s32(<2 x i32> %a) {23; CHECK-LABEL: test_vshr_n_s32:24; CHECK: // %bb.0:25; CHECK-NEXT: sshr v0.2s, v0.2s, #326; CHECK-NEXT: ret27 %vshr_n = ashr <2 x i32> %a, <i32 3, i32 3>28 ret <2 x i32> %vshr_n29}30 31define <16 x i8> @test_vshrq_n_s8(<16 x i8> %a) {32; CHECK-LABEL: test_vshrq_n_s8:33; CHECK: // %bb.0:34; CHECK-NEXT: sshr v0.16b, v0.16b, #335; CHECK-NEXT: ret36 %vshr_n = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>37 ret <16 x i8> %vshr_n38}39 40define <8 x i16> @test_vshrq_n_s16(<8 x i16> %a) {41; CHECK-LABEL: test_vshrq_n_s16:42; CHECK: // %bb.0:43; CHECK-NEXT: sshr v0.8h, v0.8h, #344; CHECK-NEXT: ret45 %vshr_n = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>46 ret <8 x i16> %vshr_n47}48 49define <4 x i32> @test_vshrq_n_s32(<4 x i32> %a) {50; CHECK-LABEL: test_vshrq_n_s32:51; CHECK: // %bb.0:52; CHECK-NEXT: sshr v0.4s, v0.4s, #353; CHECK-NEXT: ret54 %vshr_n = ashr <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>55 ret <4 x i32> %vshr_n56}57 58define <2 x i64> @test_vshrq_n_s64(<2 x i64> %a) {59; CHECK-LABEL: test_vshrq_n_s64:60; CHECK: // %bb.0:61; CHECK-NEXT: sshr v0.2d, v0.2d, #362; CHECK-NEXT: ret63 %vshr_n = ashr <2 x i64> %a, <i64 3, i64 3>64 ret <2 x i64> %vshr_n65}66 67define <8 x i8> @test_vshr_n_u8(<8 x i8> %a) {68; CHECK-LABEL: test_vshr_n_u8:69; CHECK: // %bb.0:70; CHECK-NEXT: ushr v0.8b, v0.8b, #371; CHECK-NEXT: ret72 %vshr_n = lshr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>73 ret <8 x i8> %vshr_n74}75 76define <4 x i16> @test_vshr_n_u16(<4 x i16> %a) {77; CHECK-LABEL: test_vshr_n_u16:78; CHECK: // %bb.0:79; CHECK-NEXT: ushr v0.4h, v0.4h, #380; CHECK-NEXT: ret81 %vshr_n = lshr <4 x i16> %a, <i16 3, i16 3, i16 3, i16 3>82 ret <4 x i16> %vshr_n83}84 85define <2 x i32> @test_vshr_n_u32(<2 x i32> %a) {86; CHECK-LABEL: test_vshr_n_u32:87; CHECK: // %bb.0:88; CHECK-NEXT: ushr v0.2s, v0.2s, #389; CHECK-NEXT: ret90 %vshr_n = lshr <2 x i32> %a, <i32 3, i32 3>91 ret <2 x i32> %vshr_n92}93 94define <16 x i8> @test_vshrq_n_u8(<16 x i8> %a) {95; CHECK-LABEL: test_vshrq_n_u8:96; CHECK: // %bb.0:97; CHECK-NEXT: ushr v0.16b, v0.16b, #398; CHECK-NEXT: ret99 %vshr_n = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>100 ret <16 x i8> %vshr_n101}102 103define <8 x i16> @test_vshrq_n_u16(<8 x i16> %a) {104; CHECK-LABEL: test_vshrq_n_u16:105; CHECK: // %bb.0:106; CHECK-NEXT: ushr v0.8h, v0.8h, #3107; CHECK-NEXT: ret108 %vshr_n = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>109 ret <8 x i16> %vshr_n110}111 112define <4 x i32> @test_vshrq_n_u32(<4 x i32> %a) {113; CHECK-LABEL: test_vshrq_n_u32:114; CHECK: // %bb.0:115; CHECK-NEXT: ushr v0.4s, v0.4s, #3116; CHECK-NEXT: ret117 %vshr_n = lshr <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>118 ret <4 x i32> %vshr_n119}120 121define <2 x i64> @test_vshrq_n_u64(<2 x i64> %a) {122; CHECK-LABEL: test_vshrq_n_u64:123; CHECK: // %bb.0:124; CHECK-NEXT: ushr v0.2d, v0.2d, #3125; CHECK-NEXT: ret126 %vshr_n = lshr <2 x i64> %a, <i64 3, i64 3>127 ret <2 x i64> %vshr_n128}129 130define <8 x i8> @test_vsra_n_s8(<8 x i8> %a, <8 x i8> %b) {131; CHECK-LABEL: test_vsra_n_s8:132; CHECK: // %bb.0:133; CHECK-NEXT: ssra v0.8b, v1.8b, #3134; CHECK-NEXT: ret135 %vsra_n = ashr <8 x i8> %b, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>136 %1 = add <8 x i8> %vsra_n, %a137 ret <8 x i8> %1138}139 140define <4 x i16> @test_vsra_n_s16(<4 x i16> %a, <4 x i16> %b) {141; CHECK-LABEL: test_vsra_n_s16:142; CHECK: // %bb.0:143; CHECK-NEXT: ssra v0.4h, v1.4h, #3144; CHECK-NEXT: ret145 %vsra_n = ashr <4 x i16> %b, <i16 3, i16 3, i16 3, i16 3>146 %1 = add <4 x i16> %vsra_n, %a147 ret <4 x i16> %1148}149 150define <2 x i32> @test_vsra_n_s32(<2 x i32> %a, <2 x i32> %b) {151; CHECK-LABEL: test_vsra_n_s32:152; CHECK: // %bb.0:153; CHECK-NEXT: ssra v0.2s, v1.2s, #3154; CHECK-NEXT: ret155 %vsra_n = ashr <2 x i32> %b, <i32 3, i32 3>156 %1 = add <2 x i32> %vsra_n, %a157 ret <2 x i32> %1158}159 160define <16 x i8> @test_vsraq_n_s8(<16 x i8> %a, <16 x i8> %b) {161; CHECK-LABEL: test_vsraq_n_s8:162; CHECK: // %bb.0:163; CHECK-NEXT: ssra v0.16b, v1.16b, #3164; CHECK-NEXT: ret165 %vsra_n = ashr <16 x i8> %b, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>166 %1 = add <16 x i8> %vsra_n, %a167 ret <16 x i8> %1168}169 170define <8 x i16> @test_vsraq_n_s16(<8 x i16> %a, <8 x i16> %b) {171; CHECK-LABEL: test_vsraq_n_s16:172; CHECK: // %bb.0:173; CHECK-NEXT: ssra v0.8h, v1.8h, #3174; CHECK-NEXT: ret175 %vsra_n = ashr <8 x i16> %b, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>176 %1 = add <8 x i16> %vsra_n, %a177 ret <8 x i16> %1178}179 180define <4 x i32> @test_vsraq_n_s32(<4 x i32> %a, <4 x i32> %b) {181; CHECK-LABEL: test_vsraq_n_s32:182; CHECK: // %bb.0:183; CHECK-NEXT: ssra v0.4s, v1.4s, #3184; CHECK-NEXT: ret185 %vsra_n = ashr <4 x i32> %b, <i32 3, i32 3, i32 3, i32 3>186 %1 = add <4 x i32> %vsra_n, %a187 ret <4 x i32> %1188}189 190define <2 x i64> @test_vsraq_n_s64(<2 x i64> %a, <2 x i64> %b) {191; CHECK-LABEL: test_vsraq_n_s64:192; CHECK: // %bb.0:193; CHECK-NEXT: ssra v0.2d, v1.2d, #3194; CHECK-NEXT: ret195 %vsra_n = ashr <2 x i64> %b, <i64 3, i64 3>196 %1 = add <2 x i64> %vsra_n, %a197 ret <2 x i64> %1198}199 200define <8 x i8> @test_vsra_n_u8(<8 x i8> %a, <8 x i8> %b) {201; CHECK-LABEL: test_vsra_n_u8:202; CHECK: // %bb.0:203; CHECK-NEXT: usra v0.8b, v1.8b, #3204; CHECK-NEXT: ret205 %vsra_n = lshr <8 x i8> %b, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>206 %1 = add <8 x i8> %vsra_n, %a207 ret <8 x i8> %1208}209 210define <4 x i16> @test_vsra_n_u16(<4 x i16> %a, <4 x i16> %b) {211; CHECK-LABEL: test_vsra_n_u16:212; CHECK: // %bb.0:213; CHECK-NEXT: usra v0.4h, v1.4h, #3214; CHECK-NEXT: ret215 %vsra_n = lshr <4 x i16> %b, <i16 3, i16 3, i16 3, i16 3>216 %1 = add <4 x i16> %vsra_n, %a217 ret <4 x i16> %1218}219 220define <2 x i32> @test_vsra_n_u32(<2 x i32> %a, <2 x i32> %b) {221; CHECK-LABEL: test_vsra_n_u32:222; CHECK: // %bb.0:223; CHECK-NEXT: usra v0.2s, v1.2s, #3224; CHECK-NEXT: ret225 %vsra_n = lshr <2 x i32> %b, <i32 3, i32 3>226 %1 = add <2 x i32> %vsra_n, %a227 ret <2 x i32> %1228}229 230define <16 x i8> @test_vsraq_n_u8(<16 x i8> %a, <16 x i8> %b) {231; CHECK-LABEL: test_vsraq_n_u8:232; CHECK: // %bb.0:233; CHECK-NEXT: usra v0.16b, v1.16b, #3234; CHECK-NEXT: ret235 %vsra_n = lshr <16 x i8> %b, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>236 %1 = add <16 x i8> %vsra_n, %a237 ret <16 x i8> %1238}239 240define <8 x i16> @test_vsraq_n_u16(<8 x i16> %a, <8 x i16> %b) {241; CHECK-LABEL: test_vsraq_n_u16:242; CHECK: // %bb.0:243; CHECK-NEXT: usra v0.8h, v1.8h, #3244; CHECK-NEXT: ret245 %vsra_n = lshr <8 x i16> %b, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>246 %1 = add <8 x i16> %vsra_n, %a247 ret <8 x i16> %1248}249 250define <4 x i32> @test_vsraq_n_u32(<4 x i32> %a, <4 x i32> %b) {251; CHECK-LABEL: test_vsraq_n_u32:252; CHECK: // %bb.0:253; CHECK-NEXT: usra v0.4s, v1.4s, #3254; CHECK-NEXT: ret255 %vsra_n = lshr <4 x i32> %b, <i32 3, i32 3, i32 3, i32 3>256 %1 = add <4 x i32> %vsra_n, %a257 ret <4 x i32> %1258}259 260define <2 x i64> @test_vsraq_n_u64(<2 x i64> %a, <2 x i64> %b) {261; CHECK-LABEL: test_vsraq_n_u64:262; CHECK: // %bb.0:263; CHECK-NEXT: usra v0.2d, v1.2d, #3264; CHECK-NEXT: ret265 %vsra_n = lshr <2 x i64> %b, <i64 3, i64 3>266 %1 = add <2 x i64> %vsra_n, %a267 ret <2 x i64> %1268}269 270define <8 x i8> @test_vshrn_n_s16(<8 x i16> %a) {271; CHECK-LABEL: test_vshrn_n_s16:272; CHECK: // %bb.0:273; CHECK-NEXT: shrn v0.8b, v0.8h, #3274; CHECK-NEXT: ret275 %1 = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>276 %vshrn_n = trunc <8 x i16> %1 to <8 x i8>277 ret <8 x i8> %vshrn_n278}279 280define <4 x i16> @test_vshrn_n_s32(<4 x i32> %a) {281; CHECK-LABEL: test_vshrn_n_s32:282; CHECK: // %bb.0:283; CHECK-NEXT: shrn v0.4h, v0.4s, #9284; CHECK-NEXT: ret285 %1 = ashr <4 x i32> %a, <i32 9, i32 9, i32 9, i32 9>286 %vshrn_n = trunc <4 x i32> %1 to <4 x i16>287 ret <4 x i16> %vshrn_n288}289 290define <2 x i32> @test_vshrn_n_s64(<2 x i64> %a) {291; CHECK-LABEL: test_vshrn_n_s64:292; CHECK: // %bb.0:293; CHECK-NEXT: shrn v0.2s, v0.2d, #19294; CHECK-NEXT: ret295 %1 = ashr <2 x i64> %a, <i64 19, i64 19>296 %vshrn_n = trunc <2 x i64> %1 to <2 x i32>297 ret <2 x i32> %vshrn_n298}299 300define <8 x i8> @test_vshrn_n_u16(<8 x i16> %a) {301; CHECK-LABEL: test_vshrn_n_u16:302; CHECK: // %bb.0:303; CHECK-NEXT: shrn v0.8b, v0.8h, #3304; CHECK-NEXT: ret305 %1 = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>306 %vshrn_n = trunc <8 x i16> %1 to <8 x i8>307 ret <8 x i8> %vshrn_n308}309 310define <4 x i16> @test_vshrn_n_u32(<4 x i32> %a) {311; CHECK-LABEL: test_vshrn_n_u32:312; CHECK: // %bb.0:313; CHECK-NEXT: shrn v0.4h, v0.4s, #9314; CHECK-NEXT: ret315 %1 = lshr <4 x i32> %a, <i32 9, i32 9, i32 9, i32 9>316 %vshrn_n = trunc <4 x i32> %1 to <4 x i16>317 ret <4 x i16> %vshrn_n318}319 320define <2 x i32> @test_vshrn_n_u64(<2 x i64> %a) {321; CHECK-LABEL: test_vshrn_n_u64:322; CHECK: // %bb.0:323; CHECK-NEXT: shrn v0.2s, v0.2d, #19324; CHECK-NEXT: ret325 %1 = lshr <2 x i64> %a, <i64 19, i64 19>326 %vshrn_n = trunc <2 x i64> %1 to <2 x i32>327 ret <2 x i32> %vshrn_n328}329 330define <16 x i8> @test_vshrn_high_n_s16(<8 x i8> %a, <8 x i16> %b) {331; CHECK-LABEL: test_vshrn_high_n_s16:332; CHECK: // %bb.0:333; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0334; CHECK-NEXT: shrn2 v0.16b, v1.8h, #3335; CHECK-NEXT: ret336 %1 = ashr <8 x i16> %b, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>337 %vshrn_n = trunc <8 x i16> %1 to <8 x i8>338 %2 = bitcast <8 x i8> %a to <1 x i64>339 %3 = bitcast <8 x i8> %vshrn_n to <1 x i64>340 %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>341 %4 = bitcast <2 x i64> %shuffle.i to <16 x i8>342 ret <16 x i8> %4343}344 345define <8 x i16> @test_vshrn_high_n_s32(<4 x i16> %a, <4 x i32> %b) {346; CHECK-LABEL: test_vshrn_high_n_s32:347; CHECK: // %bb.0:348; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0349; CHECK-NEXT: shrn2 v0.8h, v1.4s, #9350; CHECK-NEXT: ret351 %1 = ashr <4 x i32> %b, <i32 9, i32 9, i32 9, i32 9>352 %vshrn_n = trunc <4 x i32> %1 to <4 x i16>353 %2 = bitcast <4 x i16> %a to <1 x i64>354 %3 = bitcast <4 x i16> %vshrn_n to <1 x i64>355 %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>356 %4 = bitcast <2 x i64> %shuffle.i to <8 x i16>357 ret <8 x i16> %4358}359 360define <4 x i32> @test_vshrn_high_n_s64(<2 x i32> %a, <2 x i64> %b) {361; CHECK-LABEL: test_vshrn_high_n_s64:362; CHECK: // %bb.0:363; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0364; CHECK-NEXT: shrn2 v0.4s, v1.2d, #19365; CHECK-NEXT: ret366 %1 = bitcast <2 x i32> %a to <1 x i64>367 %2 = ashr <2 x i64> %b, <i64 19, i64 19>368 %vshrn_n = trunc <2 x i64> %2 to <2 x i32>369 %3 = bitcast <2 x i32> %vshrn_n to <1 x i64>370 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %3, <2 x i32> <i32 0, i32 1>371 %4 = bitcast <2 x i64> %shuffle.i to <4 x i32>372 ret <4 x i32> %4373}374 375define <16 x i8> @test_vshrn_high_n_u16(<8 x i8> %a, <8 x i16> %b) {376; CHECK-LABEL: test_vshrn_high_n_u16:377; CHECK: // %bb.0:378; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0379; CHECK-NEXT: shrn2 v0.16b, v1.8h, #3380; CHECK-NEXT: ret381 %1 = lshr <8 x i16> %b, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>382 %vshrn_n = trunc <8 x i16> %1 to <8 x i8>383 %2 = bitcast <8 x i8> %a to <1 x i64>384 %3 = bitcast <8 x i8> %vshrn_n to <1 x i64>385 %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>386 %4 = bitcast <2 x i64> %shuffle.i to <16 x i8>387 ret <16 x i8> %4388}389 390define <8 x i16> @test_vshrn_high_n_u32(<4 x i16> %a, <4 x i32> %b) {391; CHECK-LABEL: test_vshrn_high_n_u32:392; CHECK: // %bb.0:393; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0394; CHECK-NEXT: shrn2 v0.8h, v1.4s, #9395; CHECK-NEXT: ret396 %1 = lshr <4 x i32> %b, <i32 9, i32 9, i32 9, i32 9>397 %vshrn_n = trunc <4 x i32> %1 to <4 x i16>398 %2 = bitcast <4 x i16> %a to <1 x i64>399 %3 = bitcast <4 x i16> %vshrn_n to <1 x i64>400 %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>401 %4 = bitcast <2 x i64> %shuffle.i to <8 x i16>402 ret <8 x i16> %4403}404 405define <4 x i32> @test_vshrn_high_n_u64(<2 x i32> %a, <2 x i64> %b) {406; CHECK-LABEL: test_vshrn_high_n_u64:407; CHECK: // %bb.0:408; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0409; CHECK-NEXT: shrn2 v0.4s, v1.2d, #19410; CHECK-NEXT: ret411 %1 = bitcast <2 x i32> %a to <1 x i64>412 %2 = lshr <2 x i64> %b, <i64 19, i64 19>413 %vshrn_n = trunc <2 x i64> %2 to <2 x i32>414 %3 = bitcast <2 x i32> %vshrn_n to <1 x i64>415 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %3, <2 x i32> <i32 0, i32 1>416 %4 = bitcast <2 x i64> %shuffle.i to <4 x i32>417 ret <4 x i32> %4418}419 420define <16 x i8> @test_vqshrun_high_n_s16(<8 x i8> %a, <8 x i16> %b) {421; CHECK-LABEL: test_vqshrun_high_n_s16:422; CHECK: // %bb.0:423; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0424; CHECK-NEXT: sqshrun2 v0.16b, v1.8h, #3425; CHECK-NEXT: ret426 %vqshrun = tail call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %b, i32 3)427 %1 = bitcast <8 x i8> %a to <1 x i64>428 %2 = bitcast <8 x i8> %vqshrun to <1 x i64>429 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>430 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>431 ret <16 x i8> %3432}433 434define <8 x i16> @test_vqshrun_high_n_s32(<4 x i16> %a, <4 x i32> %b) {435; CHECK-LABEL: test_vqshrun_high_n_s32:436; CHECK: // %bb.0:437; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0438; CHECK-NEXT: sqshrun2 v0.8h, v1.4s, #9439; CHECK-NEXT: ret440 %vqshrun = tail call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %b, i32 9)441 %1 = bitcast <4 x i16> %a to <1 x i64>442 %2 = bitcast <4 x i16> %vqshrun to <1 x i64>443 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>444 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>445 ret <8 x i16> %3446}447 448define <4 x i32> @test_vqshrun_high_n_s64(<2 x i32> %a, <2 x i64> %b) {449; CHECK-LABEL: test_vqshrun_high_n_s64:450; CHECK: // %bb.0:451; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0452; CHECK-NEXT: sqshrun2 v0.4s, v1.2d, #19453; CHECK-NEXT: ret454 %1 = bitcast <2 x i32> %a to <1 x i64>455 %vqshrun = tail call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %b, i32 19)456 %2 = bitcast <2 x i32> %vqshrun to <1 x i64>457 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>458 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>459 ret <4 x i32> %3460}461 462define <16 x i8> @test_vrshrn_high_n_s16(<8 x i8> %a, <8 x i16> %b) {463; CHECK-LABEL: test_vrshrn_high_n_s16:464; CHECK: // %bb.0:465; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0466; CHECK-NEXT: rshrn2 v0.16b, v1.8h, #3467; CHECK-NEXT: ret468 %vrshrn = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %b, i32 3)469 %1 = bitcast <8 x i8> %a to <1 x i64>470 %2 = bitcast <8 x i8> %vrshrn to <1 x i64>471 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>472 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>473 ret <16 x i8> %3474}475 476define <8 x i16> @test_vrshrn_high_n_s32(<4 x i16> %a, <4 x i32> %b) {477; CHECK-LABEL: test_vrshrn_high_n_s32:478; CHECK: // %bb.0:479; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0480; CHECK-NEXT: rshrn2 v0.8h, v1.4s, #9481; CHECK-NEXT: ret482 %vrshrn = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %b, i32 9)483 %1 = bitcast <4 x i16> %a to <1 x i64>484 %2 = bitcast <4 x i16> %vrshrn to <1 x i64>485 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>486 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>487 ret <8 x i16> %3488}489 490define <4 x i32> @test_vrshrn_high_n_s64(<2 x i32> %a, <2 x i64> %b) {491; CHECK-LABEL: test_vrshrn_high_n_s64:492; CHECK: // %bb.0:493; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0494; CHECK-NEXT: rshrn2 v0.4s, v1.2d, #19495; CHECK-NEXT: ret496 %1 = bitcast <2 x i32> %a to <1 x i64>497 %vrshrn = tail call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %b, i32 19)498 %2 = bitcast <2 x i32> %vrshrn to <1 x i64>499 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>500 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>501 ret <4 x i32> %3502}503 504define <16 x i8> @test_vqrshrun_high_n_s16(<8 x i8> %a, <8 x i16> %b) {505; CHECK-LABEL: test_vqrshrun_high_n_s16:506; CHECK: // %bb.0:507; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0508; CHECK-NEXT: sqrshrun2 v0.16b, v1.8h, #3509; CHECK-NEXT: ret510 %vqrshrun = tail call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %b, i32 3)511 %1 = bitcast <8 x i8> %a to <1 x i64>512 %2 = bitcast <8 x i8> %vqrshrun to <1 x i64>513 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>514 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>515 ret <16 x i8> %3516}517 518define <8 x i16> @test_vqrshrun_high_n_s32(<4 x i16> %a, <4 x i32> %b) {519; CHECK-LABEL: test_vqrshrun_high_n_s32:520; CHECK: // %bb.0:521; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0522; CHECK-NEXT: sqrshrun2 v0.8h, v1.4s, #9523; CHECK-NEXT: ret524 %vqrshrun = tail call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %b, i32 9)525 %1 = bitcast <4 x i16> %a to <1 x i64>526 %2 = bitcast <4 x i16> %vqrshrun to <1 x i64>527 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>528 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>529 ret <8 x i16> %3530}531 532define <4 x i32> @test_vqrshrun_high_n_s64(<2 x i32> %a, <2 x i64> %b) {533; CHECK-LABEL: test_vqrshrun_high_n_s64:534; CHECK: // %bb.0:535; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0536; CHECK-NEXT: sqrshrun2 v0.4s, v1.2d, #19537; CHECK-NEXT: ret538 %1 = bitcast <2 x i32> %a to <1 x i64>539 %vqrshrun = tail call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %b, i32 19)540 %2 = bitcast <2 x i32> %vqrshrun to <1 x i64>541 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>542 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>543 ret <4 x i32> %3544}545 546define <16 x i8> @test_vqshrn_high_n_s16(<8 x i8> %a, <8 x i16> %b) {547; CHECK-LABEL: test_vqshrn_high_n_s16:548; CHECK: // %bb.0:549; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0550; CHECK-NEXT: sqshrn2 v0.16b, v1.8h, #3551; CHECK-NEXT: ret552 %vqshrn = tail call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %b, i32 3)553 %1 = bitcast <8 x i8> %a to <1 x i64>554 %2 = bitcast <8 x i8> %vqshrn to <1 x i64>555 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>556 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>557 ret <16 x i8> %3558}559 560define <8 x i16> @test_vqshrn_high_n_s32(<4 x i16> %a, <4 x i32> %b) {561; CHECK-LABEL: test_vqshrn_high_n_s32:562; CHECK: // %bb.0:563; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0564; CHECK-NEXT: sqshrn2 v0.8h, v1.4s, #9565; CHECK-NEXT: ret566 %vqshrn = tail call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %b, i32 9)567 %1 = bitcast <4 x i16> %a to <1 x i64>568 %2 = bitcast <4 x i16> %vqshrn to <1 x i64>569 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>570 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>571 ret <8 x i16> %3572}573 574define <4 x i32> @test_vqshrn_high_n_s64(<2 x i32> %a, <2 x i64> %b) {575; CHECK-LABEL: test_vqshrn_high_n_s64:576; CHECK: // %bb.0:577; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0578; CHECK-NEXT: sqshrn2 v0.4s, v1.2d, #19579; CHECK-NEXT: ret580 %1 = bitcast <2 x i32> %a to <1 x i64>581 %vqshrn = tail call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %b, i32 19)582 %2 = bitcast <2 x i32> %vqshrn to <1 x i64>583 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>584 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>585 ret <4 x i32> %3586}587 588define <16 x i8> @test_vqshrn_high_n_u16(<8 x i8> %a, <8 x i16> %b) {589; CHECK-LABEL: test_vqshrn_high_n_u16:590; CHECK: // %bb.0:591; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0592; CHECK-NEXT: uqshrn2 v0.16b, v1.8h, #3593; CHECK-NEXT: ret594 %vqshrn = tail call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %b, i32 3)595 %1 = bitcast <8 x i8> %a to <1 x i64>596 %2 = bitcast <8 x i8> %vqshrn to <1 x i64>597 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>598 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>599 ret <16 x i8> %3600}601 602define <8 x i16> @test_vqshrn_high_n_u32(<4 x i16> %a, <4 x i32> %b) {603; CHECK-LABEL: test_vqshrn_high_n_u32:604; CHECK: // %bb.0:605; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0606; CHECK-NEXT: uqshrn2 v0.8h, v1.4s, #9607; CHECK-NEXT: ret608 %vqshrn = tail call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %b, i32 9)609 %1 = bitcast <4 x i16> %a to <1 x i64>610 %2 = bitcast <4 x i16> %vqshrn to <1 x i64>611 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>612 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>613 ret <8 x i16> %3614}615 616define <4 x i32> @test_vqshrn_high_n_u64(<2 x i32> %a, <2 x i64> %b) {617; CHECK-LABEL: test_vqshrn_high_n_u64:618; CHECK: // %bb.0:619; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0620; CHECK-NEXT: uqshrn2 v0.4s, v1.2d, #19621; CHECK-NEXT: ret622 %1 = bitcast <2 x i32> %a to <1 x i64>623 %vqshrn = tail call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %b, i32 19)624 %2 = bitcast <2 x i32> %vqshrn to <1 x i64>625 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>626 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>627 ret <4 x i32> %3628}629 630define <16 x i8> @test_vqrshrn_high_n_s16(<8 x i8> %a, <8 x i16> %b) {631; CHECK-LABEL: test_vqrshrn_high_n_s16:632; CHECK: // %bb.0:633; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0634; CHECK-NEXT: sqrshrn2 v0.16b, v1.8h, #3635; CHECK-NEXT: ret636 %vqrshrn = tail call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %b, i32 3)637 %1 = bitcast <8 x i8> %a to <1 x i64>638 %2 = bitcast <8 x i8> %vqrshrn to <1 x i64>639 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>640 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>641 ret <16 x i8> %3642}643 644define <8 x i16> @test_vqrshrn_high_n_s32(<4 x i16> %a, <4 x i32> %b) {645; CHECK-LABEL: test_vqrshrn_high_n_s32:646; CHECK: // %bb.0:647; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0648; CHECK-NEXT: sqrshrn2 v0.8h, v1.4s, #9649; CHECK-NEXT: ret650 %vqrshrn = tail call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %b, i32 9)651 %1 = bitcast <4 x i16> %a to <1 x i64>652 %2 = bitcast <4 x i16> %vqrshrn to <1 x i64>653 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>654 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>655 ret <8 x i16> %3656}657 658define <4 x i32> @test_vqrshrn_high_n_s64(<2 x i32> %a, <2 x i64> %b) {659; CHECK-LABEL: test_vqrshrn_high_n_s64:660; CHECK: // %bb.0:661; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0662; CHECK-NEXT: sqrshrn2 v0.4s, v1.2d, #19663; CHECK-NEXT: ret664 %1 = bitcast <2 x i32> %a to <1 x i64>665 %vqrshrn = tail call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %b, i32 19)666 %2 = bitcast <2 x i32> %vqrshrn to <1 x i64>667 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>668 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>669 ret <4 x i32> %3670}671 672define <16 x i8> @test_vqrshrn_high_n_u16(<8 x i8> %a, <8 x i16> %b) {673; CHECK-LABEL: test_vqrshrn_high_n_u16:674; CHECK: // %bb.0:675; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0676; CHECK-NEXT: uqrshrn2 v0.16b, v1.8h, #3677; CHECK-NEXT: ret678 %vqrshrn = tail call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %b, i32 3)679 %1 = bitcast <8 x i8> %a to <1 x i64>680 %2 = bitcast <8 x i8> %vqrshrn to <1 x i64>681 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>682 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>683 ret <16 x i8> %3684}685 686define <8 x i16> @test_vqrshrn_high_n_u32(<4 x i16> %a, <4 x i32> %b) {687; CHECK-LABEL: test_vqrshrn_high_n_u32:688; CHECK: // %bb.0:689; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0690; CHECK-NEXT: uqrshrn2 v0.8h, v1.4s, #9691; CHECK-NEXT: ret692 %vqrshrn = tail call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %b, i32 9)693 %1 = bitcast <4 x i16> %a to <1 x i64>694 %2 = bitcast <4 x i16> %vqrshrn to <1 x i64>695 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>696 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>697 ret <8 x i16> %3698}699 700define <4 x i32> @test_vqrshrn_high_n_u64(<2 x i32> %a, <2 x i64> %b) {701; CHECK-LABEL: test_vqrshrn_high_n_u64:702; CHECK: // %bb.0:703; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0704; CHECK-NEXT: uqrshrn2 v0.4s, v1.2d, #19705; CHECK-NEXT: ret706 %1 = bitcast <2 x i32> %a to <1 x i64>707 %vqrshrn = tail call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %b, i32 19)708 %2 = bitcast <2 x i32> %vqrshrn to <1 x i64>709 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>710 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>711 ret <4 x i32> %3712}713 714 715 716declare <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, i32)717 718declare <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32>, i32)719 720declare <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64>, i32)721 722declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)723 724declare <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32>, i32)725 726declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32)727 728declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32)729 730declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32)731 732declare <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64>, i32)733 734declare <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16>, i32)735 736declare <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32>, i32)737 738declare <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64>, i32)739 740declare <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32)741 742declare <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32>, i32)743 744declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32)745 746declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32)747 748declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32)749 750declare <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64>, i32)751 752declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32)753 754declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32)755 756declare <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64>, i32)757 758declare <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32)759 760declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32)761 762declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32)763 764declare <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32)765 766declare <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32)767 768declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32)769 770declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32)771 772declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32)773 774declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32)775 776declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32)777 778declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32)779 780declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32)781 782define <1 x i64> @test_vcvt_n_s64_f64(<1 x double> %a) {783; CHECK-LABEL: test_vcvt_n_s64_f64:784; CHECK: // %bb.0:785; CHECK-NEXT: fcvtzs d0, d0, #64786; CHECK-NEXT: ret787 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double> %a, i32 64)788 ret <1 x i64> %1789}790 791define <1 x i64> @test_vcvt_n_u64_f64(<1 x double> %a) {792; CHECK-LABEL: test_vcvt_n_u64_f64:793; CHECK: // %bb.0:794; CHECK-NEXT: fcvtzu d0, d0, #64795; CHECK-NEXT: ret796 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double> %a, i32 64)797 ret <1 x i64> %1798}799 800define <1 x double> @test_vcvt_n_f64_s64(<1 x i64> %a) {801; CHECK-LABEL: test_vcvt_n_f64_s64:802; CHECK: // %bb.0:803; CHECK-NEXT: scvtf d0, d0, #64804; CHECK-NEXT: ret805 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64> %a, i32 64)806 ret <1 x double> %1807}808 809define <1 x double> @test_vcvt_n_f64_u64(<1 x i64> %a) {810; CHECK-LABEL: test_vcvt_n_f64_u64:811; CHECK: // %bb.0:812; CHECK-NEXT: ucvtf d0, d0, #64813; CHECK-NEXT: ret814 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64> %a, i32 64)815 ret <1 x double> %1816}817 818declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32)819declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32)820declare <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32)821declare <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)822