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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc %s -o - -verify-machineinstrs -mtriple=arm64-none-linux-gnu | FileCheck %s3 4; This is the analogue of AArch64's file of the same name. It's mostly testing5; some form of correct lowering occurs, the tests are a little artificial but I6; strongly suspect there's room for improved CodeGen (FIXME).7 8define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {9; CHECK-LABEL: test_sext_extr_cmp_0:10; CHECK: // %bb.0:11; CHECK-NEXT: // kill: def $d1 killed $d1 def $q112; CHECK-NEXT: // kill: def $d0 killed $d0 def $q013; CHECK-NEXT: fmov x8, d114; CHECK-NEXT: fmov x9, d015; CHECK-NEXT: cmp x9, x816; CHECK-NEXT: cset w8, ge17; CHECK-NEXT: sbfx x0, x8, #0, #118; CHECK-NEXT: ret19 %1 = icmp sge <1 x i64> %v1, %v220 %2 = extractelement <1 x i1> %1, i32 021 %vget_lane = sext i1 %2 to i6422 ret i64 %vget_lane23}24 25define i64 @test_sext_extr_cmp_1(<1 x double> %v1, <1 x double> %v2) {26; CHECK-LABEL: test_sext_extr_cmp_1:27; CHECK: // %bb.0:28; CHECK-NEXT: fcmp d0, d129; CHECK-NEXT: cset w8, eq30; CHECK-NEXT: sbfx x0, x8, #0, #131; CHECK-NEXT: ret32 %1 = fcmp oeq <1 x double> %v1, %v233 %2 = extractelement <1 x i1> %1, i32 034 %vget_lane = sext i1 %2 to i6435 ret i64 %vget_lane36}37 38define <1 x i64> @test_select_v1i1_0(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {39; CHECK-LABEL: test_select_v1i1_0:40; CHECK: // %bb.0:41; CHECK-NEXT: cmeq d0, d0, d142; CHECK-NEXT: bic v0.8b, v2.8b, v0.8b43; CHECK-NEXT: ret44 %1 = icmp eq <1 x i64> %v1, %v245 %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v346 ret <1 x i64> %res47}48 49define <1 x i64> @test_select_v1i1_1(<1 x double> %v1, <1 x double> %v2, <1 x i64> %v3) {50; CHECK-LABEL: test_select_v1i1_1:51; CHECK: // %bb.0:52; CHECK-NEXT: fcmeq d0, d0, d153; CHECK-NEXT: bic v0.8b, v2.8b, v0.8b54; CHECK-NEXT: ret55 %1 = fcmp oeq <1 x double> %v1, %v256 %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v357 ret <1 x i64> %res58}59 60define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x double> %v3) {61; CHECK-LABEL: test_select_v1i1_2:62; CHECK: // %bb.0:63; CHECK-NEXT: cmeq d0, d0, d164; CHECK-NEXT: bic v0.8b, v2.8b, v0.8b65; CHECK-NEXT: ret66 %1 = icmp eq <1 x i64> %v1, %v267 %res = select <1 x i1> %1, <1 x double> zeroinitializer, <1 x double> %v368 ret <1 x double> %res69}70 71; For v1i64, it's not clear which of the vector or scalar compare is better.72; Let's stick to the vector form, like for all other vector selects fed by a73; scalar setcc. If anything, it exposes more ILP.74define <1 x i64> @test_select_v1i1_3(i64 %lhs, i64 %rhs, <1 x i64> %v3) {75; CHECK-LABEL: test_select_v1i1_3:76; CHECK: // %bb.0:77; CHECK-NEXT: fmov d1, x178; CHECK-NEXT: fmov d2, x079; CHECK-NEXT: cmeq d1, d2, d180; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b81; CHECK-NEXT: ret82 %tst = icmp eq i64 %lhs, %rhs83 %evil = insertelement <1 x i1> undef, i1 %tst, i32 084 %res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v385 ret <1 x i64> %res86}87 88define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) {89; CHECK-LABEL: test_br_extr_cmp:90; CHECK: // %bb.0: // %common.ret91; CHECK-NEXT: // kill: def $d1 killed $d1 def $q192; CHECK-NEXT: // kill: def $d0 killed $d0 def $q093; CHECK-NEXT: fmov x8, d194; CHECK-NEXT: fmov x9, d095; CHECK-NEXT: cmp x9, x896; CHECK-NEXT: cset w0, eq97; CHECK-NEXT: ret98 %1 = icmp eq <1 x i64> %v1, %v299 %2 = extractelement <1 x i1> %1, i32 0100 br i1 %2, label %if.end, label %if.then101 102if.then:103 ret i32 0;104 105if.end:106 ret i32 1;107}108 109 110define <1 x float> @test_vselect_f32(<1 x float> %i105, <1 x float> %in) {111; CHECK-LABEL: test_vselect_f32:112; CHECK: // %bb.0:113; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0114; CHECK-NEXT: fcmp s0, s0115; CHECK-NEXT: cset w8, vs116; CHECK-NEXT: fmov s2, w8117; CHECK-NEXT: shl v2.2s, v2.2s, #31118; CHECK-NEXT: cmlt v2.2s, v2.2s, #0119; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b120; CHECK-NEXT: ret121 %i179 = fcmp uno <1 x float> %i105, zeroinitializer122 %i180 = select <1 x i1> %i179, <1 x float> %in, <1 x float> %i105123 ret <1 x float> %i180124}125 126define <1 x half> @test_vselect_f16(<1 x half> %i105, <1 x half> %in) {127; CHECK-LABEL: test_vselect_f16:128; CHECK: // %bb.0:129; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0130; CHECK-NEXT: fcvt s2, h0131; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1132; CHECK-NEXT: fcmp s2, s2133; CHECK-NEXT: fcsel s0, s1, s0, vs134; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0135; CHECK-NEXT: ret136 %i179 = fcmp uno <1 x half> %i105, zeroinitializer137 %i180 = select <1 x i1> %i179, <1 x half> %in, <1 x half> %i105138 ret <1 x half> %i180139}140 141define <1 x half> @test_select_f16(half %a, half %b, <1 x half> %c, <1 x half> %d ) {142; CHECK-LABEL: test_select_f16:143; CHECK: // %bb.0:144; CHECK-NEXT: fcvt s1, h1145; CHECK-NEXT: fcvt s0, h0146; CHECK-NEXT: // kill: def $h3 killed $h3 def $s3147; CHECK-NEXT: // kill: def $h2 killed $h2 def $s2148; CHECK-NEXT: fcmp s0, s1149; CHECK-NEXT: fcsel s0, s2, s3, eq150; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0151; CHECK-NEXT: ret152 %cmp31 = fcmp oeq half %a, %b153 %e = select i1 %cmp31, <1 x half> %c, <1 x half> %d154 ret <1 x half> %e155}156 157define <1 x i16> @test_vselect_f16_i16(<1 x half> %i105, <1 x half> %in, <1 x i16> %x, <1 x i16> %y) {158; CHECK-LABEL: test_vselect_f16_i16:159; CHECK: // %bb.0:160; CHECK-NEXT: fcvt s0, h0161; CHECK-NEXT: fcmp s0, s0162; CHECK-NEXT: cset w8, vs163; CHECK-NEXT: fmov s0, w8164; CHECK-NEXT: shl v0.4h, v0.4h, #15165; CHECK-NEXT: cmlt v0.4h, v0.4h, #0166; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b167; CHECK-NEXT: ret168 %i179 = fcmp uno <1 x half> %i105, zeroinitializer169 %i180 = select <1 x i1> %i179, <1 x i16> %x, <1 x i16> %y170 ret <1 x i16> %i180171}172 173define <1 x i16> @test_select_f16_i16(half %i105, half %in, <1 x i16> %x, <1 x i16> %y) {174; CHECK-LABEL: test_select_f16_i16:175; CHECK: // %bb.0:176; CHECK-NEXT: fcvt s0, h0177; CHECK-NEXT: fcmeq s0, s0, s0178; CHECK-NEXT: mvn v0.16b, v0.16b179; CHECK-NEXT: dup v0.4h, v0.h[0]180; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b181; CHECK-NEXT: ret182 %i179 = fcmp uno half %i105, zeroinitializer183 %i180 = select i1 %i179, <1 x i16> %x, <1 x i16> %y184 ret <1 x i16> %i180185}186 187define <1 x i32> @test_vselect_f16_i32(<1 x half> %i105, <1 x half> %in, <1 x i32> %x, <1 x i32> %y) {188; CHECK-LABEL: test_vselect_f16_i32:189; CHECK: // %bb.0:190; CHECK-NEXT: fcvt s0, h0191; CHECK-NEXT: fcmp s0, s0192; CHECK-NEXT: cset w8, vs193; CHECK-NEXT: fmov s0, w8194; CHECK-NEXT: shl v0.2s, v0.2s, #31195; CHECK-NEXT: cmlt v0.2s, v0.2s, #0196; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b197; CHECK-NEXT: ret198 %i179 = fcmp uno <1 x half> %i105, zeroinitializer199 %i180 = select <1 x i1> %i179, <1 x i32> %x, <1 x i32> %y200 ret <1 x i32> %i180201}202 203define i64 @test_sext_extr_cmp_half(<1 x half> %v1, <1 x half> %v2) {204; CHECK-LABEL: test_sext_extr_cmp_half:205; CHECK: // %bb.0:206; CHECK-NEXT: fcvt s1, h1207; CHECK-NEXT: fcvt s0, h0208; CHECK-NEXT: fcmp s0, s1209; CHECK-NEXT: cset w8, eq210; CHECK-NEXT: sbfx x0, x8, #0, #1211; CHECK-NEXT: ret212 %1 = fcmp oeq <1 x half> %v1, %v2213 %2 = extractelement <1 x i1> %1, i32 0214 %vget_lane = sext i1 %2 to i64215 ret i64 %vget_lane216}217 218define <1 x i64> @test_select_v1i1_half(half %lhs, half %rhs, <1 x i64> %v3) {219; CHECK-LABEL: test_select_v1i1_half:220; CHECK: // %bb.0:221; CHECK-NEXT: fcvt s1, h1222; CHECK-NEXT: fcvt s0, h0223; CHECK-NEXT: fcmp s0, s1224; CHECK-NEXT: csetm x8, eq225; CHECK-NEXT: fmov d0, x8226; CHECK-NEXT: bic v0.8b, v2.8b, v0.8b227; CHECK-NEXT: ret228 %tst = fcmp oeq half %lhs, %rhs229 %evil = insertelement <1 x i1> undef, i1 %tst, i32 0230 %res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v3231 ret <1 x i64> %res232}233 234define i32 @test_br_extr_cmp_half(<1 x half> %v1, <1 x half> %v2) {235; CHECK-LABEL: test_br_extr_cmp_half:236; CHECK: // %bb.0: // %common.ret237; CHECK-NEXT: fcvt s1, h1238; CHECK-NEXT: fcvt s0, h0239; CHECK-NEXT: fcmp s0, s1240; CHECK-NEXT: cset w0, eq241; CHECK-NEXT: ret242 %1 = fcmp oeq <1 x half> %v1, %v2243 %2 = extractelement <1 x i1> %1, i32 0244 br i1 %2, label %if.end, label %if.then245 246if.then:247 ret i32 0;248 249if.end:250 ret i32 1;251}252 253define <1 x i64> @test_zext_half(<1 x half> %v1) {254; CHECK-LABEL: test_zext_half:255; CHECK: // %bb.0:256; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0257; CHECK-NEXT: mov w8, #1 // =0x1258; CHECK-NEXT: fcvtl v0.4s, v0.4h259; CHECK-NEXT: fmov d1, x8260; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0261; CHECK-NEXT: xtn v0.4h, v0.4s262; CHECK-NEXT: and v0.8b, v0.8b, v1.8b263; CHECK-NEXT: ret264 %1 = fcmp ogt <1 x half> %v1, zeroinitializer265 %2 = zext <1 x i1> %1 to <1 x i64>266 ret <1 x i64> %2267}268