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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s3 4define i24 @ldi24(ptr %p) nounwind {5; CHECK-LABEL: ldi24:6; CHECK: // %bb.0:7; CHECK-NEXT: ldrb w8, [x0, #2]8; CHECK-NEXT: ldrh w9, [x0]9; CHECK-NEXT: orr w0, w9, w8, lsl #1610; CHECK-NEXT: ret11 %r = load i24, ptr %p12 ret i24 %r13}14 15define i56 @ldi56(ptr %p) nounwind {16; CHECK-LABEL: ldi56:17; CHECK: // %bb.0:18; CHECK-NEXT: ldrb w8, [x0, #6]19; CHECK-NEXT: ldrh w9, [x0, #4]20; CHECK-NEXT: orr w8, w9, w8, lsl #1621; CHECK-NEXT: ldr w9, [x0]22; CHECK-NEXT: orr x0, x9, x8, lsl #3223; CHECK-NEXT: ret24 %r = load i56, ptr %p25 ret i56 %r26}27 28define i80 @ldi80(ptr %p) nounwind {29; CHECK-LABEL: ldi80:30; CHECK: // %bb.0:31; CHECK-NEXT: ldr x8, [x0]32; CHECK-NEXT: ldrh w1, [x0, #8]33; CHECK-NEXT: mov x0, x834; CHECK-NEXT: ret35 %r = load i80, ptr %p36 ret i80 %r37}38 39define i120 @ldi120(ptr %p) nounwind {40; CHECK-LABEL: ldi120:41; CHECK: // %bb.0:42; CHECK-NEXT: ldrb w8, [x0, #14]43; CHECK-NEXT: ldrh w9, [x0, #12]44; CHECK-NEXT: orr w8, w9, w8, lsl #1645; CHECK-NEXT: ldr w9, [x0, #8]46; CHECK-NEXT: ldr x0, [x0]47; CHECK-NEXT: orr x1, x9, x8, lsl #3248; CHECK-NEXT: ret49 %r = load i120, ptr %p50 ret i120 %r51}52 53define i280 @ldi280(ptr %p) nounwind {54; CHECK-LABEL: ldi280:55; CHECK: // %bb.0:56; CHECK-NEXT: ldrb w9, [x0, #34]57; CHECK-NEXT: ldrh w10, [x0, #32]58; CHECK-NEXT: ldp x8, x1, [x0]59; CHECK-NEXT: ldp x2, x3, [x0, #16]60; CHECK-NEXT: orr x4, x10, x9, lsl #1661; CHECK-NEXT: mov x0, x862; CHECK-NEXT: ret63 %r = load i280, ptr %p64 ret i280 %r65}66 67define void @sti24(ptr %p, i24 %a) nounwind {68; CHECK-LABEL: sti24:69; CHECK: // %bb.0:70; CHECK-NEXT: lsr w8, w1, #1671; CHECK-NEXT: strh w1, [x0]72; CHECK-NEXT: strb w8, [x0, #2]73; CHECK-NEXT: ret74 store i24 %a, ptr %p75 ret void76}77 78define void @sti56(ptr %p, i56 %a) nounwind {79; CHECK-LABEL: sti56:80; CHECK: // %bb.0:81; CHECK-NEXT: lsr x8, x1, #4882; CHECK-NEXT: lsr x9, x1, #3283; CHECK-NEXT: str w1, [x0]84; CHECK-NEXT: strb w8, [x0, #6]85; CHECK-NEXT: strh w9, [x0, #4]86; CHECK-NEXT: ret87 store i56 %a, ptr %p88 ret void89}90 91define void @sti80(ptr %p, i80 %a) nounwind {92; CHECK-LABEL: sti80:93; CHECK: // %bb.0:94; CHECK-NEXT: str x2, [x0]95; CHECK-NEXT: strh w3, [x0, #8]96; CHECK-NEXT: ret97 store i80 %a, ptr %p98 ret void99}100 101define void @sti120(ptr %p, i120 %a) nounwind {102; CHECK-LABEL: sti120:103; CHECK: // %bb.0:104; CHECK-NEXT: lsr x8, x3, #48105; CHECK-NEXT: lsr x9, x3, #32106; CHECK-NEXT: str x2, [x0]107; CHECK-NEXT: str w3, [x0, #8]108; CHECK-NEXT: strb w8, [x0, #14]109; CHECK-NEXT: strh w9, [x0, #12]110; CHECK-NEXT: ret111 store i120 %a, ptr %p112 ret void113}114 115define void @sti280(ptr %p, i280 %a) nounwind {116; CHECK-LABEL: sti280:117; CHECK: // %bb.0:118; CHECK-NEXT: lsr x8, x6, #16119; CHECK-NEXT: stp x4, x5, [x0, #16]120; CHECK-NEXT: stp x2, x3, [x0]121; CHECK-NEXT: strh w6, [x0, #32]122; CHECK-NEXT: strb w8, [x0, #34]123; CHECK-NEXT: ret124 store i280 %a, ptr %p125 ret void126}127 128define void @i56_or(ptr %a) {129; CHECK-LABEL: i56_or:130; CHECK: // %bb.0:131; CHECK-NEXT: ldr w8, [x0]132; CHECK-NEXT: mov x9, x0133; CHECK-NEXT: ldrh w10, [x9, #4]!134; CHECK-NEXT: ldrb w11, [x9, #2]135; CHECK-NEXT: orr w8, w8, #0x180136; CHECK-NEXT: str w8, [x0]137; CHECK-NEXT: orr w8, w10, w11, lsl #16138; CHECK-NEXT: strb w11, [x9, #2]139; CHECK-NEXT: strh w8, [x9]140; CHECK-NEXT: ret141 %aa = load i56, ptr %a, align 1142 %b = or i56 %aa, 384143 store i56 %b, ptr %a, align 1144 ret void145}146 147define void @i56_and_or(ptr %a) {148; CHECK-LABEL: i56_and_or:149; CHECK: // %bb.0:150; CHECK-NEXT: ldr w8, [x0]151; CHECK-NEXT: mov x9, x0152; CHECK-NEXT: ldrh w10, [x9, #4]!153; CHECK-NEXT: ldrb w11, [x9, #2]154; CHECK-NEXT: orr w8, w8, #0x180155; CHECK-NEXT: and w8, w8, #0xffffff80156; CHECK-NEXT: strb w11, [x9, #2]157; CHECK-NEXT: str w8, [x0]158; CHECK-NEXT: orr w8, w10, w11, lsl #16159; CHECK-NEXT: strh w8, [x9]160; CHECK-NEXT: ret161 %b = load i56, ptr %a, align 1162 %c = and i56 %b, -128163 %d = or i56 %c, 384164 store i56 %d, ptr %a, align 1165 ret void166}167 168define void @i56_insert_bit(ptr %a, i1 zeroext %bit) {169; CHECK-LABEL: i56_insert_bit:170; CHECK: // %bb.0:171; CHECK-NEXT: mov x8, x0172; CHECK-NEXT: ldr w11, [x0]173; CHECK-NEXT: ldrh w9, [x8, #4]!174; CHECK-NEXT: ldrb w10, [x8, #2]175; CHECK-NEXT: orr w9, w9, w10, lsl #16176; CHECK-NEXT: strb w10, [x8, #2]177; CHECK-NEXT: orr x11, x11, x9, lsl #32178; CHECK-NEXT: strh w9, [x8]179; CHECK-NEXT: and x11, x11, #0xffffffffffffdfff180; CHECK-NEXT: orr w11, w11, w1, lsl #13181; CHECK-NEXT: str w11, [x0]182; CHECK-NEXT: ret183 %extbit = zext i1 %bit to i56184 %b = load i56, ptr %a, align 1185 %extbit.shl = shl nuw nsw i56 %extbit, 13186 %c = and i56 %b, -8193187 %d = or i56 %c, %extbit.shl188 store i56 %d, ptr %a, align 1189 ret void190}191 192