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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple aarch64-none-linux-gnu | FileCheck %s3 4define <16 x i8> @test_combine_v8i16_to_v16i8(<8 x i16> %x, <8 x i16> %y) {5; CHECK-LABEL: test_combine_v8i16_to_v16i8:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: movi v2.2d, #00000000000000008; CHECK-NEXT: raddhn v0.8b, v0.8h, v2.8h9; CHECK-NEXT: raddhn2 v0.16b, v1.8h, v2.8h10; CHECK-NEXT: ret11entry:12 %res = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %x, i32 8)13 %res2 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %y, i32 8)14 %shuffle = shufflevector <8 x i8> %res, <8 x i8> %res2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>15 ret <16 x i8> %shuffle16}17 18define <8 x i16> @test_combine_v4i32_to_v8i16(<4 x i32> %x, <4 x i32> %y) {19; CHECK-LABEL: test_combine_v4i32_to_v8i16:20; CHECK: // %bb.0: // %entry21; CHECK-NEXT: movi v2.2d, #000000000000000022; CHECK-NEXT: raddhn v0.4h, v0.4s, v2.4s23; CHECK-NEXT: raddhn2 v0.8h, v1.4s, v2.4s24; CHECK-NEXT: ret25entry:26 %res = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %x, i32 16)27 %res2 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %y, i32 16)28 %shuffle = shufflevector <4 x i16> %res, <4 x i16> %res2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>29 ret <8 x i16> %shuffle30}31 32define <4 x i32> @test_combine_v2i64_to_v4i32(<2 x i64> %x, <2 x i64> %y) {33; CHECK-LABEL: test_combine_v2i64_to_v4i32:34; CHECK: // %bb.0: // %entry35; CHECK-NEXT: movi v2.2d, #000000000000000036; CHECK-NEXT: raddhn v0.2s, v0.2d, v2.2d37; CHECK-NEXT: raddhn2 v0.4s, v1.2d, v2.2d38; CHECK-NEXT: ret39entry:40 %res = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %x, i32 32)41 %res2 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %y, i32 32)42 %shuffle = shufflevector <2 x i32> %res, <2 x i32> %res2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>43 ret <4 x i32> %shuffle44}45 46declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)47declare <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32>, i32)48declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32)49