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1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-redzone | FileCheck %s2 3define i32 @foo(i32 %a, i32 %b) nounwind ssp {4; CHECK-LABEL: foo:5; CHECK-NOT: sub sp, sp6; CHECK: ret7 %a.addr = alloca i32, align 48 %b.addr = alloca i32, align 49 %x = alloca i32, align 410 store i32 %a, ptr %a.addr, align 411 store i32 %b, ptr %b.addr, align 412 %tmp = load i32, ptr %a.addr, align 413 %tmp1 = load i32, ptr %b.addr, align 414 %add = add nsw i32 %tmp, %tmp115 store i32 %add, ptr %x, align 416 %tmp2 = load i32, ptr %x, align 417 ret i32 %tmp218}19 20; We disable red-zone if NEON is available because copies of Q-regs21; require a spill/fill and dynamic allocation. But we only need to do22; this when FP registers are enabled.23define void @bar(fp128 %f) "target-features"="-fp-armv8" {24; CHECK-LABEL: bar:25; CHECK: // %bb.0:26; CHECK-NEXT: stp x0, x1, [sp, #-16]27; CHECK-NEXT: ret28 %ptr = alloca fp12829 store fp128 %f, ptr %ptr30 ret void31}32