145 lines · plain
1; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s2 3define i8 @test_64bit_add(ptr %a, i64 %b) {4; CHECK-LABEL: test_64bit_add:5; CHECK: ldrh w0, [x0, x1, lsl #1]6; CHECK: ret7 %tmp1 = getelementptr inbounds i16, ptr %a, i64 %b8 %tmp2 = load i16, ptr %tmp19 %tmp3 = trunc i16 %tmp2 to i810 ret i8 %tmp311}12 13; These tests are trying to form SEXT and ZEXT operations that never leave i6414; space, to make sure LLVM can adapt the offset register correctly.15define void @ldst_8bit(ptr %base, i64 %offset) minsize {16; CHECK-LABEL: ldst_8bit:17 18 %off32.sext.tmp = shl i64 %offset, 3219 %off32.sext = ashr i64 %off32.sext.tmp, 3220 %addr8_sxtw = getelementptr i8, ptr %base, i64 %off32.sext21 %val8_sxtw = load volatile i8, ptr %addr8_sxtw22 %val32_signed = sext i8 %val8_sxtw to i3223 store volatile i32 %val32_signed, ptr @var_32bit24; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]25 26 %addrint_uxtw = ptrtoint ptr %base to i6427 %offset_uxtw = and i64 %offset, 429496729528 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw29 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr30 %val8_uxtw = load volatile i8, ptr %addr_uxtw31 %newval8 = add i8 %val8_uxtw, 132 store volatile i8 %newval8, ptr @var_8bit33; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]34 35 ret void36}37 38 39define void @ldst_16bit(ptr %base, i64 %offset) minsize {40; CHECK-LABEL: ldst_16bit:41 42 %addrint_uxtw = ptrtoint ptr %base to i6443 %offset_uxtw = and i64 %offset, 429496729544 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw45 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr46 %val8_uxtw = load volatile i16, ptr %addr_uxtw47 %newval8 = add i16 %val8_uxtw, 148 store volatile i16 %newval8, ptr @var_16bit49; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]50 51 %base_sxtw = ptrtoint ptr %base to i6452 %offset_sxtw.tmp = shl i64 %offset, 3253 %offset_sxtw = ashr i64 %offset_sxtw.tmp, 3254 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw55 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr56 %val16_sxtw = load volatile i16, ptr %addr_sxtw57 %val64_signed = sext i16 %val16_sxtw to i6458 store volatile i64 %val64_signed, ptr @var_64bit59; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]60 61 62 %base_uxtwN = ptrtoint ptr %base to i6463 %offset_uxtwN = and i64 %offset, 429496729564 %offset2_uxtwN = shl i64 %offset_uxtwN, 165 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN66 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr67 %val32 = load volatile i32, ptr @var_32bit68 %val16_trunc32 = trunc i32 %val32 to i1669 store volatile i16 %val16_trunc32, ptr %addr_uxtwN70; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1]71 ret void72}73 74define void @ldst_32bit(ptr %base, i64 %offset) minsize {75; CHECK-LABEL: ldst_32bit:76 77 %addrint_uxtw = ptrtoint ptr %base to i6478 %offset_uxtw = and i64 %offset, 429496729579 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw80 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr81 %val32_uxtw = load volatile i32, ptr %addr_uxtw82 %newval32 = add i32 %val32_uxtw, 183 store volatile i32 %newval32, ptr @var_32bit84; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]85 86 %base_sxtw = ptrtoint ptr %base to i6487 %offset_sxtw.tmp = shl i64 %offset, 3288 %offset_sxtw = ashr i64 %offset_sxtw.tmp, 3289 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw90 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr91 %val32_sxtw = load volatile i32, ptr %addr_sxtw92 %val64_signed = sext i32 %val32_sxtw to i6493 store volatile i64 %val64_signed, ptr @var_64bit94; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]95 96 97 %base_uxtwN = ptrtoint ptr %base to i6498 %offset_uxtwN = and i64 %offset, 429496729599 %offset2_uxtwN = shl i64 %offset_uxtwN, 2100 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN101 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr102 %val32 = load volatile i32, ptr @var_32bit103 store volatile i32 %val32, ptr %addr_uxtwN104; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2]105 ret void106}107 108define void @ldst_64bit(ptr %base, i64 %offset) minsize {109; CHECK-LABEL: ldst_64bit:110 111 %addrint_uxtw = ptrtoint ptr %base to i64112 %offset_uxtw = and i64 %offset, 4294967295113 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw114 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr115 %val64_uxtw = load volatile i64, ptr %addr_uxtw116 %newval8 = add i64 %val64_uxtw, 1117 store volatile i64 %newval8, ptr @var_64bit118; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]119 120 %base_sxtw = ptrtoint ptr %base to i64121 %offset_sxtw.tmp = shl i64 %offset, 32122 %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32123 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw124 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr125 %val64_sxtw = load volatile i64, ptr %addr_sxtw126 store volatile i64 %val64_sxtw, ptr @var_64bit127; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]128 129 130 %base_uxtwN = ptrtoint ptr %base to i64131 %offset_uxtwN = and i64 %offset, 4294967295132 %offset2_uxtwN = shl i64 %offset_uxtwN, 3133 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN134 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr135 %val64 = load volatile i64, ptr @var_64bit136 store volatile i64 %val64, ptr %addr_uxtwN137; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3]138 ret void139}140 141@var_8bit = global i8 0142@var_16bit = global i16 0143@var_32bit = global i32 0144@var_64bit = global i64 0145