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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s3--- |4 define i32 @test01() nounwind {5 entry:6 %0 = select i1 true, i32 1, i32 07 %1 = and i32 %0, 655358 %2 = icmp sgt i32 %1, 09 br i1 %2, label %if.then, label %if.end10 11 if.then: ; preds = %entry12 ret i32 113 14 if.end: ; preds = %entry15 ret i32 016 }17...18---19name: test0120registers:21 - { id: 0, class: gpr32 }22 - { id: 1, class: gpr32common }23body: |24 ; CHECK-LABEL: name: test0125 ; CHECK: bb.0.entry:26 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)27 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 129 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32common = ANDSWri killed [[ANDSWri]], 15, implicit-def $nzcv30 ; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv31 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: bb.1.if.then:33 ; CHECK-NEXT: $w0 = MOVi32imm 134 ; CHECK-NEXT: RET_ReallyLR implicit $w035 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: bb.2.if.end:37 ; CHECK-NEXT: $w0 = MOVi32imm 038 ; CHECK-NEXT: RET_ReallyLR implicit $w039 bb.0.entry:40 successors: %bb.2.if.end, %bb.1.if.then41 42 %0 = MOVi32imm 143 %1 = ANDWri killed %1, 1544 $wzr = SUBSWri killed %1, 0, 0, implicit-def $nzcv45 Bcc 12, %bb.2.if.end, implicit $nzcv46 47 bb.1.if.then:48 $w0 = MOVi32imm 149 RET_ReallyLR implicit $w050 51 bb.2.if.end:52 $w0 = MOVi32imm 053 RET_ReallyLR implicit $w054 55...56