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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone | FileCheck --check-prefixes=CHECK,CHECK-CYC %s3; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck --check-prefixes=CHECK,CHECK-A57 %s4 5define float @t1(ptr nocapture %src) nounwind ssp {6; CHECK-LABEL: t1:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: ldr s0, [x0]9; CHECK-NEXT: scvtf s0, s010; CHECK-NEXT: ret11entry:12 %tmp1 = load i32, ptr %src, align 413 %tmp2 = sitofp i32 %tmp1 to float14 ret float %tmp215}16 17define float @t2(ptr nocapture %src) nounwind ssp {18; CHECK-LABEL: t2:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: ldr s0, [x0]21; CHECK-NEXT: ucvtf s0, s022; CHECK-NEXT: ret23entry:24 %tmp1 = load i32, ptr %src, align 425 %tmp2 = uitofp i32 %tmp1 to float26 ret float %tmp227}28 29define double @t3(ptr nocapture %src) nounwind ssp {30; CHECK-LABEL: t3:31; CHECK: // %bb.0: // %entry32; CHECK-NEXT: ldr d0, [x0]33; CHECK-NEXT: scvtf d0, d034; CHECK-NEXT: ret35entry:36 %tmp1 = load i64, ptr %src, align 437 %tmp2 = sitofp i64 %tmp1 to double38 ret double %tmp239}40 41define double @t4(ptr nocapture %src) nounwind ssp {42; CHECK-LABEL: t4:43; CHECK: // %bb.0: // %entry44; CHECK-NEXT: ldr d0, [x0]45; CHECK-NEXT: ucvtf d0, d046; CHECK-NEXT: ret47entry:48 %tmp1 = load i64, ptr %src, align 449 %tmp2 = uitofp i64 %tmp1 to double50 ret double %tmp251}52 53; rdar://1313645654define double @t5(ptr nocapture %src) nounwind ssp optsize {55; CHECK-LABEL: t5:56; CHECK: // %bb.0: // %entry57; CHECK-NEXT: ldr w8, [x0]58; CHECK-NEXT: scvtf d0, w859; CHECK-NEXT: ret60entry:61 %tmp1 = load i32, ptr %src, align 462 %tmp2 = sitofp i32 %tmp1 to double63 ret double %tmp264}65 66; Check that we load in FP register when we want to convert into67; floating point value.68; This is much faster than loading on GPR and making the conversion69; GPR -> FPR.70; <rdar://problem/14599607>71;72; Check the flollowing patterns for signed/unsigned:73; 1. load with scaled imm to float.74; 2. load with scaled register to float.75; 3. load with scaled imm to double.76; 4. load with scaled register to double.77; 5. load with unscaled imm to float.78; 6. load with unscaled imm to double.79; With loading size: 8, 16, 32, and 64-bits.80 81; ********* 1. load with scaled imm to float. *********82define float @fct1(ptr nocapture %sp0) {83; CHECK-LABEL: fct1:84; CHECK: // %bb.0: // %entry85; CHECK-NEXT: ldr b0, [x0, #1]86; CHECK-NEXT: ucvtf s0, s087; CHECK-NEXT: fmul s0, s0, s088; CHECK-NEXT: ret89entry:90 %addr = getelementptr i8, ptr %sp0, i64 191 %pix_sp0.0.copyload = load i8, ptr %addr, align 192 %val = uitofp i8 %pix_sp0.0.copyload to float93 %vmull.i = fmul float %val, %val94 ret float %vmull.i95}96 97define float @fct2(ptr nocapture %sp0) {98; CHECK-LABEL: fct2:99; CHECK: // %bb.0: // %entry100; CHECK-NEXT: ldr h0, [x0, #2]101; CHECK-NEXT: ucvtf s0, s0102; CHECK-NEXT: fmul s0, s0, s0103; CHECK-NEXT: ret104entry:105 %addr = getelementptr i16, ptr %sp0, i64 1106 %pix_sp0.0.copyload = load i16, ptr %addr, align 1107 %val = uitofp i16 %pix_sp0.0.copyload to float108 %vmull.i = fmul float %val, %val109 ret float %vmull.i110}111 112define float @fct3(ptr nocapture %sp0) {113; CHECK-LABEL: fct3:114; CHECK: // %bb.0: // %entry115; CHECK-NEXT: ldr s0, [x0, #4]116; CHECK-NEXT: ucvtf s0, s0117; CHECK-NEXT: fmul s0, s0, s0118; CHECK-NEXT: ret119entry:120 %addr = getelementptr i32, ptr %sp0, i64 1121 %pix_sp0.0.copyload = load i32, ptr %addr, align 1122 %val = uitofp i32 %pix_sp0.0.copyload to float123 %vmull.i = fmul float %val, %val124 ret float %vmull.i125}126 127; i64 -> f32 is not supported on floating point unit.128define float @fct4(ptr nocapture %sp0) {129; CHECK-LABEL: fct4:130; CHECK: // %bb.0: // %entry131; CHECK-NEXT: ldr x8, [x0, #8]132; CHECK-NEXT: ucvtf s0, x8133; CHECK-NEXT: fmul s0, s0, s0134; CHECK-NEXT: ret135entry:136 %addr = getelementptr i64, ptr %sp0, i64 1137 %pix_sp0.0.copyload = load i64, ptr %addr, align 1138 %val = uitofp i64 %pix_sp0.0.copyload to float139 %vmull.i = fmul float %val, %val140 ret float %vmull.i141}142 143; ********* 2. load with scaled register to float. *********144define float @fct5(ptr nocapture %sp0, i64 %offset) {145; CHECK-LABEL: fct5:146; CHECK: // %bb.0: // %entry147; CHECK-NEXT: ldr b0, [x0, x1]148; CHECK-NEXT: ucvtf s0, s0149; CHECK-NEXT: fmul s0, s0, s0150; CHECK-NEXT: ret151entry:152 %addr = getelementptr i8, ptr %sp0, i64 %offset153 %pix_sp0.0.copyload = load i8, ptr %addr, align 1154 %val = uitofp i8 %pix_sp0.0.copyload to float155 %vmull.i = fmul float %val, %val156 ret float %vmull.i157}158 159define float @fct6(ptr nocapture %sp0, i64 %offset) {160; CHECK-LABEL: fct6:161; CHECK: // %bb.0: // %entry162; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]163; CHECK-NEXT: ucvtf s0, s0164; CHECK-NEXT: fmul s0, s0, s0165; CHECK-NEXT: ret166entry:167 %addr = getelementptr i16, ptr %sp0, i64 %offset168 %pix_sp0.0.copyload = load i16, ptr %addr, align 1169 %val = uitofp i16 %pix_sp0.0.copyload to float170 %vmull.i = fmul float %val, %val171 ret float %vmull.i172}173 174define float @fct7(ptr nocapture %sp0, i64 %offset) {175; CHECK-LABEL: fct7:176; CHECK: // %bb.0: // %entry177; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]178; CHECK-NEXT: ucvtf s0, s0179; CHECK-NEXT: fmul s0, s0, s0180; CHECK-NEXT: ret181entry:182 %addr = getelementptr i32, ptr %sp0, i64 %offset183 %pix_sp0.0.copyload = load i32, ptr %addr, align 1184 %val = uitofp i32 %pix_sp0.0.copyload to float185 %vmull.i = fmul float %val, %val186 ret float %vmull.i187}188 189; i64 -> f32 is not supported on floating point unit.190define float @fct8(ptr nocapture %sp0, i64 %offset) {191; CHECK-LABEL: fct8:192; CHECK: // %bb.0: // %entry193; CHECK-NEXT: ldr x8, [x0, x1, lsl #3]194; CHECK-NEXT: ucvtf s0, x8195; CHECK-NEXT: fmul s0, s0, s0196; CHECK-NEXT: ret197entry:198 %addr = getelementptr i64, ptr %sp0, i64 %offset199 %pix_sp0.0.copyload = load i64, ptr %addr, align 1200 %val = uitofp i64 %pix_sp0.0.copyload to float201 %vmull.i = fmul float %val, %val202 ret float %vmull.i203}204 205 206; ********* 3. load with scaled imm to double. *********207define double @fct9(ptr nocapture %sp0) {208; CHECK-LABEL: fct9:209; CHECK: // %bb.0: // %entry210; CHECK-NEXT: ldr b0, [x0, #1]211; CHECK-NEXT: ucvtf d0, d0212; CHECK-NEXT: fmul d0, d0, d0213; CHECK-NEXT: ret214entry:215 %addr = getelementptr i8, ptr %sp0, i64 1216 %pix_sp0.0.copyload = load i8, ptr %addr, align 1217 %val = uitofp i8 %pix_sp0.0.copyload to double218 %vmull.i = fmul double %val, %val219 ret double %vmull.i220}221 222define double @fct10(ptr nocapture %sp0) {223; CHECK-LABEL: fct10:224; CHECK: // %bb.0: // %entry225; CHECK-NEXT: ldr h0, [x0, #2]226; CHECK-NEXT: ucvtf d0, d0227; CHECK-NEXT: fmul d0, d0, d0228; CHECK-NEXT: ret229entry:230 %addr = getelementptr i16, ptr %sp0, i64 1231 %pix_sp0.0.copyload = load i16, ptr %addr, align 1232 %val = uitofp i16 %pix_sp0.0.copyload to double233 %vmull.i = fmul double %val, %val234 ret double %vmull.i235}236 237define double @fct11(ptr nocapture %sp0) {238; CHECK-LABEL: fct11:239; CHECK: // %bb.0: // %entry240; CHECK-NEXT: ldr s0, [x0, #4]241; CHECK-NEXT: ucvtf d0, d0242; CHECK-NEXT: fmul d0, d0, d0243; CHECK-NEXT: ret244entry:245 %addr = getelementptr i32, ptr %sp0, i64 1246 %pix_sp0.0.copyload = load i32, ptr %addr, align 1247 %val = uitofp i32 %pix_sp0.0.copyload to double248 %vmull.i = fmul double %val, %val249 ret double %vmull.i250}251 252define double @fct12(ptr nocapture %sp0) {253; CHECK-LABEL: fct12:254; CHECK: // %bb.0: // %entry255; CHECK-NEXT: ldr d0, [x0, #8]256; CHECK-NEXT: ucvtf d0, d0257; CHECK-NEXT: fmul d0, d0, d0258; CHECK-NEXT: ret259entry:260 %addr = getelementptr i64, ptr %sp0, i64 1261 %pix_sp0.0.copyload = load i64, ptr %addr, align 1262 %val = uitofp i64 %pix_sp0.0.copyload to double263 %vmull.i = fmul double %val, %val264 ret double %vmull.i265}266 267; ********* 4. load with scaled register to double. *********268define double @fct13(ptr nocapture %sp0, i64 %offset) {269; CHECK-LABEL: fct13:270; CHECK: // %bb.0: // %entry271; CHECK-NEXT: ldr b0, [x0, x1]272; CHECK-NEXT: ucvtf d0, d0273; CHECK-NEXT: fmul d0, d0, d0274; CHECK-NEXT: ret275entry:276 %addr = getelementptr i8, ptr %sp0, i64 %offset277 %pix_sp0.0.copyload = load i8, ptr %addr, align 1278 %val = uitofp i8 %pix_sp0.0.copyload to double279 %vmull.i = fmul double %val, %val280 ret double %vmull.i281}282 283define double @fct14(ptr nocapture %sp0, i64 %offset) {284; CHECK-LABEL: fct14:285; CHECK: // %bb.0: // %entry286; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]287; CHECK-NEXT: ucvtf d0, d0288; CHECK-NEXT: fmul d0, d0, d0289; CHECK-NEXT: ret290entry:291 %addr = getelementptr i16, ptr %sp0, i64 %offset292 %pix_sp0.0.copyload = load i16, ptr %addr, align 1293 %val = uitofp i16 %pix_sp0.0.copyload to double294 %vmull.i = fmul double %val, %val295 ret double %vmull.i296}297 298define double @fct15(ptr nocapture %sp0, i64 %offset) {299; CHECK-LABEL: fct15:300; CHECK: // %bb.0: // %entry301; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]302; CHECK-NEXT: ucvtf d0, d0303; CHECK-NEXT: fmul d0, d0, d0304; CHECK-NEXT: ret305entry:306 %addr = getelementptr i32, ptr %sp0, i64 %offset307 %pix_sp0.0.copyload = load i32, ptr %addr, align 1308 %val = uitofp i32 %pix_sp0.0.copyload to double309 %vmull.i = fmul double %val, %val310 ret double %vmull.i311}312 313define double @fct16(ptr nocapture %sp0, i64 %offset) {314; CHECK-LABEL: fct16:315; CHECK: // %bb.0: // %entry316; CHECK-NEXT: ldr d0, [x0, x1, lsl #3]317; CHECK-NEXT: ucvtf d0, d0318; CHECK-NEXT: fmul d0, d0, d0319; CHECK-NEXT: ret320entry:321 %addr = getelementptr i64, ptr %sp0, i64 %offset322 %pix_sp0.0.copyload = load i64, ptr %addr, align 1323 %val = uitofp i64 %pix_sp0.0.copyload to double324 %vmull.i = fmul double %val, %val325 ret double %vmull.i326}327 328; ********* 5. load with unscaled imm to float. *********329define float @fct17(ptr nocapture %sp0) {330; CHECK-LABEL: fct17:331; CHECK: // %bb.0: // %entry332; CHECK-NEXT: ldur b0, [x0, #-1]333; CHECK-NEXT: ucvtf s0, s0334; CHECK-NEXT: fmul s0, s0, s0335; CHECK-NEXT: ret336entry:337 %bitcast = ptrtoint ptr %sp0 to i64338 %add = add i64 %bitcast, -1339 %addr = inttoptr i64 %add to ptr340 %pix_sp0.0.copyload = load i8, ptr %addr, align 1341 %val = uitofp i8 %pix_sp0.0.copyload to float342 %vmull.i = fmul float %val, %val343 ret float %vmull.i344}345 346define float @fct18(ptr nocapture %sp0) {347; CHECK-LABEL: fct18:348; CHECK: // %bb.0:349; CHECK-NEXT: ldur h0, [x0, #1]350; CHECK-NEXT: ucvtf s0, s0351; CHECK-NEXT: fmul s0, s0, s0352; CHECK-NEXT: ret353 %bitcast = ptrtoint ptr %sp0 to i64354 %add = add i64 %bitcast, 1355 %addr = inttoptr i64 %add to ptr356 %pix_sp0.0.copyload = load i16, ptr %addr, align 1357 %val = uitofp i16 %pix_sp0.0.copyload to float358 %vmull.i = fmul float %val, %val359 ret float %vmull.i360}361 362define float @fct19(ptr nocapture %sp0) {363; CHECK-LABEL: fct19:364; CHECK: // %bb.0:365; CHECK-NEXT: ldur s0, [x0, #1]366; CHECK-NEXT: ucvtf s0, s0367; CHECK-NEXT: fmul s0, s0, s0368; CHECK-NEXT: ret369 %bitcast = ptrtoint ptr %sp0 to i64370 %add = add i64 %bitcast, 1371 %addr = inttoptr i64 %add to ptr372 %pix_sp0.0.copyload = load i32, ptr %addr, align 1373 %val = uitofp i32 %pix_sp0.0.copyload to float374 %vmull.i = fmul float %val, %val375 ret float %vmull.i376}377 378; i64 -> f32 is not supported on floating point unit.379define float @fct20(ptr nocapture %sp0) {380; CHECK-LABEL: fct20:381; CHECK: // %bb.0:382; CHECK-NEXT: ldur x8, [x0, #1]383; CHECK-NEXT: ucvtf s0, x8384; CHECK-NEXT: fmul s0, s0, s0385; CHECK-NEXT: ret386 %bitcast = ptrtoint ptr %sp0 to i64387 %add = add i64 %bitcast, 1388 %addr = inttoptr i64 %add to ptr389 %pix_sp0.0.copyload = load i64, ptr %addr, align 1390 %val = uitofp i64 %pix_sp0.0.copyload to float391 %vmull.i = fmul float %val, %val392 ret float %vmull.i393 394}395 396; ********* 6. load with unscaled imm to double. *********397define double @fct21(ptr nocapture %sp0) {398; CHECK-LABEL: fct21:399; CHECK: // %bb.0: // %entry400; CHECK-NEXT: ldur b0, [x0, #-1]401; CHECK-NEXT: ucvtf d0, d0402; CHECK-NEXT: fmul d0, d0, d0403; CHECK-NEXT: ret404entry:405 %bitcast = ptrtoint ptr %sp0 to i64406 %add = add i64 %bitcast, -1407 %addr = inttoptr i64 %add to ptr408 %pix_sp0.0.copyload = load i8, ptr %addr, align 1409 %val = uitofp i8 %pix_sp0.0.copyload to double410 %vmull.i = fmul double %val, %val411 ret double %vmull.i412}413 414define double @fct22(ptr nocapture %sp0) {415; CHECK-LABEL: fct22:416; CHECK: // %bb.0:417; CHECK-NEXT: ldur h0, [x0, #1]418; CHECK-NEXT: ucvtf d0, d0419; CHECK-NEXT: fmul d0, d0, d0420; CHECK-NEXT: ret421 %bitcast = ptrtoint ptr %sp0 to i64422 %add = add i64 %bitcast, 1423 %addr = inttoptr i64 %add to ptr424 %pix_sp0.0.copyload = load i16, ptr %addr, align 1425 %val = uitofp i16 %pix_sp0.0.copyload to double426 %vmull.i = fmul double %val, %val427 ret double %vmull.i428}429 430define double @fct23(ptr nocapture %sp0) {431; CHECK-LABEL: fct23:432; CHECK: // %bb.0:433; CHECK-NEXT: ldur s0, [x0, #1]434; CHECK-NEXT: ucvtf d0, d0435; CHECK-NEXT: fmul d0, d0, d0436; CHECK-NEXT: ret437 %bitcast = ptrtoint ptr %sp0 to i64438 %add = add i64 %bitcast, 1439 %addr = inttoptr i64 %add to ptr440 %pix_sp0.0.copyload = load i32, ptr %addr, align 1441 %val = uitofp i32 %pix_sp0.0.copyload to double442 %vmull.i = fmul double %val, %val443 ret double %vmull.i444}445 446define double @fct24(ptr nocapture %sp0) {447; CHECK-LABEL: fct24:448; CHECK: // %bb.0:449; CHECK-NEXT: ldur d0, [x0, #1]450; CHECK-NEXT: ucvtf d0, d0451; CHECK-NEXT: fmul d0, d0, d0452; CHECK-NEXT: ret453 %bitcast = ptrtoint ptr %sp0 to i64454 %add = add i64 %bitcast, 1455 %addr = inttoptr i64 %add to ptr456 %pix_sp0.0.copyload = load i64, ptr %addr, align 1457 %val = uitofp i64 %pix_sp0.0.copyload to double458 %vmull.i = fmul double %val, %val459 ret double %vmull.i460 461}462 463; ********* 1s. load with scaled imm to float. *********464define float @sfct1(ptr nocapture %sp0) {465; CHECK-CYC-LABEL: sfct1:466; CHECK-CYC: // %bb.0: // %entry467; CHECK-CYC-NEXT: ldr b0, [x0, #1]468; CHECK-CYC-NEXT: sshll v0.8h, v0.8b, #0469; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0470; CHECK-CYC-NEXT: scvtf s0, s0471; CHECK-CYC-NEXT: fmul s0, s0, s0472; CHECK-CYC-NEXT: ret473;474; CHECK-A57-LABEL: sfct1:475; CHECK-A57: // %bb.0: // %entry476; CHECK-A57-NEXT: ldrsb w8, [x0, #1]477; CHECK-A57-NEXT: scvtf s0, w8478; CHECK-A57-NEXT: fmul s0, s0, s0479; CHECK-A57-NEXT: ret480entry:481 %addr = getelementptr i8, ptr %sp0, i64 1482 %pix_sp0.0.copyload = load i8, ptr %addr, align 1483 %val = sitofp i8 %pix_sp0.0.copyload to float484 %vmull.i = fmul float %val, %val485 ret float %vmull.i486}487 488define float @sfct2(ptr nocapture %sp0) {489; CHECK-CYC-LABEL: sfct2:490; CHECK-CYC: // %bb.0: // %entry491; CHECK-CYC-NEXT: ldr h0, [x0, #2]492; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0493; CHECK-CYC-NEXT: scvtf s0, s0494; CHECK-CYC-NEXT: fmul s0, s0, s0495; CHECK-CYC-NEXT: ret496;497; CHECK-A57-LABEL: sfct2:498; CHECK-A57: // %bb.0: // %entry499; CHECK-A57-NEXT: ldrsh w8, [x0, #2]500; CHECK-A57-NEXT: scvtf s0, w8501; CHECK-A57-NEXT: fmul s0, s0, s0502; CHECK-A57-NEXT: ret503entry:504 %addr = getelementptr i16, ptr %sp0, i64 1505 %pix_sp0.0.copyload = load i16, ptr %addr, align 1506 %val = sitofp i16 %pix_sp0.0.copyload to float507 %vmull.i = fmul float %val, %val508 ret float %vmull.i509}510 511define float @sfct3(ptr nocapture %sp0) {512; CHECK-LABEL: sfct3:513; CHECK: // %bb.0: // %entry514; CHECK-NEXT: ldr s0, [x0, #4]515; CHECK-NEXT: scvtf s0, s0516; CHECK-NEXT: fmul s0, s0, s0517; CHECK-NEXT: ret518entry:519 %addr = getelementptr i32, ptr %sp0, i64 1520 %pix_sp0.0.copyload = load i32, ptr %addr, align 1521 %val = sitofp i32 %pix_sp0.0.copyload to float522 %vmull.i = fmul float %val, %val523 ret float %vmull.i524}525 526; i64 -> f32 is not supported on floating point unit.527define float @sfct4(ptr nocapture %sp0) {528; CHECK-LABEL: sfct4:529; CHECK: // %bb.0: // %entry530; CHECK-NEXT: ldr x8, [x0, #8]531; CHECK-NEXT: scvtf s0, x8532; CHECK-NEXT: fmul s0, s0, s0533; CHECK-NEXT: ret534entry:535 %addr = getelementptr i64, ptr %sp0, i64 1536 %pix_sp0.0.copyload = load i64, ptr %addr, align 1537 %val = sitofp i64 %pix_sp0.0.copyload to float538 %vmull.i = fmul float %val, %val539 ret float %vmull.i540}541 542; ********* 2s. load with scaled register to float. *********543define float @sfct5(ptr nocapture %sp0, i64 %offset) {544; CHECK-CYC-LABEL: sfct5:545; CHECK-CYC: // %bb.0: // %entry546; CHECK-CYC-NEXT: ldr b0, [x0, x1]547; CHECK-CYC-NEXT: sshll v0.8h, v0.8b, #0548; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0549; CHECK-CYC-NEXT: scvtf s0, s0550; CHECK-CYC-NEXT: fmul s0, s0, s0551; CHECK-CYC-NEXT: ret552;553; CHECK-A57-LABEL: sfct5:554; CHECK-A57: // %bb.0: // %entry555; CHECK-A57-NEXT: ldrsb w8, [x0, x1]556; CHECK-A57-NEXT: scvtf s0, w8557; CHECK-A57-NEXT: fmul s0, s0, s0558; CHECK-A57-NEXT: ret559entry:560 %addr = getelementptr i8, ptr %sp0, i64 %offset561 %pix_sp0.0.copyload = load i8, ptr %addr, align 1562 %val = sitofp i8 %pix_sp0.0.copyload to float563 %vmull.i = fmul float %val, %val564 ret float %vmull.i565}566 567define float @sfct6(ptr nocapture %sp0, i64 %offset) {568; CHECK-CYC-LABEL: sfct6:569; CHECK-CYC: // %bb.0: // %entry570; CHECK-CYC-NEXT: ldr h0, [x0, x1, lsl #1]571; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0572; CHECK-CYC-NEXT: scvtf s0, s0573; CHECK-CYC-NEXT: fmul s0, s0, s0574; CHECK-CYC-NEXT: ret575;576; CHECK-A57-LABEL: sfct6:577; CHECK-A57: // %bb.0: // %entry578; CHECK-A57-NEXT: ldrsh w8, [x0, x1, lsl #1]579; CHECK-A57-NEXT: scvtf s0, w8580; CHECK-A57-NEXT: fmul s0, s0, s0581; CHECK-A57-NEXT: ret582entry:583 %addr = getelementptr i16, ptr %sp0, i64 %offset584 %pix_sp0.0.copyload = load i16, ptr %addr, align 1585 %val = sitofp i16 %pix_sp0.0.copyload to float586 %vmull.i = fmul float %val, %val587 ret float %vmull.i588}589 590define float @sfct7(ptr nocapture %sp0, i64 %offset) {591; CHECK-LABEL: sfct7:592; CHECK: // %bb.0: // %entry593; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]594; CHECK-NEXT: scvtf s0, s0595; CHECK-NEXT: fmul s0, s0, s0596; CHECK-NEXT: ret597entry:598 %addr = getelementptr i32, ptr %sp0, i64 %offset599 %pix_sp0.0.copyload = load i32, ptr %addr, align 1600 %val = sitofp i32 %pix_sp0.0.copyload to float601 %vmull.i = fmul float %val, %val602 ret float %vmull.i603}604 605; i64 -> f32 is not supported on floating point unit.606define float @sfct8(ptr nocapture %sp0, i64 %offset) {607; CHECK-LABEL: sfct8:608; CHECK: // %bb.0: // %entry609; CHECK-NEXT: ldr x8, [x0, x1, lsl #3]610; CHECK-NEXT: scvtf s0, x8611; CHECK-NEXT: fmul s0, s0, s0612; CHECK-NEXT: ret613entry:614 %addr = getelementptr i64, ptr %sp0, i64 %offset615 %pix_sp0.0.copyload = load i64, ptr %addr, align 1616 %val = sitofp i64 %pix_sp0.0.copyload to float617 %vmull.i = fmul float %val, %val618 ret float %vmull.i619}620 621; ********* 3s. load with scaled imm to double. *********622define double @sfct9(ptr nocapture %sp0) {623; CHECK-LABEL: sfct9:624; CHECK: // %bb.0: // %entry625; CHECK-NEXT: ldrsb w8, [x0, #1]626; CHECK-NEXT: scvtf d0, w8627; CHECK-NEXT: fmul d0, d0, d0628; CHECK-NEXT: ret629entry:630 %addr = getelementptr i8, ptr %sp0, i64 1631 %pix_sp0.0.copyload = load i8, ptr %addr, align 1632 %val = sitofp i8 %pix_sp0.0.copyload to double633 %vmull.i = fmul double %val, %val634 ret double %vmull.i635}636 637define double @sfct10(ptr nocapture %sp0) {638; CHECK-CYC-LABEL: sfct10:639; CHECK-CYC: // %bb.0: // %entry640; CHECK-CYC-NEXT: ldr h0, [x0, #2]641; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0642; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0643; CHECK-CYC-NEXT: scvtf d0, d0644; CHECK-CYC-NEXT: fmul d0, d0, d0645; CHECK-CYC-NEXT: ret646;647; CHECK-A57-LABEL: sfct10:648; CHECK-A57: // %bb.0: // %entry649; CHECK-A57-NEXT: ldrsh w8, [x0, #2]650; CHECK-A57-NEXT: scvtf d0, w8651; CHECK-A57-NEXT: fmul d0, d0, d0652; CHECK-A57-NEXT: ret653entry:654 %addr = getelementptr i16, ptr %sp0, i64 1655 %pix_sp0.0.copyload = load i16, ptr %addr, align 1656 %val = sitofp i16 %pix_sp0.0.copyload to double657 %vmull.i = fmul double %val, %val658 ret double %vmull.i659}660 661define double @sfct11(ptr nocapture %sp0) {662; CHECK-CYC-LABEL: sfct11:663; CHECK-CYC: // %bb.0: // %entry664; CHECK-CYC-NEXT: ldr s0, [x0, #4]665; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0666; CHECK-CYC-NEXT: scvtf d0, d0667; CHECK-CYC-NEXT: fmul d0, d0, d0668; CHECK-CYC-NEXT: ret669;670; CHECK-A57-LABEL: sfct11:671; CHECK-A57: // %bb.0: // %entry672; CHECK-A57-NEXT: ldr w8, [x0, #4]673; CHECK-A57-NEXT: scvtf d0, w8674; CHECK-A57-NEXT: fmul d0, d0, d0675; CHECK-A57-NEXT: ret676entry:677 %addr = getelementptr i32, ptr %sp0, i64 1678 %pix_sp0.0.copyload = load i32, ptr %addr, align 1679 %val = sitofp i32 %pix_sp0.0.copyload to double680 %vmull.i = fmul double %val, %val681 ret double %vmull.i682}683 684define double @sfct12(ptr nocapture %sp0) {685; CHECK-LABEL: sfct12:686; CHECK: // %bb.0: // %entry687; CHECK-NEXT: ldr d0, [x0, #8]688; CHECK-NEXT: scvtf d0, d0689; CHECK-NEXT: fmul d0, d0, d0690; CHECK-NEXT: ret691entry:692 %addr = getelementptr i64, ptr %sp0, i64 1693 %pix_sp0.0.copyload = load i64, ptr %addr, align 1694 %val = sitofp i64 %pix_sp0.0.copyload to double695 %vmull.i = fmul double %val, %val696 ret double %vmull.i697}698 699; ********* 4s. load with scaled register to double. *********700define double @sfct13(ptr nocapture %sp0, i64 %offset) {701; CHECK-LABEL: sfct13:702; CHECK: // %bb.0: // %entry703; CHECK-NEXT: ldrsb w8, [x0, x1]704; CHECK-NEXT: scvtf d0, w8705; CHECK-NEXT: fmul d0, d0, d0706; CHECK-NEXT: ret707entry:708 %addr = getelementptr i8, ptr %sp0, i64 %offset709 %pix_sp0.0.copyload = load i8, ptr %addr, align 1710 %val = sitofp i8 %pix_sp0.0.copyload to double711 %vmull.i = fmul double %val, %val712 ret double %vmull.i713}714 715define double @sfct14(ptr nocapture %sp0, i64 %offset) {716; CHECK-CYC-LABEL: sfct14:717; CHECK-CYC: // %bb.0: // %entry718; CHECK-CYC-NEXT: ldr h0, [x0, x1, lsl #1]719; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0720; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0721; CHECK-CYC-NEXT: scvtf d0, d0722; CHECK-CYC-NEXT: fmul d0, d0, d0723; CHECK-CYC-NEXT: ret724;725; CHECK-A57-LABEL: sfct14:726; CHECK-A57: // %bb.0: // %entry727; CHECK-A57-NEXT: ldrsh w8, [x0, x1, lsl #1]728; CHECK-A57-NEXT: scvtf d0, w8729; CHECK-A57-NEXT: fmul d0, d0, d0730; CHECK-A57-NEXT: ret731entry:732 %addr = getelementptr i16, ptr %sp0, i64 %offset733 %pix_sp0.0.copyload = load i16, ptr %addr, align 1734 %val = sitofp i16 %pix_sp0.0.copyload to double735 %vmull.i = fmul double %val, %val736 ret double %vmull.i737}738 739define double @sfct15(ptr nocapture %sp0, i64 %offset) {740; CHECK-CYC-LABEL: sfct15:741; CHECK-CYC: // %bb.0: // %entry742; CHECK-CYC-NEXT: ldr s0, [x0, x1, lsl #2]743; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0744; CHECK-CYC-NEXT: scvtf d0, d0745; CHECK-CYC-NEXT: fmul d0, d0, d0746; CHECK-CYC-NEXT: ret747;748; CHECK-A57-LABEL: sfct15:749; CHECK-A57: // %bb.0: // %entry750; CHECK-A57-NEXT: ldr w8, [x0, x1, lsl #2]751; CHECK-A57-NEXT: scvtf d0, w8752; CHECK-A57-NEXT: fmul d0, d0, d0753; CHECK-A57-NEXT: ret754entry:755 %addr = getelementptr i32, ptr %sp0, i64 %offset756 %pix_sp0.0.copyload = load i32, ptr %addr, align 1757 %val = sitofp i32 %pix_sp0.0.copyload to double758 %vmull.i = fmul double %val, %val759 ret double %vmull.i760}761 762define double @sfct16(ptr nocapture %sp0, i64 %offset) {763; CHECK-LABEL: sfct16:764; CHECK: // %bb.0: // %entry765; CHECK-NEXT: ldr d0, [x0, x1, lsl #3]766; CHECK-NEXT: scvtf d0, d0767; CHECK-NEXT: fmul d0, d0, d0768; CHECK-NEXT: ret769entry:770 %addr = getelementptr i64, ptr %sp0, i64 %offset771 %pix_sp0.0.copyload = load i64, ptr %addr, align 1772 %val = sitofp i64 %pix_sp0.0.copyload to double773 %vmull.i = fmul double %val, %val774 ret double %vmull.i775}776 777; ********* 5s. load with unscaled imm to float. *********778define float @sfct17(ptr nocapture %sp0) {779; CHECK-CYC-LABEL: sfct17:780; CHECK-CYC: // %bb.0: // %entry781; CHECK-CYC-NEXT: ldur b0, [x0, #-1]782; CHECK-CYC-NEXT: sshll v0.8h, v0.8b, #0783; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0784; CHECK-CYC-NEXT: scvtf s0, s0785; CHECK-CYC-NEXT: fmul s0, s0, s0786; CHECK-CYC-NEXT: ret787;788; CHECK-A57-LABEL: sfct17:789; CHECK-A57: // %bb.0: // %entry790; CHECK-A57-NEXT: ldursb w8, [x0, #-1]791; CHECK-A57-NEXT: scvtf s0, w8792; CHECK-A57-NEXT: fmul s0, s0, s0793; CHECK-A57-NEXT: ret794entry:795 %bitcast = ptrtoint ptr %sp0 to i64796 %add = add i64 %bitcast, -1797 %addr = inttoptr i64 %add to ptr798 %pix_sp0.0.copyload = load i8, ptr %addr, align 1799 %val = sitofp i8 %pix_sp0.0.copyload to float800 %vmull.i = fmul float %val, %val801 ret float %vmull.i802}803 804define float @sfct18(ptr nocapture %sp0) {805; CHECK-CYC-LABEL: sfct18:806; CHECK-CYC: // %bb.0:807; CHECK-CYC-NEXT: ldur h0, [x0, #1]808; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0809; CHECK-CYC-NEXT: scvtf s0, s0810; CHECK-CYC-NEXT: fmul s0, s0, s0811; CHECK-CYC-NEXT: ret812;813; CHECK-A57-LABEL: sfct18:814; CHECK-A57: // %bb.0:815; CHECK-A57-NEXT: ldursh w8, [x0, #1]816; CHECK-A57-NEXT: scvtf s0, w8817; CHECK-A57-NEXT: fmul s0, s0, s0818; CHECK-A57-NEXT: ret819 %bitcast = ptrtoint ptr %sp0 to i64820 %add = add i64 %bitcast, 1821 %addr = inttoptr i64 %add to ptr822 %pix_sp0.0.copyload = load i16, ptr %addr, align 1823 %val = sitofp i16 %pix_sp0.0.copyload to float824 %vmull.i = fmul float %val, %val825 ret float %vmull.i826}827 828define float @sfct19(ptr nocapture %sp0) {829; CHECK-LABEL: sfct19:830; CHECK: // %bb.0:831; CHECK-NEXT: ldur s0, [x0, #1]832; CHECK-NEXT: scvtf s0, s0833; CHECK-NEXT: fmul s0, s0, s0834; CHECK-NEXT: ret835 %bitcast = ptrtoint ptr %sp0 to i64836 %add = add i64 %bitcast, 1837 %addr = inttoptr i64 %add to ptr838 %pix_sp0.0.copyload = load i32, ptr %addr, align 1839 %val = sitofp i32 %pix_sp0.0.copyload to float840 %vmull.i = fmul float %val, %val841 ret float %vmull.i842}843 844; i64 -> f32 is not supported on floating point unit.845define float @sfct20(ptr nocapture %sp0) {846; CHECK-LABEL: sfct20:847; CHECK: // %bb.0:848; CHECK-NEXT: ldur x8, [x0, #1]849; CHECK-NEXT: scvtf s0, x8850; CHECK-NEXT: fmul s0, s0, s0851; CHECK-NEXT: ret852 %bitcast = ptrtoint ptr %sp0 to i64853 %add = add i64 %bitcast, 1854 %addr = inttoptr i64 %add to ptr855 %pix_sp0.0.copyload = load i64, ptr %addr, align 1856 %val = sitofp i64 %pix_sp0.0.copyload to float857 %vmull.i = fmul float %val, %val858 ret float %vmull.i859 860}861 862; ********* 6s. load with unscaled imm to double. *********863define double @sfct21(ptr nocapture %sp0) {864; CHECK-LABEL: sfct21:865; CHECK: // %bb.0: // %entry866; CHECK-NEXT: ldursb w8, [x0, #-1]867; CHECK-NEXT: scvtf d0, w8868; CHECK-NEXT: fmul d0, d0, d0869; CHECK-NEXT: ret870entry:871 %bitcast = ptrtoint ptr %sp0 to i64872 %add = add i64 %bitcast, -1873 %addr = inttoptr i64 %add to ptr874 %pix_sp0.0.copyload = load i8, ptr %addr, align 1875 %val = sitofp i8 %pix_sp0.0.copyload to double876 %vmull.i = fmul double %val, %val877 ret double %vmull.i878}879 880define double @sfct22(ptr nocapture %sp0) {881; CHECK-CYC-LABEL: sfct22:882; CHECK-CYC: // %bb.0:883; CHECK-CYC-NEXT: ldur h0, [x0, #1]884; CHECK-CYC-NEXT: sshll v0.4s, v0.4h, #0885; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0886; CHECK-CYC-NEXT: scvtf d0, d0887; CHECK-CYC-NEXT: fmul d0, d0, d0888; CHECK-CYC-NEXT: ret889;890; CHECK-A57-LABEL: sfct22:891; CHECK-A57: // %bb.0:892; CHECK-A57-NEXT: ldursh w8, [x0, #1]893; CHECK-A57-NEXT: scvtf d0, w8894; CHECK-A57-NEXT: fmul d0, d0, d0895; CHECK-A57-NEXT: ret896 %bitcast = ptrtoint ptr %sp0 to i64897 %add = add i64 %bitcast, 1898 %addr = inttoptr i64 %add to ptr899 %pix_sp0.0.copyload = load i16, ptr %addr, align 1900 %val = sitofp i16 %pix_sp0.0.copyload to double901 %vmull.i = fmul double %val, %val902 ret double %vmull.i903}904 905define double @sfct23(ptr nocapture %sp0) {906; CHECK-CYC-LABEL: sfct23:907; CHECK-CYC: // %bb.0:908; CHECK-CYC-NEXT: ldur s0, [x0, #1]909; CHECK-CYC-NEXT: sshll v0.2d, v0.2s, #0910; CHECK-CYC-NEXT: scvtf d0, d0911; CHECK-CYC-NEXT: fmul d0, d0, d0912; CHECK-CYC-NEXT: ret913;914; CHECK-A57-LABEL: sfct23:915; CHECK-A57: // %bb.0:916; CHECK-A57-NEXT: ldur w8, [x0, #1]917; CHECK-A57-NEXT: scvtf d0, w8918; CHECK-A57-NEXT: fmul d0, d0, d0919; CHECK-A57-NEXT: ret920 %bitcast = ptrtoint ptr %sp0 to i64921 %add = add i64 %bitcast, 1922 %addr = inttoptr i64 %add to ptr923 %pix_sp0.0.copyload = load i32, ptr %addr, align 1924 %val = sitofp i32 %pix_sp0.0.copyload to double925 %vmull.i = fmul double %val, %val926 ret double %vmull.i927}928 929define double @sfct24(ptr nocapture %sp0) {930; CHECK-LABEL: sfct24:931; CHECK: // %bb.0:932; CHECK-NEXT: ldur d0, [x0, #1]933; CHECK-NEXT: scvtf d0, d0934; CHECK-NEXT: fmul d0, d0, d0935; CHECK-NEXT: ret936 %bitcast = ptrtoint ptr %sp0 to i64937 %add = add i64 %bitcast, 1938 %addr = inttoptr i64 %add to ptr939 %pix_sp0.0.copyload = load i64, ptr %addr, align 1940 %val = sitofp i64 %pix_sp0.0.copyload to double941 %vmull.i = fmul double %val, %val942 ret double %vmull.i943 944}945 946; Check that we do not use SSHLL code sequence when code size is a concern.947define float @codesize_sfct17(ptr nocapture %sp0) optsize {948; CHECK-LABEL: codesize_sfct17:949; CHECK: // %bb.0: // %entry950; CHECK-NEXT: ldursb w8, [x0, #-1]951; CHECK-NEXT: scvtf s0, w8952; CHECK-NEXT: fmul s0, s0, s0953; CHECK-NEXT: ret954entry:955 %bitcast = ptrtoint ptr %sp0 to i64956 %add = add i64 %bitcast, -1957 %addr = inttoptr i64 %add to ptr958 %pix_sp0.0.copyload = load i8, ptr %addr, align 1959 %val = sitofp i8 %pix_sp0.0.copyload to float960 %vmull.i = fmul float %val, %val961 ret float %vmull.i962}963 964define double @codesize_sfct11(ptr nocapture %sp0) minsize {965; CHECK-LABEL: codesize_sfct11:966; CHECK: // %bb.0: // %entry967; CHECK-NEXT: ldr w8, [x0, #4]968; CHECK-NEXT: scvtf d0, w8969; CHECK-NEXT: fmul d0, d0, d0970; CHECK-NEXT: ret971entry:972 %addr = getelementptr i32, ptr %sp0, i64 1973 %pix_sp0.0.copyload = load i32, ptr %addr, align 1974 %val = sitofp i32 %pix_sp0.0.copyload to double975 %vmull.i = fmul double %val, %val976 ret double %vmull.i977}978 979; Adding fp128 custom lowering makes these a little fragile since we have to980; return the correct mix of Legal/Expand from the custom method.981;982; rdar://problem/14991489983 984define float @float_from_i128(i128 %in) {985; CHECK-LABEL: float_from_i128:986; CHECK: // %bb.0:987; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill988; CHECK-NEXT: .cfi_def_cfa_offset 16989; CHECK-NEXT: .cfi_offset w30, -16990; CHECK-NEXT: bl __floatuntisf991; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload992; CHECK-NEXT: ret993 %conv = uitofp i128 %in to float994 ret float %conv995}996 997define double @double_from_i128(i128 %in) {998; CHECK-LABEL: double_from_i128:999; CHECK: // %bb.0:1000; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1001; CHECK-NEXT: .cfi_def_cfa_offset 161002; CHECK-NEXT: .cfi_offset w30, -161003; CHECK-NEXT: bl __floattidf1004; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1005; CHECK-NEXT: ret1006 %conv = sitofp i128 %in to double1007 ret double %conv1008}1009 1010define fp128 @fp128_from_i128(i128 %in) {1011; CHECK-LABEL: fp128_from_i128:1012; CHECK: // %bb.0:1013; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1014; CHECK-NEXT: .cfi_def_cfa_offset 161015; CHECK-NEXT: .cfi_offset w30, -161016; CHECK-NEXT: bl __floatuntitf1017; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1018; CHECK-NEXT: ret1019 %conv = uitofp i128 %in to fp1281020 ret fp128 %conv1021}1022 1023define i128 @i128_from_float(float %in) {1024; CHECK-LABEL: i128_from_float:1025; CHECK: // %bb.0:1026; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1027; CHECK-NEXT: .cfi_def_cfa_offset 161028; CHECK-NEXT: .cfi_offset w30, -161029; CHECK-NEXT: bl __fixsfti1030; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1031; CHECK-NEXT: ret1032 %conv = fptosi float %in to i1281033 ret i128 %conv1034}1035 1036define i128 @i128_from_double(double %in) {1037; CHECK-LABEL: i128_from_double:1038; CHECK: // %bb.0:1039; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1040; CHECK-NEXT: .cfi_def_cfa_offset 161041; CHECK-NEXT: .cfi_offset w30, -161042; CHECK-NEXT: bl __fixunsdfti1043; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1044; CHECK-NEXT: ret1045 %conv = fptoui double %in to i1281046 ret i128 %conv1047}1048 1049define i128 @i128_from_fp128(fp128 %in) {1050; CHECK-LABEL: i128_from_fp128:1051; CHECK: // %bb.0:1052; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1053; CHECK-NEXT: .cfi_def_cfa_offset 161054; CHECK-NEXT: .cfi_offset w30, -161055; CHECK-NEXT: bl __fixtfti1056; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1057; CHECK-NEXT: ret1058 %conv = fptosi fp128 %in to i1281059 ret i128 %conv1060}1061 1062