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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define void @testLeftGood8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {6; CHECK-SD-LABEL: testLeftGood8x8:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: sli.8b v0, v1, #39; CHECK-SD-NEXT: str d0, [x0]10; CHECK-SD-NEXT: ret11;12; CHECK-GI-LABEL: testLeftGood8x8:13; CHECK-GI: // %bb.0:14; CHECK-GI-NEXT: movi.8b v2, #715; CHECK-GI-NEXT: shl.8b v1, v1, #316; CHECK-GI-NEXT: and.8b v0, v0, v217; CHECK-GI-NEXT: orr.8b v0, v0, v118; CHECK-GI-NEXT: str d0, [x0]19; CHECK-GI-NEXT: ret20 %and.i = and <8 x i8> %src1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>21 %vshl_n = shl <8 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>22 %result = or <8 x i8> %and.i, %vshl_n23 store <8 x i8> %result, ptr %dest, align 824 ret void25}26 27define void @testLeftBad8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {28; CHECK-SD-LABEL: testLeftBad8x8:29; CHECK-SD: // %bb.0:30; CHECK-SD-NEXT: movi.8b v2, #16531; CHECK-SD-NEXT: add.8b v1, v1, v132; CHECK-SD-NEXT: and.8b v0, v0, v233; CHECK-SD-NEXT: orr.8b v0, v0, v134; CHECK-SD-NEXT: str d0, [x0]35; CHECK-SD-NEXT: ret36;37; CHECK-GI-LABEL: testLeftBad8x8:38; CHECK-GI: // %bb.0:39; CHECK-GI-NEXT: movi.8b v2, #16540; CHECK-GI-NEXT: shl.8b v1, v1, #141; CHECK-GI-NEXT: and.8b v0, v0, v242; CHECK-GI-NEXT: orr.8b v0, v0, v143; CHECK-GI-NEXT: str d0, [x0]44; CHECK-GI-NEXT: ret45 %and.i = and <8 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>46 %vshl_n = shl <8 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>47 %result = or <8 x i8> %and.i, %vshl_n48 store <8 x i8> %result, ptr %dest, align 849 ret void50}51 52define void @testRightGood8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {53; CHECK-SD-LABEL: testRightGood8x8:54; CHECK-SD: // %bb.0:55; CHECK-SD-NEXT: sri.8b v0, v1, #356; CHECK-SD-NEXT: str d0, [x0]57; CHECK-SD-NEXT: ret58;59; CHECK-GI-LABEL: testRightGood8x8:60; CHECK-GI: // %bb.0:61; CHECK-GI-NEXT: movi.8b v2, #22462; CHECK-GI-NEXT: ushr.8b v1, v1, #363; CHECK-GI-NEXT: and.8b v0, v0, v264; CHECK-GI-NEXT: orr.8b v0, v0, v165; CHECK-GI-NEXT: str d0, [x0]66; CHECK-GI-NEXT: ret67 %and.i = and <8 x i8> %src1, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>68 %vshl_n = lshr <8 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>69 %result = or <8 x i8> %and.i, %vshl_n70 store <8 x i8> %result, ptr %dest, align 871 ret void72}73 74define void @testRightBad8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {75; CHECK-LABEL: testRightBad8x8:76; CHECK: // %bb.0:77; CHECK-NEXT: movi.8b v2, #16578; CHECK-NEXT: ushr.8b v1, v1, #179; CHECK-NEXT: and.8b v0, v0, v280; CHECK-NEXT: orr.8b v0, v0, v181; CHECK-NEXT: str d0, [x0]82; CHECK-NEXT: ret83 %and.i = and <8 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>84 %vshl_n = lshr <8 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>85 %result = or <8 x i8> %and.i, %vshl_n86 store <8 x i8> %result, ptr %dest, align 887 ret void88}89 90define void @testLeftGood16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {91; CHECK-SD-LABEL: testLeftGood16x8:92; CHECK-SD: // %bb.0:93; CHECK-SD-NEXT: sli.16b v0, v1, #394; CHECK-SD-NEXT: str q0, [x0]95; CHECK-SD-NEXT: ret96;97; CHECK-GI-LABEL: testLeftGood16x8:98; CHECK-GI: // %bb.0:99; CHECK-GI-NEXT: movi.16b v2, #7100; CHECK-GI-NEXT: shl.16b v1, v1, #3101; CHECK-GI-NEXT: and.16b v0, v0, v2102; CHECK-GI-NEXT: orr.16b v0, v0, v1103; CHECK-GI-NEXT: str q0, [x0]104; CHECK-GI-NEXT: ret105 %and.i = and <16 x i8> %src1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>106 %vshl_n = shl <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>107 %result = or <16 x i8> %and.i, %vshl_n108 store <16 x i8> %result, ptr %dest, align 16109 ret void110}111 112define void @testLeftBad16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {113; CHECK-SD-LABEL: testLeftBad16x8:114; CHECK-SD: // %bb.0:115; CHECK-SD-NEXT: movi.16b v2, #165116; CHECK-SD-NEXT: add.16b v1, v1, v1117; CHECK-SD-NEXT: and.16b v0, v0, v2118; CHECK-SD-NEXT: orr.16b v0, v0, v1119; CHECK-SD-NEXT: str q0, [x0]120; CHECK-SD-NEXT: ret121;122; CHECK-GI-LABEL: testLeftBad16x8:123; CHECK-GI: // %bb.0:124; CHECK-GI-NEXT: movi.16b v2, #165125; CHECK-GI-NEXT: shl.16b v1, v1, #1126; CHECK-GI-NEXT: and.16b v0, v0, v2127; CHECK-GI-NEXT: orr.16b v0, v0, v1128; CHECK-GI-NEXT: str q0, [x0]129; CHECK-GI-NEXT: ret130 %and.i = and <16 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>131 %vshl_n = shl <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>132 %result = or <16 x i8> %and.i, %vshl_n133 store <16 x i8> %result, ptr %dest, align 16134 ret void135}136 137define void @testRightGood16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {138; CHECK-SD-LABEL: testRightGood16x8:139; CHECK-SD: // %bb.0:140; CHECK-SD-NEXT: sri.16b v0, v1, #3141; CHECK-SD-NEXT: str q0, [x0]142; CHECK-SD-NEXT: ret143;144; CHECK-GI-LABEL: testRightGood16x8:145; CHECK-GI: // %bb.0:146; CHECK-GI-NEXT: movi.16b v2, #224147; CHECK-GI-NEXT: ushr.16b v1, v1, #3148; CHECK-GI-NEXT: and.16b v0, v0, v2149; CHECK-GI-NEXT: orr.16b v0, v0, v1150; CHECK-GI-NEXT: str q0, [x0]151; CHECK-GI-NEXT: ret152 %and.i = and <16 x i8> %src1, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>153 %vshl_n = lshr <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>154 %result = or <16 x i8> %and.i, %vshl_n155 store <16 x i8> %result, ptr %dest, align 16156 ret void157}158 159define void @testRightBad16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {160; CHECK-LABEL: testRightBad16x8:161; CHECK: // %bb.0:162; CHECK-NEXT: movi.16b v2, #165163; CHECK-NEXT: ushr.16b v1, v1, #1164; CHECK-NEXT: and.16b v0, v0, v2165; CHECK-NEXT: orr.16b v0, v0, v1166; CHECK-NEXT: str q0, [x0]167; CHECK-NEXT: ret168 %and.i = and <16 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>169 %vshl_n = lshr <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>170 %result = or <16 x i8> %and.i, %vshl_n171 store <16 x i8> %result, ptr %dest, align 16172 ret void173}174 175define void @testLeftGood4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {176; CHECK-SD-LABEL: testLeftGood4x16:177; CHECK-SD: // %bb.0:178; CHECK-SD-NEXT: sli.4h v0, v1, #14179; CHECK-SD-NEXT: str d0, [x0]180; CHECK-SD-NEXT: ret181;182; CHECK-GI-LABEL: testLeftGood4x16:183; CHECK-GI: // %bb.0:184; CHECK-GI-NEXT: mvni.4h v2, #192, lsl #8185; CHECK-GI-NEXT: shl.4h v1, v1, #14186; CHECK-GI-NEXT: and.8b v0, v0, v2187; CHECK-GI-NEXT: orr.8b v0, v0, v1188; CHECK-GI-NEXT: str d0, [x0]189; CHECK-GI-NEXT: ret190 %and.i = and <4 x i16> %src1, <i16 16383, i16 16383, i16 16383, i16 16383>191 %vshl_n = shl <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>192 %result = or <4 x i16> %and.i, %vshl_n193 store <4 x i16> %result, ptr %dest, align 8194 ret void195}196 197define void @testLeftBad4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {198; CHECK-SD-LABEL: testLeftBad4x16:199; CHECK-SD: // %bb.0:200; CHECK-SD-NEXT: mov w8, #16500 // =0x4074201; CHECK-SD-NEXT: shl.4h v1, v1, #14202; CHECK-SD-NEXT: dup.4h v2, w8203; CHECK-SD-NEXT: and.8b v0, v0, v2204; CHECK-SD-NEXT: orr.8b v0, v0, v1205; CHECK-SD-NEXT: str d0, [x0]206; CHECK-SD-NEXT: ret207;208; CHECK-GI-LABEL: testLeftBad4x16:209; CHECK-GI: // %bb.0:210; CHECK-GI-NEXT: adrp x8, .LCPI9_0211; CHECK-GI-NEXT: shl.4h v1, v1, #14212; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI9_0]213; CHECK-GI-NEXT: and.8b v0, v0, v2214; CHECK-GI-NEXT: orr.8b v0, v0, v1215; CHECK-GI-NEXT: str d0, [x0]216; CHECK-GI-NEXT: ret217 %and.i = and <4 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500>218 %vshl_n = shl <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>219 %result = or <4 x i16> %and.i, %vshl_n220 store <4 x i16> %result, ptr %dest, align 8221 ret void222}223 224define void @testRightGood4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {225; CHECK-SD-LABEL: testRightGood4x16:226; CHECK-SD: // %bb.0:227; CHECK-SD-NEXT: sri.4h v0, v1, #14228; CHECK-SD-NEXT: str d0, [x0]229; CHECK-SD-NEXT: ret230;231; CHECK-GI-LABEL: testRightGood4x16:232; CHECK-GI: // %bb.0:233; CHECK-GI-NEXT: mvni.4h v2, #3234; CHECK-GI-NEXT: ushr.4h v1, v1, #14235; CHECK-GI-NEXT: and.8b v0, v0, v2236; CHECK-GI-NEXT: orr.8b v0, v0, v1237; CHECK-GI-NEXT: str d0, [x0]238; CHECK-GI-NEXT: ret239 %and.i = and <4 x i16> %src1, <i16 65532, i16 65532, i16 65532, i16 65532>240 %vshl_n = lshr <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>241 %result = or <4 x i16> %and.i, %vshl_n242 store <4 x i16> %result, ptr %dest, align 8243 ret void244}245 246define void @testRightBad4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {247; CHECK-SD-LABEL: testRightBad4x16:248; CHECK-SD: // %bb.0:249; CHECK-SD-NEXT: mov w8, #16500 // =0x4074250; CHECK-SD-NEXT: dup.4h v2, w8251; CHECK-SD-NEXT: and.8b v0, v0, v2252; CHECK-SD-NEXT: usra.4h v0, v1, #14253; CHECK-SD-NEXT: str d0, [x0]254; CHECK-SD-NEXT: ret255;256; CHECK-GI-LABEL: testRightBad4x16:257; CHECK-GI: // %bb.0:258; CHECK-GI-NEXT: adrp x8, .LCPI11_0259; CHECK-GI-NEXT: ushr.4h v1, v1, #14260; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI11_0]261; CHECK-GI-NEXT: and.8b v0, v0, v2262; CHECK-GI-NEXT: orr.8b v0, v0, v1263; CHECK-GI-NEXT: str d0, [x0]264; CHECK-GI-NEXT: ret265 %and.i = and <4 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500>266 %vshl_n = lshr <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>267 %result = or <4 x i16> %and.i, %vshl_n268 store <4 x i16> %result, ptr %dest, align 8269 ret void270}271 272define void @testLeftGood8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {273; CHECK-SD-LABEL: testLeftGood8x16:274; CHECK-SD: // %bb.0:275; CHECK-SD-NEXT: sli.8h v0, v1, #14276; CHECK-SD-NEXT: str q0, [x0]277; CHECK-SD-NEXT: ret278;279; CHECK-GI-LABEL: testLeftGood8x16:280; CHECK-GI: // %bb.0:281; CHECK-GI-NEXT: mvni.8h v2, #192, lsl #8282; CHECK-GI-NEXT: shl.8h v1, v1, #14283; CHECK-GI-NEXT: and.16b v0, v0, v2284; CHECK-GI-NEXT: orr.16b v0, v0, v1285; CHECK-GI-NEXT: str q0, [x0]286; CHECK-GI-NEXT: ret287 %and.i = and <8 x i16> %src1, <i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383>288 %vshl_n = shl <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>289 %result = or <8 x i16> %and.i, %vshl_n290 store <8 x i16> %result, ptr %dest, align 16291 ret void292}293 294define void @testLeftBad8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {295; CHECK-SD-LABEL: testLeftBad8x16:296; CHECK-SD: // %bb.0:297; CHECK-SD-NEXT: mov w8, #16500 // =0x4074298; CHECK-SD-NEXT: shl.8h v1, v1, #14299; CHECK-SD-NEXT: dup.8h v2, w8300; CHECK-SD-NEXT: and.16b v0, v0, v2301; CHECK-SD-NEXT: orr.16b v0, v0, v1302; CHECK-SD-NEXT: str q0, [x0]303; CHECK-SD-NEXT: ret304;305; CHECK-GI-LABEL: testLeftBad8x16:306; CHECK-GI: // %bb.0:307; CHECK-GI-NEXT: adrp x8, .LCPI13_0308; CHECK-GI-NEXT: shl.8h v1, v1, #14309; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]310; CHECK-GI-NEXT: and.16b v0, v0, v2311; CHECK-GI-NEXT: orr.16b v0, v0, v1312; CHECK-GI-NEXT: str q0, [x0]313; CHECK-GI-NEXT: ret314 %and.i = and <8 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500>315 %vshl_n = shl <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>316 %result = or <8 x i16> %and.i, %vshl_n317 store <8 x i16> %result, ptr %dest, align 16318 ret void319}320 321define void @testRightGood8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {322; CHECK-SD-LABEL: testRightGood8x16:323; CHECK-SD: // %bb.0:324; CHECK-SD-NEXT: sri.8h v0, v1, #14325; CHECK-SD-NEXT: str q0, [x0]326; CHECK-SD-NEXT: ret327;328; CHECK-GI-LABEL: testRightGood8x16:329; CHECK-GI: // %bb.0:330; CHECK-GI-NEXT: mvni.8h v2, #3331; CHECK-GI-NEXT: ushr.8h v1, v1, #14332; CHECK-GI-NEXT: and.16b v0, v0, v2333; CHECK-GI-NEXT: orr.16b v0, v0, v1334; CHECK-GI-NEXT: str q0, [x0]335; CHECK-GI-NEXT: ret336 %and.i = and <8 x i16> %src1, <i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532>337 %vshl_n = lshr <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>338 %result = or <8 x i16> %and.i, %vshl_n339 store <8 x i16> %result, ptr %dest, align 16340 ret void341}342 343define void @testRightBad8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {344; CHECK-SD-LABEL: testRightBad8x16:345; CHECK-SD: // %bb.0:346; CHECK-SD-NEXT: mov w8, #16500 // =0x4074347; CHECK-SD-NEXT: dup.8h v2, w8348; CHECK-SD-NEXT: and.16b v0, v0, v2349; CHECK-SD-NEXT: usra.8h v0, v1, #14350; CHECK-SD-NEXT: str q0, [x0]351; CHECK-SD-NEXT: ret352;353; CHECK-GI-LABEL: testRightBad8x16:354; CHECK-GI: // %bb.0:355; CHECK-GI-NEXT: adrp x8, .LCPI15_0356; CHECK-GI-NEXT: ushr.8h v1, v1, #14357; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_0]358; CHECK-GI-NEXT: and.16b v0, v0, v2359; CHECK-GI-NEXT: orr.16b v0, v0, v1360; CHECK-GI-NEXT: str q0, [x0]361; CHECK-GI-NEXT: ret362 %and.i = and <8 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500>363 %vshl_n = lshr <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>364 %result = or <8 x i16> %and.i, %vshl_n365 store <8 x i16> %result, ptr %dest, align 16366 ret void367}368 369define void @testLeftGood2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {370; CHECK-SD-LABEL: testLeftGood2x32:371; CHECK-SD: // %bb.0:372; CHECK-SD-NEXT: sli.2s v0, v1, #22373; CHECK-SD-NEXT: str d0, [x0]374; CHECK-SD-NEXT: ret375;376; CHECK-GI-LABEL: testLeftGood2x32:377; CHECK-GI: // %bb.0:378; CHECK-GI-NEXT: movi.2s v2, #63, msl #16379; CHECK-GI-NEXT: shl.2s v1, v1, #22380; CHECK-GI-NEXT: and.8b v0, v0, v2381; CHECK-GI-NEXT: orr.8b v0, v0, v1382; CHECK-GI-NEXT: str d0, [x0]383; CHECK-GI-NEXT: ret384 %and.i = and <2 x i32> %src1, <i32 4194303, i32 4194303>385 %vshl_n = shl <2 x i32> %src2, <i32 22, i32 22>386 %result = or <2 x i32> %and.i, %vshl_n387 store <2 x i32> %result, ptr %dest, align 8388 ret void389}390 391define void @testLeftBad2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {392; CHECK-SD-LABEL: testLeftBad2x32:393; CHECK-SD: // %bb.0:394; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc395; CHECK-SD-NEXT: shl.2s v1, v1, #22396; CHECK-SD-NEXT: dup.2s v2, w8397; CHECK-SD-NEXT: and.8b v0, v0, v2398; CHECK-SD-NEXT: orr.8b v0, v0, v1399; CHECK-SD-NEXT: str d0, [x0]400; CHECK-SD-NEXT: ret401;402; CHECK-GI-LABEL: testLeftBad2x32:403; CHECK-GI: // %bb.0:404; CHECK-GI-NEXT: adrp x8, .LCPI17_0405; CHECK-GI-NEXT: shl.2s v1, v1, #22406; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI17_0]407; CHECK-GI-NEXT: and.8b v0, v0, v2408; CHECK-GI-NEXT: orr.8b v0, v0, v1409; CHECK-GI-NEXT: str d0, [x0]410; CHECK-GI-NEXT: ret411 %and.i = and <2 x i32> %src1, <i32 4194300, i32 4194300>412 %vshl_n = shl <2 x i32> %src2, <i32 22, i32 22>413 %result = or <2 x i32> %and.i, %vshl_n414 store <2 x i32> %result, ptr %dest, align 8415 ret void416}417 418define void @testRightGood2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {419; CHECK-SD-LABEL: testRightGood2x32:420; CHECK-SD: // %bb.0:421; CHECK-SD-NEXT: sri.2s v0, v1, #22422; CHECK-SD-NEXT: str d0, [x0]423; CHECK-SD-NEXT: ret424;425; CHECK-GI-LABEL: testRightGood2x32:426; CHECK-GI: // %bb.0:427; CHECK-GI-NEXT: mvni.2s v2, #3, msl #8428; CHECK-GI-NEXT: ushr.2s v1, v1, #22429; CHECK-GI-NEXT: and.8b v0, v0, v2430; CHECK-GI-NEXT: orr.8b v0, v0, v1431; CHECK-GI-NEXT: str d0, [x0]432; CHECK-GI-NEXT: ret433 %and.i = and <2 x i32> %src1, <i32 4294966272, i32 4294966272>434 %vshl_n = lshr <2 x i32> %src2, <i32 22, i32 22>435 %result = or <2 x i32> %and.i, %vshl_n436 store <2 x i32> %result, ptr %dest, align 8437 ret void438}439 440define void @testRightBad2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {441; CHECK-SD-LABEL: testRightBad2x32:442; CHECK-SD: // %bb.0:443; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc444; CHECK-SD-NEXT: ushr.2s v1, v1, #22445; CHECK-SD-NEXT: dup.2s v2, w8446; CHECK-SD-NEXT: and.8b v0, v0, v2447; CHECK-SD-NEXT: orr.8b v0, v0, v1448; CHECK-SD-NEXT: str d0, [x0]449; CHECK-SD-NEXT: ret450;451; CHECK-GI-LABEL: testRightBad2x32:452; CHECK-GI: // %bb.0:453; CHECK-GI-NEXT: adrp x8, .LCPI19_0454; CHECK-GI-NEXT: ushr.2s v1, v1, #22455; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI19_0]456; CHECK-GI-NEXT: and.8b v0, v0, v2457; CHECK-GI-NEXT: orr.8b v0, v0, v1458; CHECK-GI-NEXT: str d0, [x0]459; CHECK-GI-NEXT: ret460 %and.i = and <2 x i32> %src1, <i32 4194300, i32 4194300>461 %vshl_n = lshr <2 x i32> %src2, <i32 22, i32 22>462 %result = or <2 x i32> %and.i, %vshl_n463 store <2 x i32> %result, ptr %dest, align 8464 ret void465}466 467define void @testLeftGood4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {468; CHECK-SD-LABEL: testLeftGood4x32:469; CHECK-SD: // %bb.0:470; CHECK-SD-NEXT: sli.4s v0, v1, #22471; CHECK-SD-NEXT: str q0, [x0]472; CHECK-SD-NEXT: ret473;474; CHECK-GI-LABEL: testLeftGood4x32:475; CHECK-GI: // %bb.0:476; CHECK-GI-NEXT: movi.4s v2, #63, msl #16477; CHECK-GI-NEXT: shl.4s v1, v1, #22478; CHECK-GI-NEXT: and.16b v0, v0, v2479; CHECK-GI-NEXT: orr.16b v0, v0, v1480; CHECK-GI-NEXT: str q0, [x0]481; CHECK-GI-NEXT: ret482 %and.i = and <4 x i32> %src1, <i32 4194303, i32 4194303, i32 4194303, i32 4194303>483 %vshl_n = shl <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>484 %result = or <4 x i32> %and.i, %vshl_n485 store <4 x i32> %result, ptr %dest, align 16486 ret void487}488 489define void @testLeftBad4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {490; CHECK-SD-LABEL: testLeftBad4x32:491; CHECK-SD: // %bb.0:492; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc493; CHECK-SD-NEXT: shl.4s v1, v1, #22494; CHECK-SD-NEXT: dup.4s v2, w8495; CHECK-SD-NEXT: and.16b v0, v0, v2496; CHECK-SD-NEXT: orr.16b v0, v0, v1497; CHECK-SD-NEXT: str q0, [x0]498; CHECK-SD-NEXT: ret499;500; CHECK-GI-LABEL: testLeftBad4x32:501; CHECK-GI: // %bb.0:502; CHECK-GI-NEXT: adrp x8, .LCPI21_0503; CHECK-GI-NEXT: shl.4s v1, v1, #22504; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI21_0]505; CHECK-GI-NEXT: and.16b v0, v0, v2506; CHECK-GI-NEXT: orr.16b v0, v0, v1507; CHECK-GI-NEXT: str q0, [x0]508; CHECK-GI-NEXT: ret509 %and.i = and <4 x i32> %src1, <i32 4194300, i32 4194300, i32 4194300, i32 4194300>510 %vshl_n = shl <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>511 %result = or <4 x i32> %and.i, %vshl_n512 store <4 x i32> %result, ptr %dest, align 16513 ret void514}515 516define void @testRightGood4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {517; CHECK-SD-LABEL: testRightGood4x32:518; CHECK-SD: // %bb.0:519; CHECK-SD-NEXT: sri.4s v0, v1, #22520; CHECK-SD-NEXT: str q0, [x0]521; CHECK-SD-NEXT: ret522;523; CHECK-GI-LABEL: testRightGood4x32:524; CHECK-GI: // %bb.0:525; CHECK-GI-NEXT: mvni.4s v2, #3, msl #8526; CHECK-GI-NEXT: ushr.4s v1, v1, #22527; CHECK-GI-NEXT: and.16b v0, v0, v2528; CHECK-GI-NEXT: orr.16b v0, v0, v1529; CHECK-GI-NEXT: str q0, [x0]530; CHECK-GI-NEXT: ret531 %and.i = and <4 x i32> %src1, <i32 4294966272, i32 4294966272, i32 4294966272, i32 4294966272>532 %vshl_n = lshr <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>533 %result = or <4 x i32> %and.i, %vshl_n534 store <4 x i32> %result, ptr %dest, align 16535 ret void536}537 538define void @testRightBad4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {539; CHECK-SD-LABEL: testRightBad4x32:540; CHECK-SD: // %bb.0:541; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc542; CHECK-SD-NEXT: ushr.4s v1, v1, #22543; CHECK-SD-NEXT: dup.4s v2, w8544; CHECK-SD-NEXT: and.16b v0, v0, v2545; CHECK-SD-NEXT: orr.16b v0, v0, v1546; CHECK-SD-NEXT: str q0, [x0]547; CHECK-SD-NEXT: ret548;549; CHECK-GI-LABEL: testRightBad4x32:550; CHECK-GI: // %bb.0:551; CHECK-GI-NEXT: adrp x8, .LCPI23_0552; CHECK-GI-NEXT: ushr.4s v1, v1, #22553; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI23_0]554; CHECK-GI-NEXT: and.16b v0, v0, v2555; CHECK-GI-NEXT: orr.16b v0, v0, v1556; CHECK-GI-NEXT: str q0, [x0]557; CHECK-GI-NEXT: ret558 %and.i = and <4 x i32> %src1, <i32 4194300, i32 4194300, i32 4194300, i32 4194300>559 %vshl_n = lshr <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>560 %result = or <4 x i32> %and.i, %vshl_n561 store <4 x i32> %result, ptr %dest, align 16562 ret void563}564 565define void @testLeftGood2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {566; CHECK-SD-LABEL: testLeftGood2x64:567; CHECK-SD: // %bb.0:568; CHECK-SD-NEXT: sli.2d v0, v1, #48569; CHECK-SD-NEXT: str q0, [x0]570; CHECK-SD-NEXT: ret571;572; CHECK-GI-LABEL: testLeftGood2x64:573; CHECK-GI: // %bb.0:574; CHECK-GI-NEXT: movi.2d v2, #0x00ffffffffffff575; CHECK-GI-NEXT: shl.2d v1, v1, #48576; CHECK-GI-NEXT: and.16b v0, v0, v2577; CHECK-GI-NEXT: orr.16b v0, v0, v1578; CHECK-GI-NEXT: str q0, [x0]579; CHECK-GI-NEXT: ret580 %and.i = and <2 x i64> %src1, <i64 281474976710655, i64 281474976710655>581 %vshl_n = shl <2 x i64> %src2, <i64 48, i64 48>582 %result = or <2 x i64> %and.i, %vshl_n583 store <2 x i64> %result, ptr %dest, align 16584 ret void585}586 587define void @testLeftBad2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {588; CHECK-SD-LABEL: testLeftBad2x64:589; CHECK-SD: // %bb.0:590; CHECK-SD-NEXT: mov x8, #10 // =0xa591; CHECK-SD-NEXT: shl.2d v1, v1, #48592; CHECK-SD-NEXT: movk x8, #1, lsl #48593; CHECK-SD-NEXT: dup.2d v2, x8594; CHECK-SD-NEXT: and.16b v0, v0, v2595; CHECK-SD-NEXT: orr.16b v0, v0, v1596; CHECK-SD-NEXT: str q0, [x0]597; CHECK-SD-NEXT: ret598;599; CHECK-GI-LABEL: testLeftBad2x64:600; CHECK-GI: // %bb.0:601; CHECK-GI-NEXT: adrp x8, .LCPI25_0602; CHECK-GI-NEXT: shl.2d v1, v1, #48603; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI25_0]604; CHECK-GI-NEXT: and.16b v0, v0, v2605; CHECK-GI-NEXT: orr.16b v0, v0, v1606; CHECK-GI-NEXT: str q0, [x0]607; CHECK-GI-NEXT: ret608 %and.i = and <2 x i64> %src1, <i64 281474976710666, i64 281474976710666>609 %vshl_n = shl <2 x i64> %src2, <i64 48, i64 48>610 %result = or <2 x i64> %and.i, %vshl_n611 store <2 x i64> %result, ptr %dest, align 16612 ret void613}614 615define void @testRightGood2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {616; CHECK-SD-LABEL: testRightGood2x64:617; CHECK-SD: // %bb.0:618; CHECK-SD-NEXT: sri.2d v0, v1, #48619; CHECK-SD-NEXT: str q0, [x0]620; CHECK-SD-NEXT: ret621;622; CHECK-GI-LABEL: testRightGood2x64:623; CHECK-GI: // %bb.0:624; CHECK-GI-NEXT: movi.2d v2, #0xffffffffffff0000625; CHECK-GI-NEXT: ushr.2d v1, v1, #48626; CHECK-GI-NEXT: and.16b v0, v0, v2627; CHECK-GI-NEXT: orr.16b v0, v0, v1628; CHECK-GI-NEXT: str q0, [x0]629; CHECK-GI-NEXT: ret630 %and.i = and <2 x i64> %src1, <i64 18446744073709486080, i64 18446744073709486080>631 %vshl_n = lshr <2 x i64> %src2, <i64 48, i64 48>632 %result = or <2 x i64> %and.i, %vshl_n633 store <2 x i64> %result, ptr %dest, align 16634 ret void635}636 637define void @testRightBad2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {638; CHECK-SD-LABEL: testRightBad2x64:639; CHECK-SD: // %bb.0:640; CHECK-SD-NEXT: mov x8, #10 // =0xa641; CHECK-SD-NEXT: ushr.2d v1, v1, #48642; CHECK-SD-NEXT: movk x8, #1, lsl #48643; CHECK-SD-NEXT: dup.2d v2, x8644; CHECK-SD-NEXT: and.16b v0, v0, v2645; CHECK-SD-NEXT: orr.16b v0, v0, v1646; CHECK-SD-NEXT: str q0, [x0]647; CHECK-SD-NEXT: ret648;649; CHECK-GI-LABEL: testRightBad2x64:650; CHECK-GI: // %bb.0:651; CHECK-GI-NEXT: adrp x8, .LCPI27_0652; CHECK-GI-NEXT: ushr.2d v1, v1, #48653; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI27_0]654; CHECK-GI-NEXT: and.16b v0, v0, v2655; CHECK-GI-NEXT: orr.16b v0, v0, v1656; CHECK-GI-NEXT: str q0, [x0]657; CHECK-GI-NEXT: ret658 %and.i = and <2 x i64> %src1, <i64 281474976710666, i64 281474976710666>659 %vshl_n = lshr <2 x i64> %src2, <i64 48, i64 48>660 %result = or <2 x i64> %and.i, %vshl_n661 store <2 x i64> %result, ptr %dest, align 16662 ret void663}664 665define void @testLeftShouldNotCreateSLI1x128(<1 x i128> %src1, <1 x i128> %src2, ptr %dest) nounwind {666; CHECK-SD-LABEL: testLeftShouldNotCreateSLI1x128:667; CHECK-SD: // %bb.0:668; CHECK-SD-NEXT: bfi x1, x2, #6, #58669; CHECK-SD-NEXT: stp x0, x1, [x4]670; CHECK-SD-NEXT: ret671;672; CHECK-GI-LABEL: testLeftShouldNotCreateSLI1x128:673; CHECK-GI: // %bb.0:674; CHECK-GI-NEXT: mov.d v0[0], x0675; CHECK-GI-NEXT: bfi x1, x2, #6, #58676; CHECK-GI-NEXT: mov.d v0[1], x1677; CHECK-GI-NEXT: str q0, [x4]678; CHECK-GI-NEXT: ret679 %and.i = and <1 x i128> %src1, <i128 1180591620717411303423>680 %vshl_n = shl <1 x i128> %src2, <i128 70>681 %result = or <1 x i128> %and.i, %vshl_n682 store <1 x i128> %result, ptr %dest, align 16683 ret void684}685 686define void @testLeftNotAllConstantBuildVec8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {687; CHECK-LABEL: testLeftNotAllConstantBuildVec8x8:688; CHECK: // %bb.0:689; CHECK-NEXT: adrp x8, .LCPI29_0690; CHECK-NEXT: shl.8b v1, v1, #3691; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI29_0]692; CHECK-NEXT: and.8b v0, v0, v2693; CHECK-NEXT: orr.8b v0, v0, v1694; CHECK-NEXT: str d0, [x0]695; CHECK-NEXT: ret696 %and.i = and <8 x i8> %src1, <i8 7, i8 7, i8 255, i8 7, i8 7, i8 7, i8 255, i8 7>697 %vshl_n = shl <8 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>698 %result = or <8 x i8> %and.i, %vshl_n699 store <8 x i8> %result, ptr %dest, align 8700 ret void701}702