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1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s3; RUN: llc < %s -global-isel=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s4 5define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {6; CHECK: test_vmaxv_s87; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v08; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]9; CHECK-NEXT: ret10entry:11 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)12 %0 = trunc i32 %vmaxv.i to i813 ret i8 %014}15 16define signext i16 @test_vmaxv_s16(<4 x i16> %a1) {17; CHECK: test_vmaxv_s1618; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v019; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]20; CHECK-NEXT: ret21entry:22 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)23 %0 = trunc i32 %vmaxv.i to i1624 ret i16 %025}26 27define i32 @test_vmaxv_s32(<2 x i32> %a1) {28; CHECK: test_vmaxv_s3229; 2 x i32 is not supported by the ISA, thus, this is a special case30; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v031; CHECK-NEXT: fmov w0, s[[REGNUM]]32; CHECK-NEXT: ret33entry:34 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)35 ret i32 %vmaxv.i36}37 38define signext i8 @test_vmaxvq_s8(<16 x i8> %a1) {39; CHECK: test_vmaxvq_s840; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v041; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]42; CHECK-NEXT: ret43entry:44 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)45 %0 = trunc i32 %vmaxv.i to i846 ret i8 %047}48 49define signext i16 @test_vmaxvq_s16(<8 x i16> %a1) {50; CHECK: test_vmaxvq_s1651; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v052; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]53; CHECK-NEXT: ret54entry:55 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)56 %0 = trunc i32 %vmaxv.i to i1657 ret i16 %058}59 60define i32 @test_vmaxvq_s32(<4 x i32> %a1) {61; CHECK: test_vmaxvq_s3262; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v063; CHECK-NEXT: fmov w0, [[REGNUM]]64; CHECK-NEXT: ret65entry:66 %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a1)67 ret i32 %vmaxv.i68}69 70define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {71; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:72; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v173; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]74; CHECK-NEXT: ret75entry:76 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)77 %1 = trunc i32 %0 to i878 %2 = insertelement <8 x i8> %a1, i8 %1, i32 379 ret <8 x i8> %280}81 82define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {83; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:84; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v185; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]86; CHECK-NEXT: ret87entry:88 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)89 %1 = trunc i32 %0 to i1690 %2 = insertelement <4 x i16> %a1, i16 %1, i32 391 ret <4 x i16> %292}93 94define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {95; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:96; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v197; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]98; CHECK-NEXT: ret99entry:100 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)101 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1102 ret <2 x i32> %1103}104 105define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {106; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:107; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1108; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]109; CHECK-NEXT: ret110entry:111 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)112 %1 = trunc i32 %0 to i8113 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3114 ret <16 x i8> %2115}116 117define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {118; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:119; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1120; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]121; CHECK-NEXT: ret122entry:123 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)124 %1 = trunc i32 %0 to i16125 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3126 ret <8 x i16> %2127}128 129define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {130; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:131; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1132; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]133; CHECK-NEXT: ret134entry:135 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)136 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3137 ret <4 x i32> %1138}139 140declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)141declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)142declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)143declare i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32>)144declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)145declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)146 147