54 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi | FileCheck %s3 4; Check if sqshl/uqshl with constant shift amount can be selected.5define i64 @test_vqshld_s64_i(i64 %a) {6; CHECK-LABEL: test_vqshld_s64_i:7; CHECK: // %bb.0:8; CHECK-NEXT: fmov d0, x09; CHECK-NEXT: sqshl d0, d0, #3610; CHECK-NEXT: fmov x0, d011; CHECK-NEXT: ret12 %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)13 ret i64 %114}15 16define i64 @test_vqshld_u64_i(i64 %a) {17; CHECK-LABEL: test_vqshld_u64_i:18; CHECK: // %bb.0:19; CHECK-NEXT: fmov d0, x020; CHECK-NEXT: uqshl d0, d0, #3621; CHECK-NEXT: fmov x0, d022; CHECK-NEXT: ret23 %1 = tail call i64 @llvm.aarch64.neon.uqshl.i64(i64 %a, i64 36)24 ret i64 %125}26 27define i32 @test_vqshld_s32_i(i32 %a) {28; CHECK-LABEL: test_vqshld_s32_i:29; CHECK: // %bb.0:30; CHECK-NEXT: fmov s0, w031; CHECK-NEXT: sqshl s0, s0, #1632; CHECK-NEXT: fmov w0, s033; CHECK-NEXT: ret34 %1 = tail call i32 @llvm.aarch64.neon.sqshl.i32(i32 %a, i32 16)35 ret i32 %136}37 38define i32 @test_vqshld_u32_i(i32 %a) {39; CHECK-LABEL: test_vqshld_u32_i:40; CHECK: // %bb.0:41; CHECK-NEXT: fmov s0, w042; CHECK-NEXT: uqshl s0, s0, #1643; CHECK-NEXT: fmov w0, s044; CHECK-NEXT: ret45 %1 = tail call i32 @llvm.aarch64.neon.uqshl.i32(i32 %a, i32 16)46 ret i32 %147}48 49declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64)50declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)51 52declare i32 @llvm.aarch64.neon.uqshl.i32(i32, i32)53declare i32 @llvm.aarch64.neon.sqshl.i32(i32, i32)54