1410 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "(kill|%bb|ret)" --version 52; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,SD-CHECK3; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,GI-CHECK4; The instruction latencies of Exynos-M3 trigger the transform we see under the Exynos check.5; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m3 | FileCheck --check-prefixes=CHECK,EXYNOS %s6 7define void @st1lane_16b(<16 x i8> %A, ptr %D) {8; SD-CHECK-LABEL: st1lane_16b:9; SD-CHECK: mov b0, v0[1]10; SD-CHECK: stur b0, [x0, #1]11;12; GI-CHECK-LABEL: st1lane_16b:13; GI-CHECK: add x8, x0, #114; GI-CHECK: st1.b { v0 }[1], [x8]15;16; EXYNOS-LABEL: st1lane_16b:17; EXYNOS: mov b0, v0[1]18; EXYNOS: stur b0, [x0, #1]19 %ptr = getelementptr i8, ptr %D, i64 120 %tmp = extractelement <16 x i8> %A, i32 121 store i8 %tmp, ptr %ptr22 ret void23}24 25define void @st1lane0_16b(<16 x i8> %A, ptr %D) {26; SD-CHECK-LABEL: st1lane0_16b:27; SD-CHECK: stur b0, [x0, #1]28;29; GI-CHECK-LABEL: st1lane0_16b:30; GI-CHECK: add x8, x0, #131; GI-CHECK: st1.b { v0 }[0], [x8]32;33; EXYNOS-LABEL: st1lane0_16b:34; EXYNOS: stur b0, [x0, #1]35 36 %ptr = getelementptr i8, ptr %D, i64 137 %tmp = extractelement <16 x i8> %A, i32 038 store i8 %tmp, ptr %ptr39 ret void40}41 42define void @st1lane0u_16b(<16 x i8> %A, ptr %D) {43; SD-CHECK-LABEL: st1lane0u_16b:44; SD-CHECK: stur b0, [x0, #-1]45;46; GI-CHECK-LABEL: st1lane0u_16b:47; GI-CHECK: sub x8, x0, #148; GI-CHECK: st1.b { v0 }[0], [x8]49;50; EXYNOS-LABEL: st1lane0u_16b:51; EXYNOS: stur b0, [x0, #-1]52 %ptr = getelementptr i8, ptr %D, i64 -153 %tmp = extractelement <16 x i8> %A, i32 054 store i8 %tmp, ptr %ptr55 ret void56}57 58define void @st1lane_ro_16b(<16 x i8> %A, ptr %D, i64 %offset) {59; SD-CHECK-LABEL: st1lane_ro_16b:60; SD-CHECK: mov b0, v0[1]61; SD-CHECK: str b0, [x0, x1]62;63; GI-CHECK-LABEL: st1lane_ro_16b:64; GI-CHECK: add x8, x0, x165; GI-CHECK: st1.b { v0 }[1], [x8]66;67; EXYNOS-LABEL: st1lane_ro_16b:68; EXYNOS: mov b0, v0[1]69; EXYNOS: str b0, [x0, x1]70 %ptr = getelementptr i8, ptr %D, i64 %offset71 %tmp = extractelement <16 x i8> %A, i32 172 store i8 %tmp, ptr %ptr73 ret void74}75 76define void @st1lane0_ro_16b(<16 x i8> %A, ptr %D, i64 %offset) {77; SD-CHECK-LABEL: st1lane0_ro_16b:78; SD-CHECK: str b0, [x0, x1]79;80; GI-CHECK-LABEL: st1lane0_ro_16b:81; GI-CHECK: add x8, x0, x182; GI-CHECK: st1.b { v0 }[0], [x8]83;84; EXYNOS-LABEL: st1lane0_ro_16b:85; EXYNOS: str b0, [x0, x1]86 %ptr = getelementptr i8, ptr %D, i64 %offset87 %tmp = extractelement <16 x i8> %A, i32 088 store i8 %tmp, ptr %ptr89 ret void90}91 92define void @st1lane_8h(<8 x i16> %A, ptr %D) {93; SD-CHECK-LABEL: st1lane_8h:94; SD-CHECK: mov h0, v0[1]95; SD-CHECK: str h0, [x0, #2]96;97; GI-CHECK-LABEL: st1lane_8h:98; GI-CHECK: add x8, x0, #299; GI-CHECK: st1.h { v0 }[1], [x8]100;101; EXYNOS-LABEL: st1lane_8h:102; EXYNOS: mov h0, v0[1]103; EXYNOS: str h0, [x0, #2]104 %ptr = getelementptr i16, ptr %D, i64 1105 %tmp = extractelement <8 x i16> %A, i32 1106 store i16 %tmp, ptr %ptr107 ret void108}109 110define void @st1lane0_8h(<8 x i16> %A, ptr %D) {111; CHECK-LABEL: st1lane0_8h:112; CHECK: str h0, [x0, #2]113 %ptr = getelementptr i16, ptr %D, i64 1114 %tmp = extractelement <8 x i16> %A, i32 0115 store i16 %tmp, ptr %ptr116 ret void117}118 119define void @st1lane0u_8h(<8 x i16> %A, ptr %D) {120; CHECK-LABEL: st1lane0u_8h:121; CHECK: stur h0, [x0, #-2]122 %ptr = getelementptr i16, ptr %D, i64 -1123 %tmp = extractelement <8 x i16> %A, i32 0124 store i16 %tmp, ptr %ptr125 ret void126}127 128define void @st1lane_ro_8h(<8 x i16> %A, ptr %D, i64 %offset) {129; SD-CHECK-LABEL: st1lane_ro_8h:130; SD-CHECK: mov h0, v0[1]131; SD-CHECK: str h0, [x0, x1, lsl #1]132;133; GI-CHECK-LABEL: st1lane_ro_8h:134; GI-CHECK: add x8, x0, x1, lsl #1135; GI-CHECK: st1.h { v0 }[1], [x8]136;137; EXYNOS-LABEL: st1lane_ro_8h:138; EXYNOS: mov h0, v0[1]139; EXYNOS: str h0, [x0, x1, lsl #1]140 %ptr = getelementptr i16, ptr %D, i64 %offset141 %tmp = extractelement <8 x i16> %A, i32 1142 store i16 %tmp, ptr %ptr143 ret void144}145 146define void @st1lane0_ro_8h(<8 x i16> %A, ptr %D, i64 %offset) {147; CHECK-LABEL: st1lane0_ro_8h:148; CHECK: str h0, [x0, x1, lsl #1]149 %ptr = getelementptr i16, ptr %D, i64 %offset150 %tmp = extractelement <8 x i16> %A, i32 0151 store i16 %tmp, ptr %ptr152 ret void153}154 155define void @st1lane_4s(<4 x i32> %A, ptr %D) {156; SD-CHECK-LABEL: st1lane_4s:157; SD-CHECK: mov s0, v0[1]158; SD-CHECK: str s0, [x0, #4]159;160; GI-CHECK-LABEL: st1lane_4s:161; GI-CHECK: add x8, x0, #4162; GI-CHECK: st1.s { v0 }[1], [x8]163;164; EXYNOS-LABEL: st1lane_4s:165; EXYNOS: mov s0, v0[1]166; EXYNOS: str s0, [x0, #4]167 %ptr = getelementptr i32, ptr %D, i64 1168 %tmp = extractelement <4 x i32> %A, i32 1169 store i32 %tmp, ptr %ptr170 ret void171}172 173define void @st1lane0_4s(<4 x i32> %A, ptr %D) {174; CHECK-LABEL: st1lane0_4s:175; CHECK: str s0, [x0, #4]176 %ptr = getelementptr i32, ptr %D, i64 1177 %tmp = extractelement <4 x i32> %A, i32 0178 store i32 %tmp, ptr %ptr179 ret void180}181 182define void @st1lane0u_4s(<4 x i32> %A, ptr %D) {183; CHECK-LABEL: st1lane0u_4s:184; CHECK: stur s0, [x0, #-4]185 %ptr = getelementptr i32, ptr %D, i64 -1186 %tmp = extractelement <4 x i32> %A, i32 0187 store i32 %tmp, ptr %ptr188 ret void189}190 191define void @st1lane_ro_4s(<4 x i32> %A, ptr %D, i64 %offset) {192; SD-CHECK-LABEL: st1lane_ro_4s:193; SD-CHECK: mov s0, v0[1]194; SD-CHECK: str s0, [x0, x1, lsl #2]195;196; GI-CHECK-LABEL: st1lane_ro_4s:197; GI-CHECK: add x8, x0, x1, lsl #2198; GI-CHECK: st1.s { v0 }[1], [x8]199;200; EXYNOS-LABEL: st1lane_ro_4s:201; EXYNOS: mov s0, v0[1]202; EXYNOS: str s0, [x0, x1, lsl #2]203 %ptr = getelementptr i32, ptr %D, i64 %offset204 %tmp = extractelement <4 x i32> %A, i32 1205 store i32 %tmp, ptr %ptr206 ret void207}208 209define void @st1lane0_ro_4s(<4 x i32> %A, ptr %D, i64 %offset) {210; CHECK-LABEL: st1lane0_ro_4s:211; CHECK: str s0, [x0, x1, lsl #2]212 %ptr = getelementptr i32, ptr %D, i64 %offset213 %tmp = extractelement <4 x i32> %A, i32 0214 store i32 %tmp, ptr %ptr215 ret void216}217 218define void @st1lane_4s_float(<4 x float> %A, ptr %D) {219; CHECK-LABEL: st1lane_4s_float:220; CHECK: add x8, x0, #4221; CHECK: st1.s { v0 }[1], [x8]222 %ptr = getelementptr float, ptr %D, i64 1223 %tmp = extractelement <4 x float> %A, i32 1224 store float %tmp, ptr %ptr225 ret void226}227 228define void @st1lane0_4s_float(<4 x float> %A, ptr %D) {229; CHECK-LABEL: st1lane0_4s_float:230; CHECK: str s0, [x0, #4]231 %ptr = getelementptr float, ptr %D, i64 1232 %tmp = extractelement <4 x float> %A, i32 0233 store float %tmp, ptr %ptr234 ret void235}236 237define void @st1lane0u_4s_float(<4 x float> %A, ptr %D) {238; CHECK-LABEL: st1lane0u_4s_float:239; CHECK: stur s0, [x0, #-4]240 %ptr = getelementptr float, ptr %D, i64 -1241 %tmp = extractelement <4 x float> %A, i32 0242 store float %tmp, ptr %ptr243 ret void244}245 246define void @st1lane_ro_4s_float(<4 x float> %A, ptr %D, i64 %offset) {247; CHECK-LABEL: st1lane_ro_4s_float:248; CHECK: add x8, x0, x1, lsl #2249; CHECK: st1.s { v0 }[1], [x8]250 %ptr = getelementptr float, ptr %D, i64 %offset251 %tmp = extractelement <4 x float> %A, i32 1252 store float %tmp, ptr %ptr253 ret void254}255 256define void @st1lane0_ro_4s_float(<4 x float> %A, ptr %D, i64 %offset) {257; CHECK-LABEL: st1lane0_ro_4s_float:258; CHECK: str s0, [x0, x1, lsl #2]259 %ptr = getelementptr float, ptr %D, i64 %offset260 %tmp = extractelement <4 x float> %A, i32 0261 store float %tmp, ptr %ptr262 ret void263}264 265define void @st1lane_2d(<2 x i64> %A, ptr %D) {266; SD-CHECK-LABEL: st1lane_2d:267; SD-CHECK: mov d0, v0[1]268; SD-CHECK: str d0, [x0, #8]269;270; GI-CHECK-LABEL: st1lane_2d:271; GI-CHECK: add x8, x0, #8272; GI-CHECK: st1.d { v0 }[1], [x8]273;274; EXYNOS-LABEL: st1lane_2d:275; EXYNOS: mov d0, v0[1]276; EXYNOS: str d0, [x0, #8]277 %ptr = getelementptr i64, ptr %D, i64 1278 %tmp = extractelement <2 x i64> %A, i32 1279 store i64 %tmp, ptr %ptr280 ret void281}282 283define void @st1lane0_2d(<2 x i64> %A, ptr %D) {284; CHECK-LABEL: st1lane0_2d:285; CHECK: str d0, [x0, #8]286 %ptr = getelementptr i64, ptr %D, i64 1287 %tmp = extractelement <2 x i64> %A, i32 0288 store i64 %tmp, ptr %ptr289 ret void290}291 292define void @st1lane0u_2d(<2 x i64> %A, ptr %D) {293; CHECK-LABEL: st1lane0u_2d:294; CHECK: stur d0, [x0, #-8]295 %ptr = getelementptr i64, ptr %D, i64 -1296 %tmp = extractelement <2 x i64> %A, i32 0297 store i64 %tmp, ptr %ptr298 ret void299}300 301define void @st1lane_ro_2d(<2 x i64> %A, ptr %D, i64 %offset) {302; SD-CHECK-LABEL: st1lane_ro_2d:303; SD-CHECK: mov d0, v0[1]304; SD-CHECK: str d0, [x0, x1, lsl #3]305;306; GI-CHECK-LABEL: st1lane_ro_2d:307; GI-CHECK: add x8, x0, x1, lsl #3308; GI-CHECK: st1.d { v0 }[1], [x8]309;310; EXYNOS-LABEL: st1lane_ro_2d:311; EXYNOS: mov d0, v0[1]312; EXYNOS: str d0, [x0, x1, lsl #3]313 %ptr = getelementptr i64, ptr %D, i64 %offset314 %tmp = extractelement <2 x i64> %A, i32 1315 store i64 %tmp, ptr %ptr316 ret void317}318 319define void @st1lane0_ro_2d(<2 x i64> %A, ptr %D, i64 %offset) {320; CHECK-LABEL: st1lane0_ro_2d:321; CHECK: str d0, [x0, x1, lsl #3]322 %ptr = getelementptr i64, ptr %D, i64 %offset323 %tmp = extractelement <2 x i64> %A, i32 0324 store i64 %tmp, ptr %ptr325 ret void326}327 328define void @st1lane_2d_double(<2 x double> %A, ptr %D) {329; CHECK-LABEL: st1lane_2d_double:330; CHECK: add x8, x0, #8331; CHECK: st1.d { v0 }[1], [x8]332 %ptr = getelementptr double, ptr %D, i64 1333 %tmp = extractelement <2 x double> %A, i32 1334 store double %tmp, ptr %ptr335 ret void336}337 338define void @st1lane0_2d_double(<2 x double> %A, ptr %D) {339; CHECK-LABEL: st1lane0_2d_double:340; CHECK: str d0, [x0, #8]341 %ptr = getelementptr double, ptr %D, i64 1342 %tmp = extractelement <2 x double> %A, i32 0343 store double %tmp, ptr %ptr344 ret void345}346 347define void @st1lane0u_2d_double(<2 x double> %A, ptr %D) {348; CHECK-LABEL: st1lane0u_2d_double:349; CHECK: stur d0, [x0, #-8]350 %ptr = getelementptr double, ptr %D, i64 -1351 %tmp = extractelement <2 x double> %A, i32 0352 store double %tmp, ptr %ptr353 ret void354}355 356define void @st1lane_ro_2d_double(<2 x double> %A, ptr %D, i64 %offset) {357; CHECK-LABEL: st1lane_ro_2d_double:358; CHECK: add x8, x0, x1, lsl #3359; CHECK: st1.d { v0 }[1], [x8]360 %ptr = getelementptr double, ptr %D, i64 %offset361 %tmp = extractelement <2 x double> %A, i32 1362 store double %tmp, ptr %ptr363 ret void364}365 366define void @st1lane0_ro_2d_double(<2 x double> %A, ptr %D, i64 %offset) {367; CHECK-LABEL: st1lane0_ro_2d_double:368; CHECK: str d0, [x0, x1, lsl #3]369 %ptr = getelementptr double, ptr %D, i64 %offset370 %tmp = extractelement <2 x double> %A, i32 0371 store double %tmp, ptr %ptr372 ret void373}374 375define void @st1lane_8b(<8 x i8> %A, ptr %D) {376; SD-CHECK-LABEL: st1lane_8b:377; SD-CHECK: mov b0, v0[1]378; SD-CHECK: stur b0, [x0, #1]379;380; GI-CHECK-LABEL: st1lane_8b:381; GI-CHECK: add x8, x0, #1382; GI-CHECK: st1.b { v0 }[1], [x8]383;384; EXYNOS-LABEL: st1lane_8b:385; EXYNOS: mov b0, v0[1]386; EXYNOS: stur b0, [x0, #1]387 %ptr = getelementptr i8, ptr %D, i64 1388 %tmp = extractelement <8 x i8> %A, i32 1389 store i8 %tmp, ptr %ptr390 ret void391}392 393define void @st1lane_ro_8b(<8 x i8> %A, ptr %D, i64 %offset) {394; SD-CHECK-LABEL: st1lane_ro_8b:395; SD-CHECK: mov b0, v0[1]396; SD-CHECK: str b0, [x0, x1]397;398; GI-CHECK-LABEL: st1lane_ro_8b:399; GI-CHECK: add x8, x0, x1400; GI-CHECK: st1.b { v0 }[1], [x8]401;402; EXYNOS-LABEL: st1lane_ro_8b:403; EXYNOS: mov b0, v0[1]404; EXYNOS: str b0, [x0, x1]405 %ptr = getelementptr i8, ptr %D, i64 %offset406 %tmp = extractelement <8 x i8> %A, i32 1407 store i8 %tmp, ptr %ptr408 ret void409}410 411define void @st1lane0_ro_8b(<8 x i8> %A, ptr %D, i64 %offset) {412; SD-CHECK-LABEL: st1lane0_ro_8b:413; SD-CHECK: str b0, [x0, x1]414;415; GI-CHECK-LABEL: st1lane0_ro_8b:416; GI-CHECK: add x8, x0, x1417; GI-CHECK: st1.b { v0 }[0], [x8]418;419; EXYNOS-LABEL: st1lane0_ro_8b:420; EXYNOS: str b0, [x0, x1]421 %ptr = getelementptr i8, ptr %D, i64 %offset422 %tmp = extractelement <8 x i8> %A, i32 0423 store i8 %tmp, ptr %ptr424 ret void425}426 427define void @st1lane_4h(<4 x i16> %A, ptr %D) {428; SD-CHECK-LABEL: st1lane_4h:429; SD-CHECK: mov h0, v0[1]430; SD-CHECK: str h0, [x0, #2]431;432; GI-CHECK-LABEL: st1lane_4h:433; GI-CHECK: add x8, x0, #2434; GI-CHECK: st1.h { v0 }[1], [x8]435;436; EXYNOS-LABEL: st1lane_4h:437; EXYNOS: mov h0, v0[1]438; EXYNOS: str h0, [x0, #2]439 %ptr = getelementptr i16, ptr %D, i64 1440 %tmp = extractelement <4 x i16> %A, i32 1441 store i16 %tmp, ptr %ptr442 ret void443}444 445define void @st1lane0_4h(<4 x i16> %A, ptr %D) {446; CHECK-LABEL: st1lane0_4h:447; CHECK: str h0, [x0, #2]448 %ptr = getelementptr i16, ptr %D, i64 1449 %tmp = extractelement <4 x i16> %A, i32 0450 store i16 %tmp, ptr %ptr451 ret void452}453 454define void @st1lane0u_4h(<4 x i16> %A, ptr %D) {455; CHECK-LABEL: st1lane0u_4h:456; CHECK: stur h0, [x0, #-2]457 %ptr = getelementptr i16, ptr %D, i64 -1458 %tmp = extractelement <4 x i16> %A, i32 0459 store i16 %tmp, ptr %ptr460 ret void461}462 463define void @st1lane_ro_4h(<4 x i16> %A, ptr %D, i64 %offset) {464; SD-CHECK-LABEL: st1lane_ro_4h:465; SD-CHECK: mov h0, v0[1]466; SD-CHECK: str h0, [x0, x1, lsl #1]467;468; GI-CHECK-LABEL: st1lane_ro_4h:469; GI-CHECK: add x8, x0, x1, lsl #1470; GI-CHECK: st1.h { v0 }[1], [x8]471;472; EXYNOS-LABEL: st1lane_ro_4h:473; EXYNOS: mov h0, v0[1]474; EXYNOS: str h0, [x0, x1, lsl #1]475 %ptr = getelementptr i16, ptr %D, i64 %offset476 %tmp = extractelement <4 x i16> %A, i32 1477 store i16 %tmp, ptr %ptr478 ret void479}480 481define void @st1lane0_ro_4h(<4 x i16> %A, ptr %D, i64 %offset) {482; CHECK-LABEL: st1lane0_ro_4h:483; CHECK: str h0, [x0, x1, lsl #1]484 %ptr = getelementptr i16, ptr %D, i64 %offset485 %tmp = extractelement <4 x i16> %A, i32 0486 store i16 %tmp, ptr %ptr487 ret void488}489 490define void @st1lane_2s(<2 x i32> %A, ptr %D) {491; SD-CHECK-LABEL: st1lane_2s:492; SD-CHECK: mov s0, v0[1]493; SD-CHECK: str s0, [x0, #4]494;495; GI-CHECK-LABEL: st1lane_2s:496; GI-CHECK: add x8, x0, #4497; GI-CHECK: st1.s { v0 }[1], [x8]498;499; EXYNOS-LABEL: st1lane_2s:500; EXYNOS: mov s0, v0[1]501; EXYNOS: str s0, [x0, #4]502 %ptr = getelementptr i32, ptr %D, i64 1503 %tmp = extractelement <2 x i32> %A, i32 1504 store i32 %tmp, ptr %ptr505 ret void506}507 508define void @st1lane0_2s(<2 x i32> %A, ptr %D) {509; CHECK-LABEL: st1lane0_2s:510; CHECK: str s0, [x0, #4]511 %ptr = getelementptr i32, ptr %D, i64 1512 %tmp = extractelement <2 x i32> %A, i32 0513 store i32 %tmp, ptr %ptr514 ret void515}516 517define void @st1lane0u_2s(<2 x i32> %A, ptr %D) {518; CHECK-LABEL: st1lane0u_2s:519; CHECK: stur s0, [x0, #-4]520 %ptr = getelementptr i32, ptr %D, i64 -1521 %tmp = extractelement <2 x i32> %A, i32 0522 store i32 %tmp, ptr %ptr523 ret void524}525 526define void @st1lane_ro_2s(<2 x i32> %A, ptr %D, i64 %offset) {527; SD-CHECK-LABEL: st1lane_ro_2s:528; SD-CHECK: mov s0, v0[1]529; SD-CHECK: str s0, [x0, x1, lsl #2]530;531; GI-CHECK-LABEL: st1lane_ro_2s:532; GI-CHECK: add x8, x0, x1, lsl #2533; GI-CHECK: st1.s { v0 }[1], [x8]534;535; EXYNOS-LABEL: st1lane_ro_2s:536; EXYNOS: mov s0, v0[1]537; EXYNOS: str s0, [x0, x1, lsl #2]538 %ptr = getelementptr i32, ptr %D, i64 %offset539 %tmp = extractelement <2 x i32> %A, i32 1540 store i32 %tmp, ptr %ptr541 ret void542}543 544define void @st1lane0_ro_2s(<2 x i32> %A, ptr %D, i64 %offset) {545; CHECK-LABEL: st1lane0_ro_2s:546; CHECK: str s0, [x0, x1, lsl #2]547 %ptr = getelementptr i32, ptr %D, i64 %offset548 %tmp = extractelement <2 x i32> %A, i32 0549 store i32 %tmp, ptr %ptr550 ret void551}552 553define void @st1lane_2s_float(<2 x float> %A, ptr %D) {554; CHECK-LABEL: st1lane_2s_float:555; CHECK: add x8, x0, #4556; CHECK: st1.s { v0 }[1], [x8]557 %ptr = getelementptr float, ptr %D, i64 1558 %tmp = extractelement <2 x float> %A, i32 1559 store float %tmp, ptr %ptr560 ret void561}562 563define void @st1lane0_2s_float(<2 x float> %A, ptr %D) {564; CHECK-LABEL: st1lane0_2s_float:565; CHECK: str s0, [x0, #4]566 %ptr = getelementptr float, ptr %D, i64 1567 %tmp = extractelement <2 x float> %A, i32 0568 store float %tmp, ptr %ptr569 ret void570}571 572define void @st1lane0u_2s_float(<2 x float> %A, ptr %D) {573; CHECK-LABEL: st1lane0u_2s_float:574; CHECK: stur s0, [x0, #-4]575 %ptr = getelementptr float, ptr %D, i64 -1576 %tmp = extractelement <2 x float> %A, i32 0577 store float %tmp, ptr %ptr578 ret void579}580 581define void @st1lane_ro_2s_float(<2 x float> %A, ptr %D, i64 %offset) {582; CHECK-LABEL: st1lane_ro_2s_float:583; CHECK: add x8, x0, x1, lsl #2584; CHECK: st1.s { v0 }[1], [x8]585 %ptr = getelementptr float, ptr %D, i64 %offset586 %tmp = extractelement <2 x float> %A, i32 1587 store float %tmp, ptr %ptr588 ret void589}590 591define void @st1lane0_ro_2s_float(<2 x float> %A, ptr %D, i64 %offset) {592; CHECK-LABEL: st1lane0_ro_2s_float:593; CHECK: str s0, [x0, x1, lsl #2]594 %ptr = getelementptr float, ptr %D, i64 %offset595 %tmp = extractelement <2 x float> %A, i32 0596 store float %tmp, ptr %ptr597 ret void598}599 600define void @st1lane0_1d(<1 x i64> %A, ptr %D) {601; CHECK-LABEL: st1lane0_1d:602; CHECK: str d0, [x0, #8]603 %ptr = getelementptr i64, ptr %D, i64 1604 %tmp = extractelement <1 x i64> %A, i32 0605 store i64 %tmp, ptr %ptr606 ret void607}608 609define void @st1lane0u_1d(<1 x i64> %A, ptr %D) {610; CHECK-LABEL: st1lane0u_1d:611; CHECK: stur d0, [x0, #-8]612 %ptr = getelementptr i64, ptr %D, i64 -1613 %tmp = extractelement <1 x i64> %A, i32 0614 store i64 %tmp, ptr %ptr615 ret void616}617 618define void @st1lane0_ro_1d(<1 x i64> %A, ptr %D, i64 %offset) {619; CHECK-LABEL: st1lane0_ro_1d:620; CHECK: str d0, [x0, x1, lsl #3]621 %ptr = getelementptr i64, ptr %D, i64 %offset622 %tmp = extractelement <1 x i64> %A, i32 0623 store i64 %tmp, ptr %ptr624 ret void625}626 627define void @st1lane0_1d_double(<1 x double> %A, ptr %D) {628; CHECK-LABEL: st1lane0_1d_double:629; CHECK: str d0, [x0, #8]630 %ptr = getelementptr double, ptr %D, i64 1631 %tmp = extractelement <1 x double> %A, i32 0632 store double %tmp, ptr %ptr633 ret void634}635 636define void @st1lane0u_1d_double(<1 x double> %A, ptr %D) {637; CHECK-LABEL: st1lane0u_1d_double:638; CHECK: stur d0, [x0, #-8]639 %ptr = getelementptr double, ptr %D, i64 -1640 %tmp = extractelement <1 x double> %A, i32 0641 store double %tmp, ptr %ptr642 ret void643}644 645define void @st1lane0_ro_1d_double(<1 x double> %A, ptr %D, i64 %offset) {646; CHECK-LABEL: st1lane0_ro_1d_double:647; CHECK: str d0, [x0, x1, lsl #3]648 %ptr = getelementptr double, ptr %D, i64 %offset649 %tmp = extractelement <1 x double> %A, i32 0650 store double %tmp, ptr %ptr651 ret void652}653 654define void @st2lane_16b(<16 x i8> %A, <16 x i8> %B, ptr %D) {655; CHECK-LABEL: st2lane_16b:656; CHECK: st2.b { v0, v1 }[1], [x0]657 call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> %A, <16 x i8> %B, i64 1, ptr %D)658 ret void659}660 661define void @st2lane_8h(<8 x i16> %A, <8 x i16> %B, ptr %D) {662; CHECK-LABEL: st2lane_8h:663; CHECK: st2.h { v0, v1 }[1], [x0]664 call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> %A, <8 x i16> %B, i64 1, ptr %D)665 ret void666}667 668define void @st2lane_4s(<4 x i32> %A, <4 x i32> %B, ptr %D) {669; CHECK-LABEL: st2lane_4s:670; CHECK: st2.s { v0, v1 }[1], [x0]671 call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> %A, <4 x i32> %B, i64 1, ptr %D)672 ret void673}674 675define void @st2lane_2d(<2 x i64> %A, <2 x i64> %B, ptr %D) {676; CHECK-LABEL: st2lane_2d:677; CHECK: st2.d { v0, v1 }[1], [x0]678 call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> %A, <2 x i64> %B, i64 1, ptr %D)679 ret void680}681 682declare void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8>, <16 x i8>, i64, ptr) nounwind readnone683declare void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16>, <8 x i16>, i64, ptr) nounwind readnone684declare void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32>, <4 x i32>, i64, ptr) nounwind readnone685declare void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64>, <2 x i64>, i64, ptr) nounwind readnone686 687define void @st3lane_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %D) {688; CHECK-LABEL: st3lane_16b:689; CHECK: st3.b { v0, v1, v2 }[1], [x0]690 call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i64 1, ptr %D)691 ret void692}693 694define void @st3lane_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %D) {695; CHECK-LABEL: st3lane_8h:696; CHECK: st3.h { v0, v1, v2 }[1], [x0]697 call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i64 1, ptr %D)698 ret void699}700 701define void @st3lane_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %D) {702; CHECK-LABEL: st3lane_4s:703; CHECK: st3.s { v0, v1, v2 }[1], [x0]704 call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i64 1, ptr %D)705 ret void706}707 708define void @st3lane_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %D) {709; CHECK-LABEL: st3lane_2d:710; CHECK: st3.d { v0, v1, v2 }[1], [x0]711 call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64 1, ptr %D)712 ret void713}714 715declare void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, i64, ptr) nounwind readnone716declare void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, i64, ptr) nounwind readnone717declare void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, i64, ptr) nounwind readnone718declare void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, i64, ptr) nounwind readnone719 720define void @st4lane_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %E) {721; CHECK-LABEL: st4lane_16b:722; CHECK: st4.b { v0, v1, v2, v3 }[1], [x0]723 call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 1, ptr %E)724 ret void725}726 727define void @st4lane_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %E) {728; CHECK-LABEL: st4lane_8h:729; CHECK: st4.h { v0, v1, v2, v3 }[1], [x0]730 call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 1, ptr %E)731 ret void732}733 734define void @st4lane_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %E) {735; CHECK-LABEL: st4lane_4s:736; CHECK: st4.s { v0, v1, v2, v3 }[1], [x0]737 call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 1, ptr %E)738 ret void739}740 741define void @st4lane_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %E) {742; CHECK-LABEL: st4lane_2d:743; CHECK: st4.d { v0, v1, v2, v3 }[1], [x0]744 call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 1, ptr %E)745 ret void746}747 748declare void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i64, ptr) nounwind readnone749declare void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i64, ptr) nounwind readnone750declare void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, ptr) nounwind readnone751declare void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, i64, ptr) nounwind readnone752 753 754define void @st2_8b(<8 x i8> %A, <8 x i8> %B, ptr %P) nounwind {755; SD-CHECK-LABEL: st2_8b:756; SD-CHECK: st2.8b { v0, v1 }, [x0]757;758; GI-CHECK-LABEL: st2_8b:759; GI-CHECK: st2.8b { v0, v1 }, [x0]760;761; EXYNOS-LABEL: st2_8b:762; EXYNOS: zip1.8b v2, v0, v1763; EXYNOS: zip2.8b v0, v0, v1764; EXYNOS: stp d2, d0, [x0]765 call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %A, <8 x i8> %B, ptr %P)766 ret void767}768 769define void @st3_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %P) nounwind {770; CHECK-LABEL: st3_8b:771; CHECK: st3.8b { v0, v1, v2 }, [x0]772 call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %P)773 ret void774}775 776define void @st4_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %P) nounwind {777; SD-CHECK-LABEL: st4_8b:778; SD-CHECK: st4.8b { v0, v1, v2, v3 }, [x0]779;780; GI-CHECK-LABEL: st4_8b:781; GI-CHECK: st4.8b { v0, v1, v2, v3 }, [x0]782;783; EXYNOS-LABEL: st4_8b:784; EXYNOS: zip1.8b v4, v0, v2785; EXYNOS: zip2.8b v0, v0, v2786; EXYNOS: zip1.8b v2, v1, v3787; EXYNOS: zip2.8b v1, v1, v3788; EXYNOS: zip1.8b v3, v4, v2789; EXYNOS: zip2.8b v2, v4, v2790; EXYNOS: stp d3, d2, [x0]791; EXYNOS: zip1.8b v4, v0, v1792; EXYNOS: zip2.8b v0, v0, v1793; EXYNOS: stp d4, d0, [x0, #16]794 call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %P)795 ret void796}797 798declare void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8>, <8 x i8>, ptr) nounwind readonly799declare void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, ptr) nounwind readonly800declare void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, ptr) nounwind readonly801 802define void @st2_16b(<16 x i8> %A, <16 x i8> %B, ptr %P) nounwind {803; SD-CHECK-LABEL: st2_16b:804; SD-CHECK: st2.16b { v0, v1 }, [x0]805;806; GI-CHECK-LABEL: st2_16b:807; GI-CHECK: st2.16b { v0, v1 }, [x0]808;809; EXYNOS-LABEL: st2_16b:810; EXYNOS: zip1.16b v2, v0, v1811; EXYNOS: zip2.16b v0, v0, v1812; EXYNOS: stp q2, q0, [x0]813 call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> %A, <16 x i8> %B, ptr %P)814 ret void815}816 817define void @st3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %P) nounwind {818; CHECK-LABEL: st3_16b:819; CHECK: st3.16b { v0, v1, v2 }, [x0]820 call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %P)821 ret void822}823 824define void @st4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %P) nounwind {825; SD-CHECK-LABEL: st4_16b:826; SD-CHECK: st4.16b { v0, v1, v2, v3 }, [x0]827;828; GI-CHECK-LABEL: st4_16b:829; GI-CHECK: st4.16b { v0, v1, v2, v3 }, [x0]830;831; EXYNOS-LABEL: st4_16b:832; EXYNOS: zip1.16b v4, v0, v2833; EXYNOS: zip2.16b v0, v0, v2834; EXYNOS: zip1.16b v2, v1, v3835; EXYNOS: zip2.16b v1, v1, v3836; EXYNOS: zip1.16b v3, v4, v2837; EXYNOS: zip2.16b v2, v4, v2838; EXYNOS: stp q3, q2, [x0]839; EXYNOS: zip1.16b v4, v0, v1840; EXYNOS: zip2.16b v0, v0, v1841; EXYNOS: stp q4, q0, [x0, #32]842 call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %P)843 ret void844}845 846declare void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8>, <16 x i8>, ptr) nounwind readonly847declare void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, ptr) nounwind readonly848declare void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, ptr) nounwind readonly849 850define void @st2_4h(<4 x i16> %A, <4 x i16> %B, ptr %P) nounwind {851; SD-CHECK-LABEL: st2_4h:852; SD-CHECK: st2.4h { v0, v1 }, [x0]853;854; GI-CHECK-LABEL: st2_4h:855; GI-CHECK: st2.4h { v0, v1 }, [x0]856;857; EXYNOS-LABEL: st2_4h:858; EXYNOS: zip1.4h v2, v0, v1859; EXYNOS: zip2.4h v0, v0, v1860; EXYNOS: stp d2, d0, [x0]861 call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> %A, <4 x i16> %B, ptr %P)862 ret void863}864 865define void @st3_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %P) nounwind {866; CHECK-LABEL: st3_4h:867; CHECK: st3.4h { v0, v1, v2 }, [x0]868 call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %P)869 ret void870}871 872define void @st4_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %P) nounwind {873; SD-CHECK-LABEL: st4_4h:874; SD-CHECK: st4.4h { v0, v1, v2, v3 }, [x0]875;876; GI-CHECK-LABEL: st4_4h:877; GI-CHECK: st4.4h { v0, v1, v2, v3 }, [x0]878;879; EXYNOS-LABEL: st4_4h:880; EXYNOS: zip1.4h v4, v0, v2881; EXYNOS: zip2.4h v0, v0, v2882; EXYNOS: zip1.4h v2, v1, v3883; EXYNOS: zip2.4h v1, v1, v3884; EXYNOS: zip1.4h v3, v4, v2885; EXYNOS: zip2.4h v2, v4, v2886; EXYNOS: stp d3, d2, [x0]887; EXYNOS: zip1.4h v4, v0, v1888; EXYNOS: zip2.4h v0, v0, v1889; EXYNOS: stp d4, d0, [x0, #16]890 call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %P)891 ret void892}893 894declare void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16>, <4 x i16>, ptr) nounwind readonly895declare void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, ptr) nounwind readonly896declare void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, ptr) nounwind readonly897 898define void @st2_8h(<8 x i16> %A, <8 x i16> %B, ptr %P) nounwind {899; SD-CHECK-LABEL: st2_8h:900; SD-CHECK: st2.8h { v0, v1 }, [x0]901;902; GI-CHECK-LABEL: st2_8h:903; GI-CHECK: st2.8h { v0, v1 }, [x0]904;905; EXYNOS-LABEL: st2_8h:906; EXYNOS: zip1.8h v2, v0, v1907; EXYNOS: zip2.8h v0, v0, v1908; EXYNOS: stp q2, q0, [x0]909 call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> %A, <8 x i16> %B, ptr %P)910 ret void911}912 913define void @st3_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %P) nounwind {914; CHECK-LABEL: st3_8h:915; CHECK: st3.8h { v0, v1, v2 }, [x0]916 call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %P)917 ret void918}919 920define void @st4_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %P) nounwind {921; SD-CHECK-LABEL: st4_8h:922; SD-CHECK: st4.8h { v0, v1, v2, v3 }, [x0]923;924; GI-CHECK-LABEL: st4_8h:925; GI-CHECK: st4.8h { v0, v1, v2, v3 }, [x0]926;927; EXYNOS-LABEL: st4_8h:928; EXYNOS: zip1.8h v4, v0, v2929; EXYNOS: zip2.8h v0, v0, v2930; EXYNOS: zip1.8h v2, v1, v3931; EXYNOS: zip2.8h v1, v1, v3932; EXYNOS: zip1.8h v3, v4, v2933; EXYNOS: zip2.8h v2, v4, v2934; EXYNOS: stp q3, q2, [x0]935; EXYNOS: zip1.8h v4, v0, v1936; EXYNOS: zip2.8h v0, v0, v1937; EXYNOS: stp q4, q0, [x0, #32]938 call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %P)939 ret void940}941 942declare void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16>, <8 x i16>, ptr) nounwind readonly943declare void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, ptr) nounwind readonly944declare void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, ptr) nounwind readonly945 946define void @st2_2s(<2 x i32> %A, <2 x i32> %B, ptr %P) nounwind {947; SD-CHECK-LABEL: st2_2s:948; SD-CHECK: st2.2s { v0, v1 }, [x0]949;950; GI-CHECK-LABEL: st2_2s:951; GI-CHECK: st2.2s { v0, v1 }, [x0]952;953; EXYNOS-LABEL: st2_2s:954; EXYNOS: zip1.2s v2, v0, v1955; EXYNOS: zip2.2s v0, v0, v1956; EXYNOS: stp d2, d0, [x0]957 call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> %A, <2 x i32> %B, ptr %P)958 ret void959}960 961define void @st3_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %P) nounwind {962; CHECK-LABEL: st3_2s:963; CHECK: st3.2s { v0, v1, v2 }, [x0]964 call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %P)965 ret void966}967 968define void @st4_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %P) nounwind {969; SD-CHECK-LABEL: st4_2s:970; SD-CHECK: st4.2s { v0, v1, v2, v3 }, [x0]971;972; GI-CHECK-LABEL: st4_2s:973; GI-CHECK: st4.2s { v0, v1, v2, v3 }, [x0]974;975; EXYNOS-LABEL: st4_2s:976; EXYNOS: zip1.2s v4, v0, v2977; EXYNOS: zip2.2s v0, v0, v2978; EXYNOS: zip1.2s v2, v1, v3979; EXYNOS: zip2.2s v1, v1, v3980; EXYNOS: zip1.2s v3, v4, v2981; EXYNOS: zip2.2s v2, v4, v2982; EXYNOS: stp d3, d2, [x0]983; EXYNOS: zip1.2s v4, v0, v1984; EXYNOS: zip2.2s v0, v0, v1985; EXYNOS: stp d4, d0, [x0, #16]986 call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %P)987 ret void988}989 990declare void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32>, <2 x i32>, ptr) nounwind readonly991declare void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, ptr) nounwind readonly992declare void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, ptr) nounwind readonly993 994define void @st2_4s(<4 x i32> %A, <4 x i32> %B, ptr %P) nounwind {995; SD-CHECK-LABEL: st2_4s:996; SD-CHECK: st2.4s { v0, v1 }, [x0]997;998; GI-CHECK-LABEL: st2_4s:999; GI-CHECK: st2.4s { v0, v1 }, [x0]1000;1001; EXYNOS-LABEL: st2_4s:1002; EXYNOS: zip1.4s v2, v0, v11003; EXYNOS: zip2.4s v0, v0, v11004; EXYNOS: stp q2, q0, [x0]1005 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %A, <4 x i32> %B, ptr %P)1006 ret void1007}1008 1009define void @st3_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %P) nounwind {1010; CHECK-LABEL: st3_4s:1011; CHECK: st3.4s { v0, v1, v2 }, [x0]1012 call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %P)1013 ret void1014}1015 1016define void @st4_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %P) nounwind {1017; SD-CHECK-LABEL: st4_4s:1018; SD-CHECK: st4.4s { v0, v1, v2, v3 }, [x0]1019;1020; GI-CHECK-LABEL: st4_4s:1021; GI-CHECK: st4.4s { v0, v1, v2, v3 }, [x0]1022;1023; EXYNOS-LABEL: st4_4s:1024; EXYNOS: zip1.4s v4, v0, v21025; EXYNOS: zip2.4s v0, v0, v21026; EXYNOS: zip1.4s v2, v1, v31027; EXYNOS: zip2.4s v1, v1, v31028; EXYNOS: zip1.4s v3, v4, v21029; EXYNOS: zip2.4s v2, v4, v21030; EXYNOS: stp q3, q2, [x0]1031; EXYNOS: zip1.4s v4, v0, v11032; EXYNOS: zip2.4s v0, v0, v11033; EXYNOS: stp q4, q0, [x0, #32]1034 call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %P)1035 ret void1036}1037 1038declare void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32>, <4 x i32>, ptr) nounwind readonly1039declare void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, ptr) nounwind readonly1040declare void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, ptr) nounwind readonly1041 1042; If there's only one element, st2/3/4 don't make much sense, stick to st1.1043define void @st2_1d(<1 x i64> %A, <1 x i64> %B, ptr %P) nounwind {1044; CHECK-LABEL: st2_1d:1045; CHECK: st1.1d { v0, v1 }, [x0]1046 call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> %A, <1 x i64> %B, ptr %P)1047 ret void1048}1049 1050define void @st3_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %P) nounwind {1051; CHECK-LABEL: st3_1d:1052; CHECK: st1.1d { v0, v1, v2 }, [x0]1053 call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %P)1054 ret void1055}1056 1057define void @st4_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %P) nounwind {1058; CHECK-LABEL: st4_1d:1059; CHECK: st1.1d { v0, v1, v2, v3 }, [x0]1060 call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %P)1061 ret void1062}1063 1064declare void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64>, <1 x i64>, ptr) nounwind readonly1065declare void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, ptr) nounwind readonly1066declare void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, ptr) nounwind readonly1067 1068define void @st2_2d(<2 x i64> %A, <2 x i64> %B, ptr %P) nounwind {1069; SD-CHECK-LABEL: st2_2d:1070; SD-CHECK: st2.2d { v0, v1 }, [x0]1071;1072; GI-CHECK-LABEL: st2_2d:1073; GI-CHECK: st2.2d { v0, v1 }, [x0]1074;1075; EXYNOS-LABEL: st2_2d:1076; EXYNOS: zip1.2d v2, v0, v11077; EXYNOS: zip2.2d v0, v0, v11078; EXYNOS: stp q2, q0, [x0]1079 call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> %A, <2 x i64> %B, ptr %P)1080 ret void1081}1082 1083define void @st3_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %P) nounwind {1084; CHECK-LABEL: st3_2d:1085; CHECK: st3.2d { v0, v1, v2 }, [x0]1086 call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %P)1087 ret void1088}1089 1090define void @st4_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %P) nounwind {1091; SD-CHECK-LABEL: st4_2d:1092; SD-CHECK: st4.2d { v0, v1, v2, v3 }, [x0]1093;1094; GI-CHECK-LABEL: st4_2d:1095; GI-CHECK: st4.2d { v0, v1, v2, v3 }, [x0]1096;1097; EXYNOS-LABEL: st4_2d:1098; EXYNOS: zip1.2d v4, v0, v21099; EXYNOS: zip2.2d v0, v0, v21100; EXYNOS: zip1.2d v2, v1, v31101; EXYNOS: zip2.2d v1, v1, v31102; EXYNOS: zip1.2d v3, v4, v21103; EXYNOS: zip2.2d v2, v4, v21104; EXYNOS: stp q3, q2, [x0]1105; EXYNOS: zip1.2d v4, v0, v11106; EXYNOS: zip2.2d v0, v0, v11107; EXYNOS: stp q4, q0, [x0, #32]1108 call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %P)1109 ret void1110}1111 1112declare void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64>, <2 x i64>, ptr) nounwind readonly1113declare void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, ptr) nounwind readonly1114declare void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, ptr) nounwind readonly1115 1116declare void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8>, <8 x i8>, ptr) nounwind readonly1117declare void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16>, <4 x i16>, ptr) nounwind readonly1118declare void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32>, <2 x i32>, ptr) nounwind readonly1119declare void @llvm.aarch64.neon.st1x2.v2f32.p0(<2 x float>, <2 x float>, ptr) nounwind readonly1120declare void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64>, <1 x i64>, ptr) nounwind readonly1121declare void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double>, <1 x double>, ptr) nounwind readonly1122 1123define void @st1_x2_v8i8(<8 x i8> %A, <8 x i8> %B, ptr %addr) {1124; CHECK-LABEL: st1_x2_v8i8:1125; CHECK: st1.8b { v0, v1 }, [x0]1126 call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> %A, <8 x i8> %B, ptr %addr)1127 ret void1128}1129 1130define void @st1_x2_v4i16(<4 x i16> %A, <4 x i16> %B, ptr %addr) {1131; CHECK-LABEL: st1_x2_v4i16:1132; CHECK: st1.4h { v0, v1 }, [x0]1133 call void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16> %A, <4 x i16> %B, ptr %addr)1134 ret void1135}1136 1137define void @st1_x2_v2i32(<2 x i32> %A, <2 x i32> %B, ptr %addr) {1138; CHECK-LABEL: st1_x2_v2i32:1139; CHECK: st1.2s { v0, v1 }, [x0]1140 call void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32> %A, <2 x i32> %B, ptr %addr)1141 ret void1142}1143 1144define void @st1_x2_v2f32(<2 x float> %A, <2 x float> %B, ptr %addr) {1145; CHECK-LABEL: st1_x2_v2f32:1146; CHECK: st1.2s { v0, v1 }, [x0]1147 call void @llvm.aarch64.neon.st1x2.v2f32.p0(<2 x float> %A, <2 x float> %B, ptr %addr)1148 ret void1149}1150 1151define void @st1_x2_v1i64(<1 x i64> %A, <1 x i64> %B, ptr %addr) {1152; CHECK-LABEL: st1_x2_v1i64:1153; CHECK: st1.1d { v0, v1 }, [x0]1154 call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> %A, <1 x i64> %B, ptr %addr)1155 ret void1156}1157 1158define void @st1_x2_v1f64(<1 x double> %A, <1 x double> %B, ptr %addr) {1159; CHECK-LABEL: st1_x2_v1f64:1160; CHECK: st1.1d { v0, v1 }, [x0]1161 call void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double> %A, <1 x double> %B, ptr %addr)1162 ret void1163}1164 1165declare void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8>, <16 x i8>, ptr) nounwind readonly1166declare void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16>, <8 x i16>, ptr) nounwind readonly1167declare void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32>, <4 x i32>, ptr) nounwind readonly1168declare void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float>, <4 x float>, ptr) nounwind readonly1169declare void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64>, <2 x i64>, ptr) nounwind readonly1170declare void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double>, <2 x double>, ptr) nounwind readonly1171 1172define void @st1_x2_v16i8(<16 x i8> %A, <16 x i8> %B, ptr %addr) {1173; CHECK-LABEL: st1_x2_v16i8:1174; CHECK: st1.16b { v0, v1 }, [x0]1175 call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> %A, <16 x i8> %B, ptr %addr)1176 ret void1177}1178 1179define void @st1_x2_v8i16(<8 x i16> %A, <8 x i16> %B, ptr %addr) {1180; CHECK-LABEL: st1_x2_v8i16:1181; CHECK: st1.8h { v0, v1 }, [x0]1182 call void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16> %A, <8 x i16> %B, ptr %addr)1183 ret void1184}1185 1186define void @st1_x2_v4i32(<4 x i32> %A, <4 x i32> %B, ptr %addr) {1187; CHECK-LABEL: st1_x2_v4i32:1188; CHECK: st1.4s { v0, v1 }, [x0]1189 call void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32> %A, <4 x i32> %B, ptr %addr)1190 ret void1191}1192 1193define void @st1_x2_v4f32(<4 x float> %A, <4 x float> %B, ptr %addr) {1194; CHECK-LABEL: st1_x2_v4f32:1195; CHECK: st1.4s { v0, v1 }, [x0]1196 call void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float> %A, <4 x float> %B, ptr %addr)1197 ret void1198}1199 1200define void @st1_x2_v2i64(<2 x i64> %A, <2 x i64> %B, ptr %addr) {1201; CHECK-LABEL: st1_x2_v2i64:1202; CHECK: st1.2d { v0, v1 }, [x0]1203 call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> %A, <2 x i64> %B, ptr %addr)1204 ret void1205}1206 1207define void @st1_x2_v2f64(<2 x double> %A, <2 x double> %B, ptr %addr) {1208; CHECK-LABEL: st1_x2_v2f64:1209; CHECK: st1.2d { v0, v1 }, [x0]1210 call void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double> %A, <2 x double> %B, ptr %addr)1211 ret void1212}1213 1214declare void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, ptr) nounwind readonly1215declare void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, ptr) nounwind readonly1216declare void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, ptr) nounwind readonly1217declare void @llvm.aarch64.neon.st1x3.v2f32.p0(<2 x float>, <2 x float>, <2 x float>, ptr) nounwind readonly1218declare void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, ptr) nounwind readonly1219declare void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double>, <1 x double>, <1 x double>, ptr) nounwind readonly1220 1221define void @st1_x3_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %addr) {1222; CHECK-LABEL: st1_x3_v8i8:1223; CHECK: st1.8b { v0, v1, v2 }, [x0]1224 call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %addr)1225 ret void1226}1227 1228define void @st1_x3_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %addr) {1229; CHECK-LABEL: st1_x3_v4i16:1230; CHECK: st1.4h { v0, v1, v2 }, [x0]1231 call void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %addr)1232 ret void1233}1234 1235define void @st1_x3_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %addr) {1236; CHECK-LABEL: st1_x3_v2i32:1237; CHECK: st1.2s { v0, v1, v2 }, [x0]1238 call void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %addr)1239 ret void1240}1241 1242define void @st1_x3_v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, ptr %addr) {1243; CHECK-LABEL: st1_x3_v2f32:1244; CHECK: st1.2s { v0, v1, v2 }, [x0]1245 call void @llvm.aarch64.neon.st1x3.v2f32.p0(<2 x float> %A, <2 x float> %B, <2 x float> %C, ptr %addr)1246 ret void1247}1248 1249define void @st1_x3_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %addr) {1250; CHECK-LABEL: st1_x3_v1i64:1251; CHECK: st1.1d { v0, v1, v2 }, [x0]1252 call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %addr)1253 ret void1254}1255 1256define void @st1_x3_v1f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, ptr %addr) {1257; CHECK-LABEL: st1_x3_v1f64:1258; CHECK: st1.1d { v0, v1, v2 }, [x0]1259 call void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double> %A, <1 x double> %B, <1 x double> %C, ptr %addr)1260 ret void1261}1262 1263declare void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, ptr) nounwind readonly1264declare void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, ptr) nounwind readonly1265declare void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, ptr) nounwind readonly1266declare void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, ptr) nounwind readonly1267declare void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, ptr) nounwind readonly1268declare void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double>, <2 x double>, <2 x double>, ptr) nounwind readonly1269 1270define void @st1_x3_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %addr) {1271; CHECK-LABEL: st1_x3_v16i8:1272; CHECK: st1.16b { v0, v1, v2 }, [x0]1273 call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %addr)1274 ret void1275}1276 1277define void @st1_x3_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %addr) {1278; CHECK-LABEL: st1_x3_v8i16:1279; CHECK: st1.8h { v0, v1, v2 }, [x0]1280 call void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %addr)1281 ret void1282}1283 1284define void @st1_x3_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %addr) {1285; CHECK-LABEL: st1_x3_v4i32:1286; CHECK: st1.4s { v0, v1, v2 }, [x0]1287 call void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %addr)1288 ret void1289}1290 1291define void @st1_x3_v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, ptr %addr) {1292; CHECK-LABEL: st1_x3_v4f32:1293; CHECK: st1.4s { v0, v1, v2 }, [x0]1294 call void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float> %A, <4 x float> %B, <4 x float> %C, ptr %addr)1295 ret void1296}1297 1298define void @st1_x3_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %addr) {1299; CHECK-LABEL: st1_x3_v2i64:1300; CHECK: st1.2d { v0, v1, v2 }, [x0]1301 call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %addr)1302 ret void1303}1304 1305define void @st1_x3_v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, ptr %addr) {1306; CHECK-LABEL: st1_x3_v2f64:1307; CHECK: st1.2d { v0, v1, v2 }, [x0]1308 call void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double> %A, <2 x double> %B, <2 x double> %C, ptr %addr)1309 ret void1310}1311 1312 1313declare void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, ptr) nounwind readonly1314declare void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, ptr) nounwind readonly1315declare void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, ptr) nounwind readonly1316declare void @llvm.aarch64.neon.st1x4.v2f32.p0(<2 x float>, <2 x float>, <2 x float>, <2 x float>, ptr) nounwind readonly1317declare void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, ptr) nounwind readonly1318declare void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double>, <1 x double>, <1 x double>, <1 x double>, ptr) nounwind readonly1319 1320define void @st1_x4_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %addr) {1321; CHECK-LABEL: st1_x4_v8i8:1322; CHECK: st1.8b { v0, v1, v2, v3 }, [x0]1323 call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %addr)1324 ret void1325}1326 1327define void @st1_x4_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %addr) {1328; CHECK-LABEL: st1_x4_v4i16:1329; CHECK: st1.4h { v0, v1, v2, v3 }, [x0]1330 call void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %addr)1331 ret void1332}1333 1334define void @st1_x4_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %addr) {1335; CHECK-LABEL: st1_x4_v2i32:1336; CHECK: st1.2s { v0, v1, v2, v3 }, [x0]1337 call void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %addr)1338 ret void1339}1340 1341define void @st1_x4_v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %addr) {1342; CHECK-LABEL: st1_x4_v2f32:1343; CHECK: st1.2s { v0, v1, v2, v3 }, [x0]1344 call void @llvm.aarch64.neon.st1x4.v2f32.p0(<2 x float> %A, <2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %addr)1345 ret void1346}1347 1348define void @st1_x4_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %addr) {1349; CHECK-LABEL: st1_x4_v1i64:1350; CHECK: st1.1d { v0, v1, v2, v3 }, [x0]1351 call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %addr)1352 ret void1353}1354 1355define void @st1_x4_v1f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %addr) {1356; CHECK-LABEL: st1_x4_v1f64:1357; CHECK: st1.1d { v0, v1, v2, v3 }, [x0]1358 call void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double> %A, <1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %addr)1359 ret void1360}1361 1362declare void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, ptr) nounwind readonly1363declare void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, ptr) nounwind readonly1364declare void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, ptr) nounwind readonly1365declare void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, <4 x float>, ptr) nounwind readonly1366declare void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, ptr) nounwind readonly1367declare void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double>, <2 x double>, <2 x double>, <2 x double>, ptr) nounwind readonly1368 1369define void @st1_x4_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %addr) {1370; CHECK-LABEL: st1_x4_v16i8:1371; CHECK: st1.16b { v0, v1, v2, v3 }, [x0]1372 call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %addr)1373 ret void1374}1375 1376define void @st1_x4_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %addr) {1377; CHECK-LABEL: st1_x4_v8i16:1378; CHECK: st1.8h { v0, v1, v2, v3 }, [x0]1379 call void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %addr)1380 ret void1381}1382 1383define void @st1_x4_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %addr) {1384; CHECK-LABEL: st1_x4_v4i32:1385; CHECK: st1.4s { v0, v1, v2, v3 }, [x0]1386 call void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %addr)1387 ret void1388}1389 1390define void @st1_x4_v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %addr) {1391; CHECK-LABEL: st1_x4_v4f32:1392; CHECK: st1.4s { v0, v1, v2, v3 }, [x0]1393 call void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float> %A, <4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %addr)1394 ret void1395}1396 1397define void @st1_x4_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %addr) {1398; CHECK-LABEL: st1_x4_v2i64:1399; CHECK: st1.2d { v0, v1, v2, v3 }, [x0]1400 call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %addr)1401 ret void1402}1403 1404define void @st1_x4_v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %addr) {1405; CHECK-LABEL: st1_x4_v2f64:1406; CHECK: st1.2d { v0, v1, v2, v3 }, [x0]1407 call void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double> %A, <2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %addr)1408 ret void1409}1410