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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECKLE3; RUN: llc < %s -mtriple=aarch64_be | FileCheck %s --check-prefixes=CHECKBE4 5define <8 x i8> @vtrni8(ptr %A, ptr %B) nounwind {6; CHECKLE-LABEL: vtrni8:7; CHECKLE: // %bb.0:8; CHECKLE-NEXT: ldr d0, [x0]9; CHECKLE-NEXT: ldr d1, [x1]10; CHECKLE-NEXT: trn1 v2.8b, v0.8b, v1.8b11; CHECKLE-NEXT: trn2 v0.8b, v0.8b, v1.8b12; CHECKLE-NEXT: add v0.8b, v2.8b, v0.8b13; CHECKLE-NEXT: ret14;15; CHECKBE-LABEL: vtrni8:16; CHECKBE: // %bb.0:17; CHECKBE-NEXT: ld1 { v0.8b }, [x0]18; CHECKBE-NEXT: ld1 { v1.8b }, [x1]19; CHECKBE-NEXT: trn1 v2.8b, v0.8b, v1.8b20; CHECKBE-NEXT: trn2 v0.8b, v0.8b, v1.8b21; CHECKBE-NEXT: add v0.8b, v2.8b, v0.8b22; CHECKBE-NEXT: rev64 v0.8b, v0.8b23; CHECKBE-NEXT: ret24 %tmp1 = load <8 x i8>, ptr %A25 %tmp2 = load <8 x i8>, ptr %B26 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>27 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>28 %tmp5 = add <8 x i8> %tmp3, %tmp429 ret <8 x i8> %tmp530}31 32define <4 x i16> @vtrni16(ptr %A, ptr %B) nounwind {33; CHECKLE-LABEL: vtrni16:34; CHECKLE: // %bb.0:35; CHECKLE-NEXT: ldr d0, [x0]36; CHECKLE-NEXT: ldr d1, [x1]37; CHECKLE-NEXT: trn1 v2.4h, v0.4h, v1.4h38; CHECKLE-NEXT: trn2 v0.4h, v0.4h, v1.4h39; CHECKLE-NEXT: add v0.4h, v2.4h, v0.4h40; CHECKLE-NEXT: ret41;42; CHECKBE-LABEL: vtrni16:43; CHECKBE: // %bb.0:44; CHECKBE-NEXT: ld1 { v0.4h }, [x0]45; CHECKBE-NEXT: ld1 { v1.4h }, [x1]46; CHECKBE-NEXT: trn1 v2.4h, v0.4h, v1.4h47; CHECKBE-NEXT: trn2 v0.4h, v0.4h, v1.4h48; CHECKBE-NEXT: add v0.4h, v2.4h, v0.4h49; CHECKBE-NEXT: rev64 v0.4h, v0.4h50; CHECKBE-NEXT: ret51 %tmp1 = load <4 x i16>, ptr %A52 %tmp2 = load <4 x i16>, ptr %B53 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>54 %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>55 %tmp5 = add <4 x i16> %tmp3, %tmp456 ret <4 x i16> %tmp557}58 59define <8 x i8> @vtrni16_viabitcast(ptr %A, ptr %B) nounwind {60; CHECKLE-LABEL: vtrni16_viabitcast:61; CHECKLE: // %bb.0:62; CHECKLE-NEXT: ldr d0, [x0]63; CHECKLE-NEXT: ldr d1, [x1]64; CHECKLE-NEXT: trn1 v0.4h, v0.4h, v1.4h65; CHECKLE-NEXT: ret66;67; CHECKBE-LABEL: vtrni16_viabitcast:68; CHECKBE: // %bb.0:69; CHECKBE-NEXT: ld1 { v0.4h }, [x0]70; CHECKBE-NEXT: ld1 { v1.4h }, [x1]71; CHECKBE-NEXT: trn1 v0.4h, v0.4h, v1.4h72; CHECKBE-NEXT: rev64 v0.4h, v0.4h73; CHECKBE-NEXT: ret74 %l1 = load <4 x i16>, ptr %A75 %l2 = load <4 x i16>, ptr %B76 %b1 = bitcast <4 x i16> %l1 to <8 x i8>77 %b2 = bitcast <4 x i16> %l2 to <8 x i8>78 %tmp3 = shufflevector <8 x i8> %b1, <8 x i8> %b2, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 12, i32 13>79 ret <8 x i8> %tmp380}81 82; 2xi32 TRN is redundant with ZIP83define <2 x i32> @vtrni32(ptr %A, ptr %B) nounwind {84; CHECKLE-LABEL: vtrni32:85; CHECKLE: // %bb.0:86; CHECKLE-NEXT: ldr d0, [x0]87; CHECKLE-NEXT: ldr d1, [x1]88; CHECKLE-NEXT: zip1 v2.2s, v0.2s, v1.2s89; CHECKLE-NEXT: zip2 v0.2s, v0.2s, v1.2s90; CHECKLE-NEXT: add v0.2s, v2.2s, v0.2s91; CHECKLE-NEXT: ret92;93; CHECKBE-LABEL: vtrni32:94; CHECKBE: // %bb.0:95; CHECKBE-NEXT: ld1 { v0.2s }, [x0]96; CHECKBE-NEXT: ld1 { v1.2s }, [x1]97; CHECKBE-NEXT: zip1 v2.2s, v0.2s, v1.2s98; CHECKBE-NEXT: zip2 v0.2s, v0.2s, v1.2s99; CHECKBE-NEXT: add v0.2s, v2.2s, v0.2s100; CHECKBE-NEXT: rev64 v0.2s, v0.2s101; CHECKBE-NEXT: ret102 %tmp1 = load <2 x i32>, ptr %A103 %tmp2 = load <2 x i32>, ptr %B104 %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>105 %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>106 %tmp5 = add <2 x i32> %tmp3, %tmp4107 ret <2 x i32> %tmp5108}109 110define <2 x float> @vtrnf(ptr %A, ptr %B) nounwind {111; CHECKLE-LABEL: vtrnf:112; CHECKLE: // %bb.0:113; CHECKLE-NEXT: ldr d0, [x0]114; CHECKLE-NEXT: ldr d1, [x1]115; CHECKLE-NEXT: zip1 v2.2s, v0.2s, v1.2s116; CHECKLE-NEXT: zip2 v0.2s, v0.2s, v1.2s117; CHECKLE-NEXT: fadd v0.2s, v2.2s, v0.2s118; CHECKLE-NEXT: ret119;120; CHECKBE-LABEL: vtrnf:121; CHECKBE: // %bb.0:122; CHECKBE-NEXT: ld1 { v0.2s }, [x0]123; CHECKBE-NEXT: ld1 { v1.2s }, [x1]124; CHECKBE-NEXT: zip1 v2.2s, v0.2s, v1.2s125; CHECKBE-NEXT: zip2 v0.2s, v0.2s, v1.2s126; CHECKBE-NEXT: fadd v0.2s, v2.2s, v0.2s127; CHECKBE-NEXT: rev64 v0.2s, v0.2s128; CHECKBE-NEXT: ret129 %tmp1 = load <2 x float>, ptr %A130 %tmp2 = load <2 x float>, ptr %B131 %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>132 %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>133 %tmp5 = fadd <2 x float> %tmp3, %tmp4134 ret <2 x float> %tmp5135}136 137define <16 x i8> @vtrnQi8(ptr %A, ptr %B) nounwind {138; CHECKLE-LABEL: vtrnQi8:139; CHECKLE: // %bb.0:140; CHECKLE-NEXT: ldr q0, [x0]141; CHECKLE-NEXT: ldr q1, [x1]142; CHECKLE-NEXT: trn1 v2.16b, v0.16b, v1.16b143; CHECKLE-NEXT: trn2 v0.16b, v0.16b, v1.16b144; CHECKLE-NEXT: add v0.16b, v2.16b, v0.16b145; CHECKLE-NEXT: ret146;147; CHECKBE-LABEL: vtrnQi8:148; CHECKBE: // %bb.0:149; CHECKBE-NEXT: ld1 { v0.16b }, [x0]150; CHECKBE-NEXT: ld1 { v1.16b }, [x1]151; CHECKBE-NEXT: trn1 v2.16b, v0.16b, v1.16b152; CHECKBE-NEXT: trn2 v0.16b, v0.16b, v1.16b153; CHECKBE-NEXT: add v0.16b, v2.16b, v0.16b154; CHECKBE-NEXT: rev64 v0.16b, v0.16b155; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8156; CHECKBE-NEXT: ret157 %tmp1 = load <16 x i8>, ptr %A158 %tmp2 = load <16 x i8>, ptr %B159 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>160 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>161 %tmp5 = add <16 x i8> %tmp3, %tmp4162 ret <16 x i8> %tmp5163}164 165define <8 x i16> @vtrnQi16(ptr %A, ptr %B) nounwind {166; CHECKLE-LABEL: vtrnQi16:167; CHECKLE: // %bb.0:168; CHECKLE-NEXT: ldr q0, [x0]169; CHECKLE-NEXT: ldr q1, [x1]170; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h171; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h172; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h173; CHECKLE-NEXT: ret174;175; CHECKBE-LABEL: vtrnQi16:176; CHECKBE: // %bb.0:177; CHECKBE-NEXT: ld1 { v0.8h }, [x0]178; CHECKBE-NEXT: ld1 { v1.8h }, [x1]179; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h180; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h181; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h182; CHECKBE-NEXT: rev64 v0.8h, v0.8h183; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8184; CHECKBE-NEXT: ret185 %tmp1 = load <8 x i16>, ptr %A186 %tmp2 = load <8 x i16>, ptr %B187 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>188 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>189 %tmp5 = add <8 x i16> %tmp3, %tmp4190 ret <8 x i16> %tmp5191}192 193define <4 x i32> @vtrnQi32(ptr %A, ptr %B) nounwind {194; CHECKLE-LABEL: vtrnQi32:195; CHECKLE: // %bb.0:196; CHECKLE-NEXT: ldr q0, [x0]197; CHECKLE-NEXT: ldr q1, [x1]198; CHECKLE-NEXT: trn1 v2.4s, v0.4s, v1.4s199; CHECKLE-NEXT: trn2 v0.4s, v0.4s, v1.4s200; CHECKLE-NEXT: add v0.4s, v2.4s, v0.4s201; CHECKLE-NEXT: ret202;203; CHECKBE-LABEL: vtrnQi32:204; CHECKBE: // %bb.0:205; CHECKBE-NEXT: ld1 { v0.4s }, [x0]206; CHECKBE-NEXT: ld1 { v1.4s }, [x1]207; CHECKBE-NEXT: trn1 v2.4s, v0.4s, v1.4s208; CHECKBE-NEXT: trn2 v0.4s, v0.4s, v1.4s209; CHECKBE-NEXT: add v0.4s, v2.4s, v0.4s210; CHECKBE-NEXT: rev64 v0.4s, v0.4s211; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8212; CHECKBE-NEXT: ret213 %tmp1 = load <4 x i32>, ptr %A214 %tmp2 = load <4 x i32>, ptr %B215 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>216 %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>217 %tmp5 = add <4 x i32> %tmp3, %tmp4218 ret <4 x i32> %tmp5219}220 221define <4 x float> @vtrnQf(ptr %A, ptr %B) nounwind {222; CHECKLE-LABEL: vtrnQf:223; CHECKLE: // %bb.0:224; CHECKLE-NEXT: ldr q0, [x0]225; CHECKLE-NEXT: ldr q1, [x1]226; CHECKLE-NEXT: trn1 v2.4s, v0.4s, v1.4s227; CHECKLE-NEXT: trn2 v0.4s, v0.4s, v1.4s228; CHECKLE-NEXT: fadd v0.4s, v2.4s, v0.4s229; CHECKLE-NEXT: ret230;231; CHECKBE-LABEL: vtrnQf:232; CHECKBE: // %bb.0:233; CHECKBE-NEXT: ld1 { v0.4s }, [x0]234; CHECKBE-NEXT: ld1 { v1.4s }, [x1]235; CHECKBE-NEXT: trn1 v2.4s, v0.4s, v1.4s236; CHECKBE-NEXT: trn2 v0.4s, v0.4s, v1.4s237; CHECKBE-NEXT: fadd v0.4s, v2.4s, v0.4s238; CHECKBE-NEXT: rev64 v0.4s, v0.4s239; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8240; CHECKBE-NEXT: ret241 %tmp1 = load <4 x float>, ptr %A242 %tmp2 = load <4 x float>, ptr %B243 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>244 %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>245 %tmp5 = fadd <4 x float> %tmp3, %tmp4246 ret <4 x float> %tmp5247}248 249; Undef shuffle indices (even at the start of the shuffle mask) should not prevent matching to VTRN:250 251define <8 x i8> @vtrni8_undef(ptr %A, ptr %B) nounwind {252; CHECKLE-LABEL: vtrni8_undef:253; CHECKLE: // %bb.0:254; CHECKLE-NEXT: ldr d0, [x0]255; CHECKLE-NEXT: ldr d1, [x1]256; CHECKLE-NEXT: trn1 v2.8b, v0.8b, v1.8b257; CHECKLE-NEXT: trn2 v0.8b, v0.8b, v1.8b258; CHECKLE-NEXT: add v0.8b, v2.8b, v0.8b259; CHECKLE-NEXT: ret260;261; CHECKBE-LABEL: vtrni8_undef:262; CHECKBE: // %bb.0:263; CHECKBE-NEXT: ld1 { v0.8b }, [x0]264; CHECKBE-NEXT: ld1 { v1.8b }, [x1]265; CHECKBE-NEXT: trn1 v2.8b, v0.8b, v1.8b266; CHECKBE-NEXT: trn2 v0.8b, v0.8b, v1.8b267; CHECKBE-NEXT: add v0.8b, v2.8b, v0.8b268; CHECKBE-NEXT: rev64 v0.8b, v0.8b269; CHECKBE-NEXT: ret270 %tmp1 = load <8 x i8>, ptr %A271 %tmp2 = load <8 x i8>, ptr %B272 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>273 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>274 %tmp5 = add <8 x i8> %tmp3, %tmp4275 ret <8 x i8> %tmp5276}277 278define <8 x i16> @vtrnQi16_undef(ptr %A, ptr %B) nounwind {279; CHECKLE-LABEL: vtrnQi16_undef:280; CHECKLE: // %bb.0:281; CHECKLE-NEXT: ldr q0, [x0]282; CHECKLE-NEXT: ldr q1, [x1]283; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h284; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h285; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h286; CHECKLE-NEXT: ret287;288; CHECKBE-LABEL: vtrnQi16_undef:289; CHECKBE: // %bb.0:290; CHECKBE-NEXT: ld1 { v0.8h }, [x0]291; CHECKBE-NEXT: ld1 { v1.8h }, [x1]292; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h293; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h294; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h295; CHECKBE-NEXT: rev64 v0.8h, v0.8h296; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8297; CHECKBE-NEXT: ret298 %tmp1 = load <8 x i16>, ptr %A299 %tmp2 = load <8 x i16>, ptr %B300 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>301 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>302 %tmp5 = add <8 x i16> %tmp3, %tmp4303 ret <8 x i16> %tmp5304}305 306define <8 x i16> @vtrnQi16_undef_01(ptr %A, ptr %B) nounwind {307; CHECKLE-LABEL: vtrnQi16_undef_01:308; CHECKLE: // %bb.0:309; CHECKLE-NEXT: ldr q0, [x0]310; CHECKLE-NEXT: ldr q1, [x1]311; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h312; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h313; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h314; CHECKLE-NEXT: ret315;316; CHECKBE-LABEL: vtrnQi16_undef_01:317; CHECKBE: // %bb.0:318; CHECKBE-NEXT: ld1 { v0.8h }, [x0]319; CHECKBE-NEXT: ld1 { v1.8h }, [x1]320; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h321; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h322; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h323; CHECKBE-NEXT: rev64 v0.8h, v0.8h324; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8325; CHECKBE-NEXT: ret326 %tmp1 = load <8 x i16>, ptr %A327 %tmp2 = load <8 x i16>, ptr %B328 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 poison, i32 2, i32 poison, i32 4, i32 12, i32 6, i32 14>329 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 poison, i32 3, i32 11, i32 poison, i32 13, i32 poison, i32 poison>330 %tmp5 = add <8 x i16> %tmp3, %tmp4331 ret <8 x i16> %tmp5332}333 334define <8 x i16> @vtrnQi16_undef_0(ptr %A, ptr %B) nounwind {335; CHECKLE-LABEL: vtrnQi16_undef_0:336; CHECKLE: // %bb.0:337; CHECKLE-NEXT: ldr q0, [x0]338; CHECKLE-NEXT: ldr q1, [x1]339; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h340; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h341; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h342; CHECKLE-NEXT: ret343;344; CHECKBE-LABEL: vtrnQi16_undef_0:345; CHECKBE: // %bb.0:346; CHECKBE-NEXT: ld1 { v0.8h }, [x0]347; CHECKBE-NEXT: ld1 { v1.8h }, [x1]348; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h349; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h350; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h351; CHECKBE-NEXT: rev64 v0.8h, v0.8h352; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8353; CHECKBE-NEXT: ret354 %tmp1 = load <8 x i16>, ptr %A355 %tmp2 = load <8 x i16>, ptr %B356 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 8, i32 poison, i32 poison, i32 4, i32 12, i32 6, i32 14>357 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 9, i32 3, i32 11, i32 5, i32 13, i32 poison, i32 poison>358 %tmp5 = add <8 x i16> %tmp3, %tmp4359 ret <8 x i16> %tmp5360}361 362define <4 x i32> @vtrnQi32_undef_1(ptr %A, ptr %B) nounwind {363; CHECKLE-LABEL: vtrnQi32_undef_1:364; CHECKLE: // %bb.0:365; CHECKLE-NEXT: ldr q0, [x0]366; CHECKLE-NEXT: ldr q1, [x1]367; CHECKLE-NEXT: trn1 v2.4s, v0.4s, v1.4s368; CHECKLE-NEXT: trn2 v0.4s, v0.4s, v1.4s369; CHECKLE-NEXT: add v0.4s, v2.4s, v0.4s370; CHECKLE-NEXT: ret371;372; CHECKBE-LABEL: vtrnQi32_undef_1:373; CHECKBE: // %bb.0:374; CHECKBE-NEXT: ld1 { v0.4s }, [x0]375; CHECKBE-NEXT: ld1 { v1.4s }, [x1]376; CHECKBE-NEXT: trn1 v2.4s, v0.4s, v1.4s377; CHECKBE-NEXT: trn2 v0.4s, v0.4s, v1.4s378; CHECKBE-NEXT: add v0.4s, v2.4s, v0.4s379; CHECKBE-NEXT: rev64 v0.4s, v0.4s380; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8381; CHECKBE-NEXT: ret382 %tmp1 = load <4 x i32>, ptr %A383 %tmp2 = load <4 x i32>, ptr %B384 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 poison, i32 2, i32 6>385 %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 poison, i32 3, i32 7>386 %tmp5 = add <4 x i32> %tmp3, %tmp4387 ret <4 x i32> %tmp5388}389 390define <16 x i8> @vtrnQi8_undef_012(ptr %A, ptr %B) nounwind {391; CHECKLE-LABEL: vtrnQi8_undef_012:392; CHECKLE: // %bb.0:393; CHECKLE-NEXT: ldr q0, [x0]394; CHECKLE-NEXT: ldr q1, [x1]395; CHECKLE-NEXT: trn1 v2.16b, v0.16b, v1.16b396; CHECKLE-NEXT: trn2 v0.16b, v0.16b, v1.16b397; CHECKLE-NEXT: add v0.16b, v2.16b, v0.16b398; CHECKLE-NEXT: ret399;400; CHECKBE-LABEL: vtrnQi8_undef_012:401; CHECKBE: // %bb.0:402; CHECKBE-NEXT: ld1 { v0.16b }, [x0]403; CHECKBE-NEXT: ld1 { v1.16b }, [x1]404; CHECKBE-NEXT: trn1 v2.16b, v0.16b, v1.16b405; CHECKBE-NEXT: trn2 v0.16b, v0.16b, v1.16b406; CHECKBE-NEXT: add v0.16b, v2.16b, v0.16b407; CHECKBE-NEXT: rev64 v0.16b, v0.16b408; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8409; CHECKBE-NEXT: ret410 %tmp1 = load <16 x i8>, ptr %A411 %tmp2 = load <16 x i8>, ptr %B412 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 18, i32 4, i32 poison, i32 6, i32 22, i32 poison, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>413 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 19, i32 5, i32 21, i32 7, i32 poison, i32 9, i32 25, i32 11, i32 27, i32 poison, i32 29, i32 15, i32 31>414 %tmp5 = add <16 x i8> %tmp3, %tmp4415 ret <16 x i8> %tmp5416}417