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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s -check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {6; CHECK-LABEL: sabdl8h:7; CHECK: // %bb.0:8; CHECK-NEXT: ldr d0, [x0]9; CHECK-NEXT: ldr d1, [x1]10; CHECK-NEXT: sabdl.8h v0, v0, v111; CHECK-NEXT: ret12 %tmp1 = load <8 x i8>, ptr %A13 %tmp2 = load <8 x i8>, ptr %B14 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)15 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>16 ret <8 x i16> %tmp417}18 19define <4 x i32> @sabdl4s(ptr %A, ptr %B) nounwind {20; CHECK-LABEL: sabdl4s:21; CHECK: // %bb.0:22; CHECK-NEXT: ldr d0, [x0]23; CHECK-NEXT: ldr d1, [x1]24; CHECK-NEXT: sabdl.4s v0, v0, v125; CHECK-NEXT: ret26 %tmp1 = load <4 x i16>, ptr %A27 %tmp2 = load <4 x i16>, ptr %B28 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)29 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>30 ret <4 x i32> %tmp431}32 33define <2 x i64> @sabdl2d(ptr %A, ptr %B) nounwind {34; CHECK-LABEL: sabdl2d:35; CHECK: // %bb.0:36; CHECK-NEXT: ldr d0, [x0]37; CHECK-NEXT: ldr d1, [x1]38; CHECK-NEXT: sabdl.2d v0, v0, v139; CHECK-NEXT: ret40 %tmp1 = load <2 x i32>, ptr %A41 %tmp2 = load <2 x i32>, ptr %B42 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)43 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>44 ret <2 x i64> %tmp445}46 47define void @commutable_sabdl(ptr %A, ptr %B, ptr %C) nounwind {48; CHECK-SD-LABEL: commutable_sabdl:49; CHECK-SD: // %bb.0:50; CHECK-SD-NEXT: ldr d0, [x0]51; CHECK-SD-NEXT: ldr d1, [x1]52; CHECK-SD-NEXT: sabdl.8h v0, v1, v053; CHECK-SD-NEXT: str q0, [x2]54; CHECK-SD-NEXT: ret55;56; CHECK-GI-LABEL: commutable_sabdl:57; CHECK-GI: // %bb.0:58; CHECK-GI-NEXT: ldr d0, [x0]59; CHECK-GI-NEXT: ldr d1, [x1]60; CHECK-GI-NEXT: sabdl.8h v0, v0, v161; CHECK-GI-NEXT: str q0, [x2]62; CHECK-GI-NEXT: str q0, [x2]63; CHECK-GI-NEXT: ret64 %tmp1 = load <8 x i8>, ptr %A65 %tmp2 = load <8 x i8>, ptr %B66 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)67 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>68 store <8 x i16> %tmp4, ptr %C69 %tmp5 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp1)70 %tmp6 = zext <8 x i8> %tmp5 to <8 x i16>71 %tmp7 = getelementptr i8, ptr %C, i64 1672 store <8 x i16> %tmp6, ptr %C73 ret void74}75 76define <8 x i16> @sabdl2_8h(ptr %A, ptr %B) nounwind {77; CHECK-SD-LABEL: sabdl2_8h:78; CHECK-SD: // %bb.0:79; CHECK-SD-NEXT: ldr d0, [x0, #8]80; CHECK-SD-NEXT: ldr d1, [x1, #8]81; CHECK-SD-NEXT: sabdl.8h v0, v0, v182; CHECK-SD-NEXT: ret83;84; CHECK-GI-LABEL: sabdl2_8h:85; CHECK-GI: // %bb.0:86; CHECK-GI-NEXT: ldr q0, [x0]87; CHECK-GI-NEXT: ldr q1, [x1]88; CHECK-GI-NEXT: sabdl2.8h v0, v0, v189; CHECK-GI-NEXT: ret90 %load1 = load <16 x i8>, ptr %A91 %load2 = load <16 x i8>, ptr %B92 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>93 %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>94 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)95 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>96 ret <8 x i16> %tmp497}98 99define <4 x i32> @sabdl2_4s(ptr %A, ptr %B) nounwind {100; CHECK-SD-LABEL: sabdl2_4s:101; CHECK-SD: // %bb.0:102; CHECK-SD-NEXT: ldr d0, [x0, #8]103; CHECK-SD-NEXT: ldr d1, [x1, #8]104; CHECK-SD-NEXT: sabdl.4s v0, v0, v1105; CHECK-SD-NEXT: ret106;107; CHECK-GI-LABEL: sabdl2_4s:108; CHECK-GI: // %bb.0:109; CHECK-GI-NEXT: ldr q0, [x0]110; CHECK-GI-NEXT: ldr q1, [x1]111; CHECK-GI-NEXT: sabdl2.4s v0, v0, v1112; CHECK-GI-NEXT: ret113 %load1 = load <8 x i16>, ptr %A114 %load2 = load <8 x i16>, ptr %B115 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>116 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>117 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)118 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>119 ret <4 x i32> %tmp4120}121 122define <2 x i64> @sabdl2_2d(ptr %A, ptr %B) nounwind {123; CHECK-SD-LABEL: sabdl2_2d:124; CHECK-SD: // %bb.0:125; CHECK-SD-NEXT: ldr d0, [x0, #8]126; CHECK-SD-NEXT: ldr d1, [x1, #8]127; CHECK-SD-NEXT: sabdl.2d v0, v0, v1128; CHECK-SD-NEXT: ret129;130; CHECK-GI-LABEL: sabdl2_2d:131; CHECK-GI: // %bb.0:132; CHECK-GI-NEXT: ldr q0, [x0]133; CHECK-GI-NEXT: ldr q1, [x1]134; CHECK-GI-NEXT: sabdl2.2d v0, v0, v1135; CHECK-GI-NEXT: ret136 %load1 = load <4 x i32>, ptr %A137 %load2 = load <4 x i32>, ptr %B138 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>139 %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>140 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)141 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>142 ret <2 x i64> %tmp4143}144 145define <8 x i16> @uabdl8h(ptr %A, ptr %B) nounwind {146; CHECK-LABEL: uabdl8h:147; CHECK: // %bb.0:148; CHECK-NEXT: ldr d0, [x0]149; CHECK-NEXT: ldr d1, [x1]150; CHECK-NEXT: uabdl.8h v0, v0, v1151; CHECK-NEXT: ret152 %tmp1 = load <8 x i8>, ptr %A153 %tmp2 = load <8 x i8>, ptr %B154 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)155 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>156 ret <8 x i16> %tmp4157}158 159define <4 x i32> @uabdl4s(ptr %A, ptr %B) nounwind {160; CHECK-LABEL: uabdl4s:161; CHECK: // %bb.0:162; CHECK-NEXT: ldr d0, [x0]163; CHECK-NEXT: ldr d1, [x1]164; CHECK-NEXT: uabdl.4s v0, v0, v1165; CHECK-NEXT: ret166 %tmp1 = load <4 x i16>, ptr %A167 %tmp2 = load <4 x i16>, ptr %B168 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)169 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>170 ret <4 x i32> %tmp4171}172 173define <2 x i64> @uabdl2d(ptr %A, ptr %B) nounwind {174; CHECK-LABEL: uabdl2d:175; CHECK: // %bb.0:176; CHECK-NEXT: ldr d0, [x0]177; CHECK-NEXT: ldr d1, [x1]178; CHECK-NEXT: uabdl.2d v0, v0, v1179; CHECK-NEXT: ret180 %tmp1 = load <2 x i32>, ptr %A181 %tmp2 = load <2 x i32>, ptr %B182 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)183 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>184 ret <2 x i64> %tmp4185}186 187define void @commutable_uabdl(ptr %A, ptr %B, ptr %C) nounwind {188; CHECK-SD-LABEL: commutable_uabdl:189; CHECK-SD: // %bb.0:190; CHECK-SD-NEXT: ldr d0, [x0]191; CHECK-SD-NEXT: ldr d1, [x1]192; CHECK-SD-NEXT: uabdl.8h v0, v1, v0193; CHECK-SD-NEXT: str q0, [x2]194; CHECK-SD-NEXT: ret195;196; CHECK-GI-LABEL: commutable_uabdl:197; CHECK-GI: // %bb.0:198; CHECK-GI-NEXT: ldr d0, [x0]199; CHECK-GI-NEXT: ldr d1, [x1]200; CHECK-GI-NEXT: uabdl.8h v0, v0, v1201; CHECK-GI-NEXT: str q0, [x2]202; CHECK-GI-NEXT: str q0, [x2]203; CHECK-GI-NEXT: ret204 %tmp1 = load <8 x i8>, ptr %A205 %tmp2 = load <8 x i8>, ptr %B206 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)207 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>208 store <8 x i16> %tmp4, ptr %C209 %tmp5 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp1)210 %tmp6 = zext <8 x i8> %tmp5 to <8 x i16>211 %tmp7 = getelementptr i8, ptr %C, i64 16212 store <8 x i16> %tmp6, ptr %C213 ret void214}215 216define <8 x i16> @uabdl2_8h(ptr %A, ptr %B) nounwind {217; CHECK-SD-LABEL: uabdl2_8h:218; CHECK-SD: // %bb.0:219; CHECK-SD-NEXT: ldr d0, [x0, #8]220; CHECK-SD-NEXT: ldr d1, [x1, #8]221; CHECK-SD-NEXT: uabdl.8h v0, v0, v1222; CHECK-SD-NEXT: ret223;224; CHECK-GI-LABEL: uabdl2_8h:225; CHECK-GI: // %bb.0:226; CHECK-GI-NEXT: ldr q0, [x0]227; CHECK-GI-NEXT: ldr q1, [x1]228; CHECK-GI-NEXT: uabdl2.8h v0, v0, v1229; CHECK-GI-NEXT: ret230 %load1 = load <16 x i8>, ptr %A231 %load2 = load <16 x i8>, ptr %B232 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>233 %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>234 235 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)236 %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>237 ret <8 x i16> %tmp4238}239 240define <4 x i32> @uabdl2_4s(ptr %A, ptr %B) nounwind {241; CHECK-SD-LABEL: uabdl2_4s:242; CHECK-SD: // %bb.0:243; CHECK-SD-NEXT: ldr d0, [x0, #8]244; CHECK-SD-NEXT: ldr d1, [x1, #8]245; CHECK-SD-NEXT: uabdl.4s v0, v0, v1246; CHECK-SD-NEXT: ret247;248; CHECK-GI-LABEL: uabdl2_4s:249; CHECK-GI: // %bb.0:250; CHECK-GI-NEXT: ldr q0, [x0]251; CHECK-GI-NEXT: ldr q1, [x1]252; CHECK-GI-NEXT: uabdl2.4s v0, v0, v1253; CHECK-GI-NEXT: ret254 %load1 = load <8 x i16>, ptr %A255 %load2 = load <8 x i16>, ptr %B256 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>257 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>258 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)259 %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>260 ret <4 x i32> %tmp4261}262 263define <2 x i64> @uabdl2_2d(ptr %A, ptr %B) nounwind {264; CHECK-SD-LABEL: uabdl2_2d:265; CHECK-SD: // %bb.0:266; CHECK-SD-NEXT: ldr d0, [x0, #8]267; CHECK-SD-NEXT: ldr d1, [x1, #8]268; CHECK-SD-NEXT: uabdl.2d v0, v0, v1269; CHECK-SD-NEXT: ret270;271; CHECK-GI-LABEL: uabdl2_2d:272; CHECK-GI: // %bb.0:273; CHECK-GI-NEXT: ldr q0, [x0]274; CHECK-GI-NEXT: ldr q1, [x1]275; CHECK-GI-NEXT: uabdl2.2d v0, v0, v1276; CHECK-GI-NEXT: ret277 %load1 = load <4 x i32>, ptr %A278 %load2 = load <4 x i32>, ptr %B279 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>280 %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>281 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)282 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>283 ret <2 x i64> %tmp4284}285 286declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)287declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)288 289define i16 @uabd16b_rdx(ptr %a, ptr %b) {290; CHECK-SD-LABEL: uabd16b_rdx:291; CHECK-SD: // %bb.0:292; CHECK-SD-NEXT: ldr q0, [x0]293; CHECK-SD-NEXT: ldr q1, [x1]294; CHECK-SD-NEXT: uabd.16b v0, v0, v1295; CHECK-SD-NEXT: uaddlv.16b h0, v0296; CHECK-SD-NEXT: fmov w0, s0297; CHECK-SD-NEXT: ret298;299; CHECK-GI-LABEL: uabd16b_rdx:300; CHECK-GI: // %bb.0:301; CHECK-GI-NEXT: ldr q0, [x0]302; CHECK-GI-NEXT: ldr q1, [x1]303; CHECK-GI-NEXT: usubl.8h v2, v0, v1304; CHECK-GI-NEXT: usubl2.8h v0, v0, v1305; CHECK-GI-NEXT: cmlt.8h v1, v2, #0306; CHECK-GI-NEXT: cmlt.8h v3, v0, #0307; CHECK-GI-NEXT: neg.8h v4, v2308; CHECK-GI-NEXT: neg.8h v5, v0309; CHECK-GI-NEXT: bsl.16b v1, v4, v2310; CHECK-GI-NEXT: bit.16b v0, v5, v3311; CHECK-GI-NEXT: add.8h v0, v1, v0312; CHECK-GI-NEXT: addv.8h h0, v0313; CHECK-GI-NEXT: fmov w0, s0314; CHECK-GI-NEXT: ret315 %aload = load <16 x i8>, ptr %a, align 1316 %bload = load <16 x i8>, ptr %b, align 1317 %aext = zext <16 x i8> %aload to <16 x i16>318 %bext = zext <16 x i8> %bload to <16 x i16>319 %abdiff = sub nsw <16 x i16> %aext, %bext320 %abcmp = icmp slt <16 x i16> %abdiff, zeroinitializer321 %ababs = sub nsw <16 x i16> zeroinitializer, %abdiff322 %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff323 %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)324 ret i16 %reduced_v325}326 327define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {328; CHECK-SD-LABEL: uabd16b_rdx_i32:329; CHECK-SD: // %bb.0:330; CHECK-SD-NEXT: uabdl.8h v2, v0, v1331; CHECK-SD-NEXT: uabal2.8h v2, v0, v1332; CHECK-SD-NEXT: uaddlv.8h s0, v2333; CHECK-SD-NEXT: fmov w0, s0334; CHECK-SD-NEXT: ret335;336; CHECK-GI-LABEL: uabd16b_rdx_i32:337; CHECK-GI: // %bb.0:338; CHECK-GI-NEXT: usubl.8h v3, v0, v1339; CHECK-GI-NEXT: movi.2d v2, #0000000000000000340; CHECK-GI-NEXT: usubl2.8h v0, v0, v1341; CHECK-GI-NEXT: sshll.4s v1, v3, #0342; CHECK-GI-NEXT: sshll2.4s v4, v3, #0343; CHECK-GI-NEXT: sshll.4s v5, v0, #0344; CHECK-GI-NEXT: sshll2.4s v6, v0, #0345; CHECK-GI-NEXT: ssubw2.4s v3, v2, v3346; CHECK-GI-NEXT: ssubw2.4s v0, v2, v0347; CHECK-GI-NEXT: cmlt.4s v2, v1, #0348; CHECK-GI-NEXT: cmlt.4s v7, v4, #0349; CHECK-GI-NEXT: neg.4s v16, v1350; CHECK-GI-NEXT: cmlt.4s v17, v5, #0351; CHECK-GI-NEXT: cmlt.4s v18, v6, #0352; CHECK-GI-NEXT: neg.4s v19, v5353; CHECK-GI-NEXT: bit.16b v1, v16, v2354; CHECK-GI-NEXT: mov.16b v2, v7355; CHECK-GI-NEXT: bif.16b v0, v6, v18356; CHECK-GI-NEXT: bsl.16b v2, v3, v4357; CHECK-GI-NEXT: mov.16b v3, v17358; CHECK-GI-NEXT: bsl.16b v3, v19, v5359; CHECK-GI-NEXT: add.4s v1, v1, v2360; CHECK-GI-NEXT: add.4s v0, v3, v0361; CHECK-GI-NEXT: add.4s v0, v1, v0362; CHECK-GI-NEXT: addv.4s s0, v0363; CHECK-GI-NEXT: fmov w0, s0364; CHECK-GI-NEXT: ret365 %aext = zext <16 x i8> %a to <16 x i32>366 %bext = zext <16 x i8> %b to <16 x i32>367 %abdiff = sub nsw <16 x i32> %aext, %bext368 %abcmp = icmp slt <16 x i32> %abdiff, zeroinitializer369 %ababs = sub nsw <16 x i32> zeroinitializer, %abdiff370 %absel = select <16 x i1> %abcmp, <16 x i32> %ababs, <16 x i32> %abdiff371 %reduced_v = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %absel)372 ret i32 %reduced_v373}374 375define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {376; CHECK-SD-LABEL: sabd16b_rdx_i32:377; CHECK-SD: // %bb.0:378; CHECK-SD-NEXT: sabdl.8h v2, v0, v1379; CHECK-SD-NEXT: sabal2.8h v2, v0, v1380; CHECK-SD-NEXT: uaddlv.8h s0, v2381; CHECK-SD-NEXT: fmov w0, s0382; CHECK-SD-NEXT: ret383;384; CHECK-GI-LABEL: sabd16b_rdx_i32:385; CHECK-GI: // %bb.0:386; CHECK-GI-NEXT: ssubl.8h v3, v0, v1387; CHECK-GI-NEXT: movi.2d v2, #0000000000000000388; CHECK-GI-NEXT: ssubl2.8h v0, v0, v1389; CHECK-GI-NEXT: sshll.4s v1, v3, #0390; CHECK-GI-NEXT: sshll2.4s v4, v3, #0391; CHECK-GI-NEXT: sshll.4s v5, v0, #0392; CHECK-GI-NEXT: sshll2.4s v6, v0, #0393; CHECK-GI-NEXT: ssubw2.4s v3, v2, v3394; CHECK-GI-NEXT: ssubw2.4s v0, v2, v0395; CHECK-GI-NEXT: cmlt.4s v2, v1, #0396; CHECK-GI-NEXT: cmlt.4s v7, v4, #0397; CHECK-GI-NEXT: neg.4s v16, v1398; CHECK-GI-NEXT: cmlt.4s v17, v5, #0399; CHECK-GI-NEXT: cmlt.4s v18, v6, #0400; CHECK-GI-NEXT: neg.4s v19, v5401; CHECK-GI-NEXT: bit.16b v1, v16, v2402; CHECK-GI-NEXT: mov.16b v2, v7403; CHECK-GI-NEXT: bif.16b v0, v6, v18404; CHECK-GI-NEXT: bsl.16b v2, v3, v4405; CHECK-GI-NEXT: mov.16b v3, v17406; CHECK-GI-NEXT: bsl.16b v3, v19, v5407; CHECK-GI-NEXT: add.4s v1, v1, v2408; CHECK-GI-NEXT: add.4s v0, v3, v0409; CHECK-GI-NEXT: add.4s v0, v1, v0410; CHECK-GI-NEXT: addv.4s s0, v0411; CHECK-GI-NEXT: fmov w0, s0412; CHECK-GI-NEXT: ret413 %aext = sext <16 x i8> %a to <16 x i32>414 %bext = sext <16 x i8> %b to <16 x i32>415 %abdiff = sub nsw <16 x i32> %aext, %bext416 %abcmp = icmp slt <16 x i32> %abdiff, zeroinitializer417 %ababs = sub nsw <16 x i32> zeroinitializer, %abdiff418 %absel = select <16 x i1> %abcmp, <16 x i32> %ababs, <16 x i32> %abdiff419 %reduced_v = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %absel)420 ret i32 %reduced_v421}422 423 424declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)425declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)426 427define i32 @uabd8h_rdx(ptr %a, ptr %b) {428; CHECK-SD-LABEL: uabd8h_rdx:429; CHECK-SD: // %bb.0:430; CHECK-SD-NEXT: ldr q0, [x0]431; CHECK-SD-NEXT: ldr q1, [x1]432; CHECK-SD-NEXT: uabd.8h v0, v0, v1433; CHECK-SD-NEXT: uaddlv.8h s0, v0434; CHECK-SD-NEXT: fmov w0, s0435; CHECK-SD-NEXT: ret436;437; CHECK-GI-LABEL: uabd8h_rdx:438; CHECK-GI: // %bb.0:439; CHECK-GI-NEXT: ldr q0, [x0]440; CHECK-GI-NEXT: ldr q1, [x1]441; CHECK-GI-NEXT: usubl.4s v2, v0, v1442; CHECK-GI-NEXT: usubl2.4s v0, v0, v1443; CHECK-GI-NEXT: cmlt.4s v1, v2, #0444; CHECK-GI-NEXT: cmlt.4s v3, v0, #0445; CHECK-GI-NEXT: neg.4s v4, v2446; CHECK-GI-NEXT: neg.4s v5, v0447; CHECK-GI-NEXT: bsl.16b v1, v4, v2448; CHECK-GI-NEXT: bit.16b v0, v5, v3449; CHECK-GI-NEXT: add.4s v0, v1, v0450; CHECK-GI-NEXT: addv.4s s0, v0451; CHECK-GI-NEXT: fmov w0, s0452; CHECK-GI-NEXT: ret453 %aload = load <8 x i16>, ptr %a, align 1454 %bload = load <8 x i16>, ptr %b, align 1455 %aext = zext <8 x i16> %aload to <8 x i32>456 %bext = zext <8 x i16> %bload to <8 x i32>457 %abdiff = sub nsw <8 x i32> %aext, %bext458 %abcmp = icmp slt <8 x i32> %abdiff, zeroinitializer459 %ababs = sub nsw <8 x i32> zeroinitializer, %abdiff460 %absel = select <8 x i1> %abcmp, <8 x i32> %ababs, <8 x i32> %abdiff461 %reduced_v = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %absel)462 ret i32 %reduced_v463}464 465define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {466; CHECK-SD-LABEL: sabd8h_rdx:467; CHECK-SD: // %bb.0:468; CHECK-SD-NEXT: sabd.8h v0, v0, v1469; CHECK-SD-NEXT: uaddlv.8h s0, v0470; CHECK-SD-NEXT: fmov w0, s0471; CHECK-SD-NEXT: ret472;473; CHECK-GI-LABEL: sabd8h_rdx:474; CHECK-GI: // %bb.0:475; CHECK-GI-NEXT: ssubl.4s v2, v0, v1476; CHECK-GI-NEXT: ssubl2.4s v0, v0, v1477; CHECK-GI-NEXT: cmlt.4s v1, v2, #0478; CHECK-GI-NEXT: cmlt.4s v3, v0, #0479; CHECK-GI-NEXT: neg.4s v4, v2480; CHECK-GI-NEXT: neg.4s v5, v0481; CHECK-GI-NEXT: bsl.16b v1, v4, v2482; CHECK-GI-NEXT: bit.16b v0, v5, v3483; CHECK-GI-NEXT: add.4s v0, v1, v0484; CHECK-GI-NEXT: addv.4s s0, v0485; CHECK-GI-NEXT: fmov w0, s0486; CHECK-GI-NEXT: ret487 %aext = sext <8 x i16> %a to <8 x i32>488 %bext = sext <8 x i16> %b to <8 x i32>489 %abdiff = sub nsw <8 x i32> %aext, %bext490 %abcmp = icmp slt <8 x i32> %abdiff, zeroinitializer491 %ababs = sub nsw <8 x i32> zeroinitializer, %abdiff492 %absel = select <8 x i1> %abcmp, <8 x i32> %ababs, <8 x i32> %abdiff493 %reduced_v = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %absel)494 ret i32 %reduced_v495}496 497define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {498; CHECK-SD-LABEL: uabdl4s_rdx_i32:499; CHECK-SD: // %bb.0:500; CHECK-SD-NEXT: uabd.4h v0, v0, v1501; CHECK-SD-NEXT: uaddlv.4h s0, v0502; CHECK-SD-NEXT: fmov w0, s0503; CHECK-SD-NEXT: ret504;505; CHECK-GI-LABEL: uabdl4s_rdx_i32:506; CHECK-GI: // %bb.0:507; CHECK-GI-NEXT: usubl.4s v0, v0, v1508; CHECK-GI-NEXT: cmlt.4s v1, v0, #0509; CHECK-GI-NEXT: neg.4s v2, v0510; CHECK-GI-NEXT: bit.16b v0, v2, v1511; CHECK-GI-NEXT: addv.4s s0, v0512; CHECK-GI-NEXT: fmov w0, s0513; CHECK-GI-NEXT: ret514 %aext = zext <4 x i16> %a to <4 x i32>515 %bext = zext <4 x i16> %b to <4 x i32>516 %abdiff = sub nsw <4 x i32> %aext, %bext517 %abcmp = icmp slt <4 x i32> %abdiff, zeroinitializer518 %ababs = sub nsw <4 x i32> zeroinitializer, %abdiff519 %absel = select <4 x i1> %abcmp, <4 x i32> %ababs, <4 x i32> %abdiff520 %reduced_v = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %absel)521 ret i32 %reduced_v522}523 524declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)525declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)526 527define i64 @uabd4s_rdx(ptr %a, ptr %b, i32 %h) {528; CHECK-SD-LABEL: uabd4s_rdx:529; CHECK-SD: // %bb.0:530; CHECK-SD-NEXT: ldr q0, [x0]531; CHECK-SD-NEXT: ldr q1, [x1]532; CHECK-SD-NEXT: uabd.4s v0, v0, v1533; CHECK-SD-NEXT: uaddlv.4s d0, v0534; CHECK-SD-NEXT: fmov x0, d0535; CHECK-SD-NEXT: ret536;537; CHECK-GI-LABEL: uabd4s_rdx:538; CHECK-GI: // %bb.0:539; CHECK-GI-NEXT: ldr q0, [x0]540; CHECK-GI-NEXT: ldr q1, [x1]541; CHECK-GI-NEXT: usubl.2d v2, v0, v1542; CHECK-GI-NEXT: usubl2.2d v0, v0, v1543; CHECK-GI-NEXT: cmlt.2d v1, v2, #0544; CHECK-GI-NEXT: cmlt.2d v3, v0, #0545; CHECK-GI-NEXT: neg.2d v4, v2546; CHECK-GI-NEXT: neg.2d v5, v0547; CHECK-GI-NEXT: bsl.16b v1, v4, v2548; CHECK-GI-NEXT: bit.16b v0, v5, v3549; CHECK-GI-NEXT: add.2d v0, v1, v0550; CHECK-GI-NEXT: addp.2d d0, v0551; CHECK-GI-NEXT: fmov x0, d0552; CHECK-GI-NEXT: ret553 %aload = load <4 x i32>, ptr %a, align 1554 %bload = load <4 x i32>, ptr %b, align 1555 %aext = zext <4 x i32> %aload to <4 x i64>556 %bext = zext <4 x i32> %bload to <4 x i64>557 %abdiff = sub nsw <4 x i64> %aext, %bext558 %abcmp = icmp slt <4 x i64> %abdiff, zeroinitializer559 %ababs = sub nsw <4 x i64> zeroinitializer, %abdiff560 %absel = select <4 x i1> %abcmp, <4 x i64> %ababs, <4 x i64> %abdiff561 %reduced_v = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %absel)562 ret i64 %reduced_v563}564 565define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {566; CHECK-SD-LABEL: sabd4s_rdx:567; CHECK-SD: // %bb.0:568; CHECK-SD-NEXT: sabd.4s v0, v0, v1569; CHECK-SD-NEXT: uaddlv.4s d0, v0570; CHECK-SD-NEXT: fmov x0, d0571; CHECK-SD-NEXT: ret572;573; CHECK-GI-LABEL: sabd4s_rdx:574; CHECK-GI: // %bb.0:575; CHECK-GI-NEXT: ssubl.2d v2, v0, v1576; CHECK-GI-NEXT: ssubl2.2d v0, v0, v1577; CHECK-GI-NEXT: cmlt.2d v1, v2, #0578; CHECK-GI-NEXT: cmlt.2d v3, v0, #0579; CHECK-GI-NEXT: neg.2d v4, v2580; CHECK-GI-NEXT: neg.2d v5, v0581; CHECK-GI-NEXT: bsl.16b v1, v4, v2582; CHECK-GI-NEXT: bit.16b v0, v5, v3583; CHECK-GI-NEXT: add.2d v0, v1, v0584; CHECK-GI-NEXT: addp.2d d0, v0585; CHECK-GI-NEXT: fmov x0, d0586; CHECK-GI-NEXT: ret587 %aext = sext <4 x i32> %a to <4 x i64>588 %bext = sext <4 x i32> %b to <4 x i64>589 %abdiff = sub nsw <4 x i64> %aext, %bext590 %abcmp = icmp slt <4 x i64> %abdiff, zeroinitializer591 %ababs = sub nsw <4 x i64> zeroinitializer, %abdiff592 %absel = select <4 x i1> %abcmp, <4 x i64> %ababs, <4 x i64> %abdiff593 %reduced_v = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %absel)594 ret i64 %reduced_v595}596 597define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {598; CHECK-SD-LABEL: uabdl2d_rdx_i64:599; CHECK-SD: // %bb.0:600; CHECK-SD-NEXT: uabdl.2d v0, v0, v1601; CHECK-SD-NEXT: addp.2d d0, v0602; CHECK-SD-NEXT: fmov x0, d0603; CHECK-SD-NEXT: ret604;605; CHECK-GI-LABEL: uabdl2d_rdx_i64:606; CHECK-GI: // %bb.0:607; CHECK-GI-NEXT: usubl.2d v0, v0, v1608; CHECK-GI-NEXT: cmlt.2d v1, v0, #0609; CHECK-GI-NEXT: neg.2d v2, v0610; CHECK-GI-NEXT: bit.16b v0, v2, v1611; CHECK-GI-NEXT: addp.2d d0, v0612; CHECK-GI-NEXT: fmov x0, d0613; CHECK-GI-NEXT: ret614 %aext = zext <2 x i32> %a to <2 x i64>615 %bext = zext <2 x i32> %b to <2 x i64>616 %abdiff = sub nsw <2 x i64> %aext, %bext617 %abcmp = icmp slt <2 x i64> %abdiff, zeroinitializer618 %ababs = sub nsw <2 x i64> zeroinitializer, %abdiff619 %absel = select <2 x i1> %abcmp, <2 x i64> %ababs, <2 x i64> %abdiff620 %reduced_v = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %absel)621 ret i64 %reduced_v622}623 624define <2 x float> @fabd_2s(ptr %A, ptr %B) nounwind {625; CHECK-LABEL: fabd_2s:626; CHECK: // %bb.0:627; CHECK-NEXT: ldr d0, [x0]628; CHECK-NEXT: ldr d1, [x1]629; CHECK-NEXT: fabd.2s v0, v0, v1630; CHECK-NEXT: ret631 %tmp1 = load <2 x float>, ptr %A632 %tmp2 = load <2 x float>, ptr %B633 %tmp3 = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)634 ret <2 x float> %tmp3635}636 637define <4 x float> @fabd_4s(ptr %A, ptr %B) nounwind {638; CHECK-LABEL: fabd_4s:639; CHECK: // %bb.0:640; CHECK-NEXT: ldr q0, [x0]641; CHECK-NEXT: ldr q1, [x1]642; CHECK-NEXT: fabd.4s v0, v0, v1643; CHECK-NEXT: ret644 %tmp1 = load <4 x float>, ptr %A645 %tmp2 = load <4 x float>, ptr %B646 %tmp3 = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)647 ret <4 x float> %tmp3648}649 650define <2 x double> @fabd_2d(ptr %A, ptr %B) nounwind {651; CHECK-LABEL: fabd_2d:652; CHECK: // %bb.0:653; CHECK-NEXT: ldr q0, [x0]654; CHECK-NEXT: ldr q1, [x1]655; CHECK-NEXT: fabd.2d v0, v0, v1656; CHECK-NEXT: ret657 %tmp1 = load <2 x double>, ptr %A658 %tmp2 = load <2 x double>, ptr %B659 %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)660 ret <2 x double> %tmp3661}662 663declare <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float>, <2 x float>) nounwind readnone664declare <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float>, <4 x float>) nounwind readnone665declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>) nounwind readnone666 667define <2 x float> @fabd_2s_from_fsub_fabs(ptr %A, ptr %B) nounwind {668; CHECK-LABEL: fabd_2s_from_fsub_fabs:669; CHECK: // %bb.0:670; CHECK-NEXT: ldr d0, [x0]671; CHECK-NEXT: ldr d1, [x1]672; CHECK-NEXT: fabd.2s v0, v0, v1673; CHECK-NEXT: ret674 %tmp1 = load <2 x float>, ptr %A675 %tmp2 = load <2 x float>, ptr %B676 %sub = fsub <2 x float> %tmp1, %tmp2677 %abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %sub)678 ret <2 x float> %abs679}680 681define <4 x float> @fabd_4s_from_fsub_fabs(ptr %A, ptr %B) nounwind {682; CHECK-LABEL: fabd_4s_from_fsub_fabs:683; CHECK: // %bb.0:684; CHECK-NEXT: ldr q0, [x0]685; CHECK-NEXT: ldr q1, [x1]686; CHECK-NEXT: fabd.4s v0, v0, v1687; CHECK-NEXT: ret688 %tmp1 = load <4 x float>, ptr %A689 %tmp2 = load <4 x float>, ptr %B690 %sub = fsub <4 x float> %tmp1, %tmp2691 %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %sub)692 ret <4 x float> %abs693}694 695define <2 x double> @fabd_2d_from_fsub_fabs(ptr %A, ptr %B) nounwind {696; CHECK-LABEL: fabd_2d_from_fsub_fabs:697; CHECK: // %bb.0:698; CHECK-NEXT: ldr q0, [x0]699; CHECK-NEXT: ldr q1, [x1]700; CHECK-NEXT: fabd.2d v0, v0, v1701; CHECK-NEXT: ret702 %tmp1 = load <2 x double>, ptr %A703 %tmp2 = load <2 x double>, ptr %B704 %sub = fsub <2 x double> %tmp1, %tmp2705 %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %sub)706 ret <2 x double> %abs707}708 709declare <2 x float> @llvm.fabs.v2f32(<2 x float>) nounwind readnone710declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone711declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone712 713define <8 x i8> @sabd_8b(ptr %A, ptr %B) nounwind {714; CHECK-LABEL: sabd_8b:715; CHECK: // %bb.0:716; CHECK-NEXT: ldr d0, [x0]717; CHECK-NEXT: ldr d1, [x1]718; CHECK-NEXT: sabd.8b v0, v0, v1719; CHECK-NEXT: ret720 %tmp1 = load <8 x i8>, ptr %A721 %tmp2 = load <8 x i8>, ptr %B722 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)723 ret <8 x i8> %tmp3724}725 726define <16 x i8> @sabd_16b(ptr %A, ptr %B) nounwind {727; CHECK-LABEL: sabd_16b:728; CHECK: // %bb.0:729; CHECK-NEXT: ldr q0, [x0]730; CHECK-NEXT: ldr q1, [x1]731; CHECK-NEXT: sabd.16b v0, v0, v1732; CHECK-NEXT: ret733 %tmp1 = load <16 x i8>, ptr %A734 %tmp2 = load <16 x i8>, ptr %B735 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)736 ret <16 x i8> %tmp3737}738 739define <4 x i16> @sabd_4h(ptr %A, ptr %B) nounwind {740; CHECK-LABEL: sabd_4h:741; CHECK: // %bb.0:742; CHECK-NEXT: ldr d0, [x0]743; CHECK-NEXT: ldr d1, [x1]744; CHECK-NEXT: sabd.4h v0, v0, v1745; CHECK-NEXT: ret746 %tmp1 = load <4 x i16>, ptr %A747 %tmp2 = load <4 x i16>, ptr %B748 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)749 ret <4 x i16> %tmp3750}751 752define <8 x i16> @sabd_8h(ptr %A, ptr %B) nounwind {753; CHECK-LABEL: sabd_8h:754; CHECK: // %bb.0:755; CHECK-NEXT: ldr q0, [x0]756; CHECK-NEXT: ldr q1, [x1]757; CHECK-NEXT: sabd.8h v0, v0, v1758; CHECK-NEXT: ret759 %tmp1 = load <8 x i16>, ptr %A760 %tmp2 = load <8 x i16>, ptr %B761 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)762 ret <8 x i16> %tmp3763}764 765define <2 x i32> @sabd_2s(ptr %A, ptr %B) nounwind {766; CHECK-LABEL: sabd_2s:767; CHECK: // %bb.0:768; CHECK-NEXT: ldr d0, [x0]769; CHECK-NEXT: ldr d1, [x1]770; CHECK-NEXT: sabd.2s v0, v0, v1771; CHECK-NEXT: ret772 %tmp1 = load <2 x i32>, ptr %A773 %tmp2 = load <2 x i32>, ptr %B774 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)775 ret <2 x i32> %tmp3776}777 778define <4 x i32> @sabd_4s(ptr %A, ptr %B) nounwind {779; CHECK-LABEL: sabd_4s:780; CHECK: // %bb.0:781; CHECK-NEXT: ldr q0, [x0]782; CHECK-NEXT: ldr q1, [x1]783; CHECK-NEXT: sabd.4s v0, v0, v1784; CHECK-NEXT: ret785 %tmp1 = load <4 x i32>, ptr %A786 %tmp2 = load <4 x i32>, ptr %B787 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)788 ret <4 x i32> %tmp3789}790 791declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone792declare <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone793declare <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone794declare <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone795declare <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone796declare <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone797 798define <8 x i8> @uabd_8b(ptr %A, ptr %B) nounwind {799; CHECK-LABEL: uabd_8b:800; CHECK: // %bb.0:801; CHECK-NEXT: ldr d0, [x0]802; CHECK-NEXT: ldr d1, [x1]803; CHECK-NEXT: uabd.8b v0, v0, v1804; CHECK-NEXT: ret805 %tmp1 = load <8 x i8>, ptr %A806 %tmp2 = load <8 x i8>, ptr %B807 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)808 ret <8 x i8> %tmp3809}810 811define <16 x i8> @uabd_16b(ptr %A, ptr %B) nounwind {812; CHECK-LABEL: uabd_16b:813; CHECK: // %bb.0:814; CHECK-NEXT: ldr q0, [x0]815; CHECK-NEXT: ldr q1, [x1]816; CHECK-NEXT: uabd.16b v0, v0, v1817; CHECK-NEXT: ret818 %tmp1 = load <16 x i8>, ptr %A819 %tmp2 = load <16 x i8>, ptr %B820 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)821 ret <16 x i8> %tmp3822}823 824define <4 x i16> @uabd_4h(ptr %A, ptr %B) nounwind {825; CHECK-LABEL: uabd_4h:826; CHECK: // %bb.0:827; CHECK-NEXT: ldr d0, [x0]828; CHECK-NEXT: ldr d1, [x1]829; CHECK-NEXT: uabd.4h v0, v0, v1830; CHECK-NEXT: ret831 %tmp1 = load <4 x i16>, ptr %A832 %tmp2 = load <4 x i16>, ptr %B833 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)834 ret <4 x i16> %tmp3835}836 837define <8 x i16> @uabd_8h(ptr %A, ptr %B) nounwind {838; CHECK-LABEL: uabd_8h:839; CHECK: // %bb.0:840; CHECK-NEXT: ldr q0, [x0]841; CHECK-NEXT: ldr q1, [x1]842; CHECK-NEXT: uabd.8h v0, v0, v1843; CHECK-NEXT: ret844 %tmp1 = load <8 x i16>, ptr %A845 %tmp2 = load <8 x i16>, ptr %B846 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)847 ret <8 x i16> %tmp3848}849 850define <2 x i32> @uabd_2s(ptr %A, ptr %B) nounwind {851; CHECK-LABEL: uabd_2s:852; CHECK: // %bb.0:853; CHECK-NEXT: ldr d0, [x0]854; CHECK-NEXT: ldr d1, [x1]855; CHECK-NEXT: uabd.2s v0, v0, v1856; CHECK-NEXT: ret857 %tmp1 = load <2 x i32>, ptr %A858 %tmp2 = load <2 x i32>, ptr %B859 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)860 ret <2 x i32> %tmp3861}862 863define <4 x i32> @uabd_4s(ptr %A, ptr %B) nounwind {864; CHECK-LABEL: uabd_4s:865; CHECK: // %bb.0:866; CHECK-NEXT: ldr q0, [x0]867; CHECK-NEXT: ldr q1, [x1]868; CHECK-NEXT: uabd.4s v0, v0, v1869; CHECK-NEXT: ret870 %tmp1 = load <4 x i32>, ptr %A871 %tmp2 = load <4 x i32>, ptr %B872 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)873 ret <4 x i32> %tmp3874}875 876declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone877declare <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone878declare <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone879declare <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone880declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone881declare <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone882 883define <8 x i8> @sqabs_8b(ptr %A) nounwind {884; CHECK-LABEL: sqabs_8b:885; CHECK: // %bb.0:886; CHECK-NEXT: ldr d0, [x0]887; CHECK-NEXT: sqabs.8b v0, v0888; CHECK-NEXT: ret889 %tmp1 = load <8 x i8>, ptr %A890 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8> %tmp1)891 ret <8 x i8> %tmp3892}893 894define <16 x i8> @sqabs_16b(ptr %A) nounwind {895; CHECK-LABEL: sqabs_16b:896; CHECK: // %bb.0:897; CHECK-NEXT: ldr q0, [x0]898; CHECK-NEXT: sqabs.16b v0, v0899; CHECK-NEXT: ret900 %tmp1 = load <16 x i8>, ptr %A901 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8> %tmp1)902 ret <16 x i8> %tmp3903}904 905define <4 x i16> @sqabs_4h(ptr %A) nounwind {906; CHECK-LABEL: sqabs_4h:907; CHECK: // %bb.0:908; CHECK-NEXT: ldr d0, [x0]909; CHECK-NEXT: sqabs.4h v0, v0910; CHECK-NEXT: ret911 %tmp1 = load <4 x i16>, ptr %A912 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16> %tmp1)913 ret <4 x i16> %tmp3914}915 916define <8 x i16> @sqabs_8h(ptr %A) nounwind {917; CHECK-LABEL: sqabs_8h:918; CHECK: // %bb.0:919; CHECK-NEXT: ldr q0, [x0]920; CHECK-NEXT: sqabs.8h v0, v0921; CHECK-NEXT: ret922 %tmp1 = load <8 x i16>, ptr %A923 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16> %tmp1)924 ret <8 x i16> %tmp3925}926 927define <2 x i32> @sqabs_2s(ptr %A) nounwind {928; CHECK-LABEL: sqabs_2s:929; CHECK: // %bb.0:930; CHECK-NEXT: ldr d0, [x0]931; CHECK-NEXT: sqabs.2s v0, v0932; CHECK-NEXT: ret933 %tmp1 = load <2 x i32>, ptr %A934 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32> %tmp1)935 ret <2 x i32> %tmp3936}937 938define <4 x i32> @sqabs_4s(ptr %A) nounwind {939; CHECK-LABEL: sqabs_4s:940; CHECK: // %bb.0:941; CHECK-NEXT: ldr q0, [x0]942; CHECK-NEXT: sqabs.4s v0, v0943; CHECK-NEXT: ret944 %tmp1 = load <4 x i32>, ptr %A945 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32> %tmp1)946 ret <4 x i32> %tmp3947}948 949declare <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8>) nounwind readnone950declare <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8>) nounwind readnone951declare <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16>) nounwind readnone952declare <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16>) nounwind readnone953declare <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32>) nounwind readnone954declare <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32>) nounwind readnone955 956define <8 x i8> @sqneg_8b(ptr %A) nounwind {957; CHECK-LABEL: sqneg_8b:958; CHECK: // %bb.0:959; CHECK-NEXT: ldr d0, [x0]960; CHECK-NEXT: sqneg.8b v0, v0961; CHECK-NEXT: ret962 %tmp1 = load <8 x i8>, ptr %A963 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8> %tmp1)964 ret <8 x i8> %tmp3965}966 967define <16 x i8> @sqneg_16b(ptr %A) nounwind {968; CHECK-LABEL: sqneg_16b:969; CHECK: // %bb.0:970; CHECK-NEXT: ldr q0, [x0]971; CHECK-NEXT: sqneg.16b v0, v0972; CHECK-NEXT: ret973 %tmp1 = load <16 x i8>, ptr %A974 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8> %tmp1)975 ret <16 x i8> %tmp3976}977 978define <4 x i16> @sqneg_4h(ptr %A) nounwind {979; CHECK-LABEL: sqneg_4h:980; CHECK: // %bb.0:981; CHECK-NEXT: ldr d0, [x0]982; CHECK-NEXT: sqneg.4h v0, v0983; CHECK-NEXT: ret984 %tmp1 = load <4 x i16>, ptr %A985 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16> %tmp1)986 ret <4 x i16> %tmp3987}988 989define <8 x i16> @sqneg_8h(ptr %A) nounwind {990; CHECK-LABEL: sqneg_8h:991; CHECK: // %bb.0:992; CHECK-NEXT: ldr q0, [x0]993; CHECK-NEXT: sqneg.8h v0, v0994; CHECK-NEXT: ret995 %tmp1 = load <8 x i16>, ptr %A996 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %tmp1)997 ret <8 x i16> %tmp3998}999 1000define <2 x i32> @sqneg_2s(ptr %A) nounwind {1001; CHECK-LABEL: sqneg_2s:1002; CHECK: // %bb.0:1003; CHECK-NEXT: ldr d0, [x0]1004; CHECK-NEXT: sqneg.2s v0, v01005; CHECK-NEXT: ret1006 %tmp1 = load <2 x i32>, ptr %A1007 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32> %tmp1)1008 ret <2 x i32> %tmp31009}1010 1011define <4 x i32> @sqneg_4s(ptr %A) nounwind {1012; CHECK-LABEL: sqneg_4s:1013; CHECK: // %bb.0:1014; CHECK-NEXT: ldr q0, [x0]1015; CHECK-NEXT: sqneg.4s v0, v01016; CHECK-NEXT: ret1017 %tmp1 = load <4 x i32>, ptr %A1018 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32> %tmp1)1019 ret <4 x i32> %tmp31020}1021 1022declare <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8>) nounwind readnone1023declare <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8>) nounwind readnone1024declare <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16>) nounwind readnone1025declare <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16>) nounwind readnone1026declare <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32>) nounwind readnone1027declare <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32>) nounwind readnone1028 1029define <8 x i8> @abs_8b(ptr %A) nounwind {1030; CHECK-LABEL: abs_8b:1031; CHECK: // %bb.0:1032; CHECK-NEXT: ldr d0, [x0]1033; CHECK-NEXT: abs.8b v0, v01034; CHECK-NEXT: ret1035 %tmp1 = load <8 x i8>, ptr %A1036 %tmp3 = call <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8> %tmp1)1037 ret <8 x i8> %tmp31038}1039 1040define <16 x i8> @abs_16b(ptr %A) nounwind {1041; CHECK-LABEL: abs_16b:1042; CHECK: // %bb.0:1043; CHECK-NEXT: ldr q0, [x0]1044; CHECK-NEXT: abs.16b v0, v01045; CHECK-NEXT: ret1046 %tmp1 = load <16 x i8>, ptr %A1047 %tmp3 = call <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8> %tmp1)1048 ret <16 x i8> %tmp31049}1050 1051define <4 x i16> @abs_4h(ptr %A) nounwind {1052; CHECK-LABEL: abs_4h:1053; CHECK: // %bb.0:1054; CHECK-NEXT: ldr d0, [x0]1055; CHECK-NEXT: abs.4h v0, v01056; CHECK-NEXT: ret1057 %tmp1 = load <4 x i16>, ptr %A1058 %tmp3 = call <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16> %tmp1)1059 ret <4 x i16> %tmp31060}1061 1062define <8 x i16> @abs_8h(ptr %A) nounwind {1063; CHECK-LABEL: abs_8h:1064; CHECK: // %bb.0:1065; CHECK-NEXT: ldr q0, [x0]1066; CHECK-NEXT: abs.8h v0, v01067; CHECK-NEXT: ret1068 %tmp1 = load <8 x i16>, ptr %A1069 %tmp3 = call <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16> %tmp1)1070 ret <8 x i16> %tmp31071}1072 1073define <2 x i32> @abs_2s(ptr %A) nounwind {1074; CHECK-LABEL: abs_2s:1075; CHECK: // %bb.0:1076; CHECK-NEXT: ldr d0, [x0]1077; CHECK-NEXT: abs.2s v0, v01078; CHECK-NEXT: ret1079 %tmp1 = load <2 x i32>, ptr %A1080 %tmp3 = call <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32> %tmp1)1081 ret <2 x i32> %tmp31082}1083 1084define <4 x i32> @abs_4s(ptr %A) nounwind {1085; CHECK-LABEL: abs_4s:1086; CHECK: // %bb.0:1087; CHECK-NEXT: ldr q0, [x0]1088; CHECK-NEXT: abs.4s v0, v01089; CHECK-NEXT: ret1090 %tmp1 = load <4 x i32>, ptr %A1091 %tmp3 = call <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32> %tmp1)1092 ret <4 x i32> %tmp31093}1094 1095define <1 x i64> @abs_1d(<1 x i64> %A) nounwind {1096; CHECK-SD-LABEL: abs_1d:1097; CHECK-SD: // %bb.0:1098; CHECK-SD-NEXT: abs d0, d01099; CHECK-SD-NEXT: ret1100;1101; CHECK-GI-LABEL: abs_1d:1102; CHECK-GI: // %bb.0:1103; CHECK-GI-NEXT: fmov x8, d01104; CHECK-GI-NEXT: fmov x9, d01105; CHECK-GI-NEXT: neg x8, x81106; CHECK-GI-NEXT: cmp x9, #01107; CHECK-GI-NEXT: fmov d1, x81108; CHECK-GI-NEXT: fcsel d0, d0, d1, gt1109; CHECK-GI-NEXT: ret1110 %abs = call <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64> %A)1111 ret <1 x i64> %abs1112}1113 1114define i64 @abs_1d_honestly(i64 %A) nounwind {1115; CHECK-SD-LABEL: abs_1d_honestly:1116; CHECK-SD: // %bb.0:1117; CHECK-SD-NEXT: fmov d0, x01118; CHECK-SD-NEXT: abs d0, d01119; CHECK-SD-NEXT: fmov x0, d01120; CHECK-SD-NEXT: ret1121;1122; CHECK-GI-LABEL: abs_1d_honestly:1123; CHECK-GI: // %bb.0:1124; CHECK-GI-NEXT: cmp x0, #01125; CHECK-GI-NEXT: cneg x0, x0, le1126; CHECK-GI-NEXT: ret1127 %abs = call i64 @llvm.aarch64.neon.abs.i64(i64 %A)1128 ret i64 %abs1129}1130 1131declare <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8>) nounwind readnone1132declare <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8>) nounwind readnone1133declare <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16>) nounwind readnone1134declare <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16>) nounwind readnone1135declare <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32>) nounwind readnone1136declare <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32>) nounwind readnone1137declare <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64>) nounwind readnone1138declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone1139 1140define <8 x i16> @sabal8h(ptr %A, ptr %B, ptr %C) nounwind {1141; CHECK-LABEL: sabal8h:1142; CHECK: // %bb.0:1143; CHECK-NEXT: ldr d1, [x0]1144; CHECK-NEXT: ldr d2, [x1]1145; CHECK-NEXT: ldr q0, [x2]1146; CHECK-NEXT: sabal.8h v0, v1, v21147; CHECK-NEXT: ret1148 %tmp1 = load <8 x i8>, ptr %A1149 %tmp2 = load <8 x i8>, ptr %B1150 %tmp3 = load <8 x i16>, ptr %C1151 %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1152 %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>1153 %tmp5 = add <8 x i16> %tmp3, %tmp4.11154 ret <8 x i16> %tmp51155}1156 1157define <4 x i32> @sabal4s(ptr %A, ptr %B, ptr %C) nounwind {1158; CHECK-LABEL: sabal4s:1159; CHECK: // %bb.0:1160; CHECK-NEXT: ldr d1, [x0]1161; CHECK-NEXT: ldr d2, [x1]1162; CHECK-NEXT: ldr q0, [x2]1163; CHECK-NEXT: sabal.4s v0, v1, v21164; CHECK-NEXT: ret1165 %tmp1 = load <4 x i16>, ptr %A1166 %tmp2 = load <4 x i16>, ptr %B1167 %tmp3 = load <4 x i32>, ptr %C1168 %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1169 %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>1170 %tmp5 = add <4 x i32> %tmp3, %tmp4.11171 ret <4 x i32> %tmp51172}1173 1174define <2 x i64> @sabal2d(ptr %A, ptr %B, ptr %C) nounwind {1175; CHECK-LABEL: sabal2d:1176; CHECK: // %bb.0:1177; CHECK-NEXT: ldr d1, [x0]1178; CHECK-NEXT: ldr d2, [x1]1179; CHECK-NEXT: ldr q0, [x2]1180; CHECK-NEXT: sabal.2d v0, v1, v21181; CHECK-NEXT: ret1182 %tmp1 = load <2 x i32>, ptr %A1183 %tmp2 = load <2 x i32>, ptr %B1184 %tmp3 = load <2 x i64>, ptr %C1185 %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1186 %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>1187 %tmp4.1.1 = zext <2 x i32> %tmp4 to <2 x i64>1188 %tmp5 = add <2 x i64> %tmp3, %tmp4.11189 ret <2 x i64> %tmp51190}1191 1192define <8 x i16> @sabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {1193; CHECK-SD-LABEL: sabal2_8h:1194; CHECK-SD: // %bb.0:1195; CHECK-SD-NEXT: ldr q0, [x2]1196; CHECK-SD-NEXT: ldr d1, [x0, #8]1197; CHECK-SD-NEXT: ldr d2, [x1, #8]1198; CHECK-SD-NEXT: sabal.8h v0, v1, v21199; CHECK-SD-NEXT: ret1200;1201; CHECK-GI-LABEL: sabal2_8h:1202; CHECK-GI: // %bb.0:1203; CHECK-GI-NEXT: ldr q1, [x0]1204; CHECK-GI-NEXT: ldr q2, [x1]1205; CHECK-GI-NEXT: ldr q0, [x2]1206; CHECK-GI-NEXT: sabal2.8h v0, v1, v21207; CHECK-GI-NEXT: ret1208 %load1 = load <16 x i8>, ptr %A1209 %load2 = load <16 x i8>, ptr %B1210 %tmp3 = load <8 x i16>, ptr %C1211 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1212 %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1213 %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1214 %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>1215 %tmp5 = add <8 x i16> %tmp3, %tmp4.11216 ret <8 x i16> %tmp51217}1218 1219define <4 x i32> @sabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {1220; CHECK-SD-LABEL: sabal2_4s:1221; CHECK-SD: // %bb.0:1222; CHECK-SD-NEXT: ldr q0, [x2]1223; CHECK-SD-NEXT: ldr d1, [x0, #8]1224; CHECK-SD-NEXT: ldr d2, [x1, #8]1225; CHECK-SD-NEXT: sabal.4s v0, v1, v21226; CHECK-SD-NEXT: ret1227;1228; CHECK-GI-LABEL: sabal2_4s:1229; CHECK-GI: // %bb.0:1230; CHECK-GI-NEXT: ldr q1, [x0]1231; CHECK-GI-NEXT: ldr q2, [x1]1232; CHECK-GI-NEXT: ldr q0, [x2]1233; CHECK-GI-NEXT: sabal2.4s v0, v1, v21234; CHECK-GI-NEXT: ret1235 %load1 = load <8 x i16>, ptr %A1236 %load2 = load <8 x i16>, ptr %B1237 %tmp3 = load <4 x i32>, ptr %C1238 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1239 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1240 %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1241 %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>1242 %tmp5 = add <4 x i32> %tmp3, %tmp4.11243 ret <4 x i32> %tmp51244}1245 1246define <2 x i64> @sabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {1247; CHECK-SD-LABEL: sabal2_2d:1248; CHECK-SD: // %bb.0:1249; CHECK-SD-NEXT: ldr q0, [x2]1250; CHECK-SD-NEXT: ldr d1, [x0, #8]1251; CHECK-SD-NEXT: ldr d2, [x1, #8]1252; CHECK-SD-NEXT: sabal.2d v0, v1, v21253; CHECK-SD-NEXT: ret1254;1255; CHECK-GI-LABEL: sabal2_2d:1256; CHECK-GI: // %bb.0:1257; CHECK-GI-NEXT: ldr q1, [x0]1258; CHECK-GI-NEXT: ldr q2, [x1]1259; CHECK-GI-NEXT: ldr q0, [x2]1260; CHECK-GI-NEXT: sabal2.2d v0, v1, v21261; CHECK-GI-NEXT: ret1262 %load1 = load <4 x i32>, ptr %A1263 %load2 = load <4 x i32>, ptr %B1264 %tmp3 = load <2 x i64>, ptr %C1265 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1266 %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1267 %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1268 %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>1269 %tmp5 = add <2 x i64> %tmp3, %tmp4.11270 ret <2 x i64> %tmp51271}1272 1273define <8 x i16> @uabal8h(ptr %A, ptr %B, ptr %C) nounwind {1274; CHECK-LABEL: uabal8h:1275; CHECK: // %bb.0:1276; CHECK-NEXT: ldr d1, [x0]1277; CHECK-NEXT: ldr d2, [x1]1278; CHECK-NEXT: ldr q0, [x2]1279; CHECK-NEXT: uabal.8h v0, v1, v21280; CHECK-NEXT: ret1281 %tmp1 = load <8 x i8>, ptr %A1282 %tmp2 = load <8 x i8>, ptr %B1283 %tmp3 = load <8 x i16>, ptr %C1284 %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1285 %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>1286 %tmp5 = add <8 x i16> %tmp3, %tmp4.11287 ret <8 x i16> %tmp51288}1289 1290define <4 x i32> @uabal4s(ptr %A, ptr %B, ptr %C) nounwind {1291; CHECK-LABEL: uabal4s:1292; CHECK: // %bb.0:1293; CHECK-NEXT: ldr d1, [x0]1294; CHECK-NEXT: ldr d2, [x1]1295; CHECK-NEXT: ldr q0, [x2]1296; CHECK-NEXT: uabal.4s v0, v1, v21297; CHECK-NEXT: ret1298 %tmp1 = load <4 x i16>, ptr %A1299 %tmp2 = load <4 x i16>, ptr %B1300 %tmp3 = load <4 x i32>, ptr %C1301 %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1302 %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>1303 %tmp5 = add <4 x i32> %tmp3, %tmp4.11304 ret <4 x i32> %tmp51305}1306 1307define <2 x i64> @uabal2d(ptr %A, ptr %B, ptr %C) nounwind {1308; CHECK-LABEL: uabal2d:1309; CHECK: // %bb.0:1310; CHECK-NEXT: ldr d1, [x0]1311; CHECK-NEXT: ldr d2, [x1]1312; CHECK-NEXT: ldr q0, [x2]1313; CHECK-NEXT: uabal.2d v0, v1, v21314; CHECK-NEXT: ret1315 %tmp1 = load <2 x i32>, ptr %A1316 %tmp2 = load <2 x i32>, ptr %B1317 %tmp3 = load <2 x i64>, ptr %C1318 %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1319 %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>1320 %tmp5 = add <2 x i64> %tmp3, %tmp4.11321 ret <2 x i64> %tmp51322}1323 1324define <8 x i16> @uabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {1325; CHECK-SD-LABEL: uabal2_8h:1326; CHECK-SD: // %bb.0:1327; CHECK-SD-NEXT: ldr q0, [x2]1328; CHECK-SD-NEXT: ldr d1, [x0, #8]1329; CHECK-SD-NEXT: ldr d2, [x1, #8]1330; CHECK-SD-NEXT: uabal.8h v0, v1, v21331; CHECK-SD-NEXT: ret1332;1333; CHECK-GI-LABEL: uabal2_8h:1334; CHECK-GI: // %bb.0:1335; CHECK-GI-NEXT: ldr q1, [x0]1336; CHECK-GI-NEXT: ldr q2, [x1]1337; CHECK-GI-NEXT: ldr q0, [x2]1338; CHECK-GI-NEXT: uabal2.8h v0, v1, v21339; CHECK-GI-NEXT: ret1340 %load1 = load <16 x i8>, ptr %A1341 %load2 = load <16 x i8>, ptr %B1342 %tmp3 = load <8 x i16>, ptr %C1343 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1344 %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1345 %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1346 %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>1347 %tmp5 = add <8 x i16> %tmp3, %tmp4.11348 ret <8 x i16> %tmp51349}1350 1351define <4 x i32> @uabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {1352; CHECK-SD-LABEL: uabal2_4s:1353; CHECK-SD: // %bb.0:1354; CHECK-SD-NEXT: ldr q0, [x2]1355; CHECK-SD-NEXT: ldr d1, [x0, #8]1356; CHECK-SD-NEXT: ldr d2, [x1, #8]1357; CHECK-SD-NEXT: uabal.4s v0, v1, v21358; CHECK-SD-NEXT: ret1359;1360; CHECK-GI-LABEL: uabal2_4s:1361; CHECK-GI: // %bb.0:1362; CHECK-GI-NEXT: ldr q1, [x0]1363; CHECK-GI-NEXT: ldr q2, [x1]1364; CHECK-GI-NEXT: ldr q0, [x2]1365; CHECK-GI-NEXT: uabal2.4s v0, v1, v21366; CHECK-GI-NEXT: ret1367 %load1 = load <8 x i16>, ptr %A1368 %load2 = load <8 x i16>, ptr %B1369 %tmp3 = load <4 x i32>, ptr %C1370 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1371 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1372 %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1373 %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>1374 %tmp5 = add <4 x i32> %tmp3, %tmp4.11375 ret <4 x i32> %tmp51376}1377 1378define <2 x i64> @uabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {1379; CHECK-SD-LABEL: uabal2_2d:1380; CHECK-SD: // %bb.0:1381; CHECK-SD-NEXT: ldr q0, [x2]1382; CHECK-SD-NEXT: ldr d1, [x0, #8]1383; CHECK-SD-NEXT: ldr d2, [x1, #8]1384; CHECK-SD-NEXT: uabal.2d v0, v1, v21385; CHECK-SD-NEXT: ret1386;1387; CHECK-GI-LABEL: uabal2_2d:1388; CHECK-GI: // %bb.0:1389; CHECK-GI-NEXT: ldr q1, [x0]1390; CHECK-GI-NEXT: ldr q2, [x1]1391; CHECK-GI-NEXT: ldr q0, [x2]1392; CHECK-GI-NEXT: uabal2.2d v0, v1, v21393; CHECK-GI-NEXT: ret1394 %load1 = load <4 x i32>, ptr %A1395 %load2 = load <4 x i32>, ptr %B1396 %tmp3 = load <2 x i64>, ptr %C1397 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1398 %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1399 %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1400 %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>1401 %tmp5 = add <2 x i64> %tmp3, %tmp4.11402 ret <2 x i64> %tmp51403}1404 1405define <8 x i8> @saba_8b(ptr %A, ptr %B, ptr %C) nounwind {1406; CHECK-LABEL: saba_8b:1407; CHECK: // %bb.0:1408; CHECK-NEXT: ldr d1, [x0]1409; CHECK-NEXT: ldr d2, [x1]1410; CHECK-NEXT: ldr d0, [x2]1411; CHECK-NEXT: saba.8b v0, v1, v21412; CHECK-NEXT: ret1413 %tmp1 = load <8 x i8>, ptr %A1414 %tmp2 = load <8 x i8>, ptr %B1415 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1416 %tmp4 = load <8 x i8>, ptr %C1417 %tmp5 = add <8 x i8> %tmp3, %tmp41418 ret <8 x i8> %tmp51419}1420 1421define <16 x i8> @saba_16b(ptr %A, ptr %B, ptr %C) nounwind {1422; CHECK-LABEL: saba_16b:1423; CHECK: // %bb.0:1424; CHECK-NEXT: ldr q1, [x0]1425; CHECK-NEXT: ldr q2, [x1]1426; CHECK-NEXT: ldr q0, [x2]1427; CHECK-NEXT: saba.16b v0, v1, v21428; CHECK-NEXT: ret1429 %tmp1 = load <16 x i8>, ptr %A1430 %tmp2 = load <16 x i8>, ptr %B1431 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)1432 %tmp4 = load <16 x i8>, ptr %C1433 %tmp5 = add <16 x i8> %tmp3, %tmp41434 ret <16 x i8> %tmp51435}1436 1437define <4 x i16> @saba_4h(ptr %A, ptr %B, ptr %C) nounwind {1438; CHECK-LABEL: saba_4h:1439; CHECK: // %bb.0:1440; CHECK-NEXT: ldr d1, [x0]1441; CHECK-NEXT: ldr d2, [x1]1442; CHECK-NEXT: ldr d0, [x2]1443; CHECK-NEXT: saba.4h v0, v1, v21444; CHECK-NEXT: ret1445 %tmp1 = load <4 x i16>, ptr %A1446 %tmp2 = load <4 x i16>, ptr %B1447 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1448 %tmp4 = load <4 x i16>, ptr %C1449 %tmp5 = add <4 x i16> %tmp3, %tmp41450 ret <4 x i16> %tmp51451}1452 1453define <8 x i16> @saba_8h(ptr %A, ptr %B, ptr %C) nounwind {1454; CHECK-LABEL: saba_8h:1455; CHECK: // %bb.0:1456; CHECK-NEXT: ldr q1, [x0]1457; CHECK-NEXT: ldr q2, [x1]1458; CHECK-NEXT: ldr q0, [x2]1459; CHECK-NEXT: saba.8h v0, v1, v21460; CHECK-NEXT: ret1461 %tmp1 = load <8 x i16>, ptr %A1462 %tmp2 = load <8 x i16>, ptr %B1463 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)1464 %tmp4 = load <8 x i16>, ptr %C1465 %tmp5 = add <8 x i16> %tmp3, %tmp41466 ret <8 x i16> %tmp51467}1468 1469define <2 x i32> @saba_2s(ptr %A, ptr %B, ptr %C) nounwind {1470; CHECK-LABEL: saba_2s:1471; CHECK: // %bb.0:1472; CHECK-NEXT: ldr d1, [x0]1473; CHECK-NEXT: ldr d2, [x1]1474; CHECK-NEXT: ldr d0, [x2]1475; CHECK-NEXT: saba.2s v0, v1, v21476; CHECK-NEXT: ret1477 %tmp1 = load <2 x i32>, ptr %A1478 %tmp2 = load <2 x i32>, ptr %B1479 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1480 %tmp4 = load <2 x i32>, ptr %C1481 %tmp5 = add <2 x i32> %tmp3, %tmp41482 ret <2 x i32> %tmp51483}1484 1485define <4 x i32> @saba_4s(ptr %A, ptr %B, ptr %C) nounwind {1486; CHECK-LABEL: saba_4s:1487; CHECK: // %bb.0:1488; CHECK-NEXT: ldr q1, [x0]1489; CHECK-NEXT: ldr q2, [x1]1490; CHECK-NEXT: ldr q0, [x2]1491; CHECK-NEXT: saba.4s v0, v1, v21492; CHECK-NEXT: ret1493 %tmp1 = load <4 x i32>, ptr %A1494 %tmp2 = load <4 x i32>, ptr %B1495 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)1496 %tmp4 = load <4 x i32>, ptr %C1497 %tmp5 = add <4 x i32> %tmp3, %tmp41498 ret <4 x i32> %tmp51499}1500 1501define <8 x i8> @uaba_8b(ptr %A, ptr %B, ptr %C) nounwind {1502; CHECK-LABEL: uaba_8b:1503; CHECK: // %bb.0:1504; CHECK-NEXT: ldr d1, [x0]1505; CHECK-NEXT: ldr d2, [x1]1506; CHECK-NEXT: ldr d0, [x2]1507; CHECK-NEXT: uaba.8b v0, v1, v21508; CHECK-NEXT: ret1509 %tmp1 = load <8 x i8>, ptr %A1510 %tmp2 = load <8 x i8>, ptr %B1511 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1512 %tmp4 = load <8 x i8>, ptr %C1513 %tmp5 = add <8 x i8> %tmp3, %tmp41514 ret <8 x i8> %tmp51515}1516 1517define <16 x i8> @uaba_16b(ptr %A, ptr %B, ptr %C) nounwind {1518; CHECK-LABEL: uaba_16b:1519; CHECK: // %bb.0:1520; CHECK-NEXT: ldr q1, [x0]1521; CHECK-NEXT: ldr q2, [x1]1522; CHECK-NEXT: ldr q0, [x2]1523; CHECK-NEXT: uaba.16b v0, v1, v21524; CHECK-NEXT: ret1525 %tmp1 = load <16 x i8>, ptr %A1526 %tmp2 = load <16 x i8>, ptr %B1527 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)1528 %tmp4 = load <16 x i8>, ptr %C1529 %tmp5 = add <16 x i8> %tmp3, %tmp41530 ret <16 x i8> %tmp51531}1532 1533define <4 x i16> @uaba_4h(ptr %A, ptr %B, ptr %C) nounwind {1534; CHECK-LABEL: uaba_4h:1535; CHECK: // %bb.0:1536; CHECK-NEXT: ldr d1, [x0]1537; CHECK-NEXT: ldr d2, [x1]1538; CHECK-NEXT: ldr d0, [x2]1539; CHECK-NEXT: uaba.4h v0, v1, v21540; CHECK-NEXT: ret1541 %tmp1 = load <4 x i16>, ptr %A1542 %tmp2 = load <4 x i16>, ptr %B1543 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1544 %tmp4 = load <4 x i16>, ptr %C1545 %tmp5 = add <4 x i16> %tmp3, %tmp41546 ret <4 x i16> %tmp51547}1548 1549define <8 x i16> @uaba_8h(ptr %A, ptr %B, ptr %C) nounwind {1550; CHECK-LABEL: uaba_8h:1551; CHECK: // %bb.0:1552; CHECK-NEXT: ldr q1, [x0]1553; CHECK-NEXT: ldr q2, [x1]1554; CHECK-NEXT: ldr q0, [x2]1555; CHECK-NEXT: uaba.8h v0, v1, v21556; CHECK-NEXT: ret1557 %tmp1 = load <8 x i16>, ptr %A1558 %tmp2 = load <8 x i16>, ptr %B1559 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)1560 %tmp4 = load <8 x i16>, ptr %C1561 %tmp5 = add <8 x i16> %tmp3, %tmp41562 ret <8 x i16> %tmp51563}1564 1565define <2 x i32> @uaba_2s(ptr %A, ptr %B, ptr %C) nounwind {1566; CHECK-LABEL: uaba_2s:1567; CHECK: // %bb.0:1568; CHECK-NEXT: ldr d1, [x0]1569; CHECK-NEXT: ldr d2, [x1]1570; CHECK-NEXT: ldr d0, [x2]1571; CHECK-NEXT: uaba.2s v0, v1, v21572; CHECK-NEXT: ret1573 %tmp1 = load <2 x i32>, ptr %A1574 %tmp2 = load <2 x i32>, ptr %B1575 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1576 %tmp4 = load <2 x i32>, ptr %C1577 %tmp5 = add <2 x i32> %tmp3, %tmp41578 ret <2 x i32> %tmp51579}1580 1581define <4 x i32> @uaba_4s(ptr %A, ptr %B, ptr %C) nounwind {1582; CHECK-LABEL: uaba_4s:1583; CHECK: // %bb.0:1584; CHECK-NEXT: ldr q1, [x0]1585; CHECK-NEXT: ldr q2, [x1]1586; CHECK-NEXT: ldr q0, [x2]1587; CHECK-NEXT: uaba.4s v0, v1, v21588; CHECK-NEXT: ret1589 %tmp1 = load <4 x i32>, ptr %A1590 %tmp2 = load <4 x i32>, ptr %B1591 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)1592 %tmp4 = load <4 x i32>, ptr %C1593 %tmp5 = add <4 x i32> %tmp3, %tmp41594 ret <4 x i32> %tmp51595}1596 1597; Scalar FABD1598define float @fabds(float %a, float %b) nounwind {1599; CHECK-LABEL: fabds:1600; CHECK: // %bb.0:1601; CHECK-NEXT: fabd s0, s0, s11602; CHECK-NEXT: ret1603 %vabd.i = tail call float @llvm.aarch64.sisd.fabd.f32(float %a, float %b) nounwind1604 ret float %vabd.i1605}1606 1607define double @fabdd(double %a, double %b) nounwind {1608; CHECK-LABEL: fabdd:1609; CHECK: // %bb.0:1610; CHECK-NEXT: fabd d0, d0, d11611; CHECK-NEXT: ret1612 %vabd.i = tail call double @llvm.aarch64.sisd.fabd.f64(double %a, double %b) nounwind1613 ret double %vabd.i1614}1615 1616declare double @llvm.aarch64.sisd.fabd.f64(double, double) nounwind readnone1617declare float @llvm.aarch64.sisd.fabd.f32(float, float) nounwind readnone1618 1619define float @fabds_from_fsub_fabs(float %a, float %b) nounwind {1620; CHECK-LABEL: fabds_from_fsub_fabs:1621; CHECK: // %bb.0:1622; CHECK-NEXT: fabd s0, s0, s11623; CHECK-NEXT: ret1624 %sub = fsub float %a, %b1625 %abs = tail call float @llvm.fabs.f32(float %sub)1626 ret float %abs1627}1628 1629define double @fabdd_from_fsub_fabs(double %a, double %b) nounwind {1630; CHECK-LABEL: fabdd_from_fsub_fabs:1631; CHECK: // %bb.0:1632; CHECK-NEXT: fabd d0, d0, d11633; CHECK-NEXT: ret1634 %sub = fsub double %a, %b1635 %abs = tail call double @llvm.fabs.f64(double %sub)1636 ret double %abs1637}1638 1639declare float @llvm.fabs.f32(float) nounwind readnone1640declare double @llvm.fabs.f64(double) nounwind readnone1641 1642define <2 x i64> @uabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {1643; CHECK-LABEL: uabdl_from_extract_dup:1644; CHECK: // %bb.0:1645; CHECK-NEXT: dup.2s v1, w01646; CHECK-NEXT: uabdl.2d v0, v0, v11647; CHECK-NEXT: ret1648 %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 01649 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 11650 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>1651 %res = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind1652 %res1 = zext <2 x i32> %res to <2 x i64>1653 ret <2 x i64> %res11654}1655 1656define <2 x i64> @uabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {1657; CHECK-SD-LABEL: uabdl2_from_extract_dup:1658; CHECK-SD: // %bb.0:1659; CHECK-SD-NEXT: dup.4s v1, w01660; CHECK-SD-NEXT: uabdl2.2d v0, v0, v11661; CHECK-SD-NEXT: ret1662;1663; CHECK-GI-LABEL: uabdl2_from_extract_dup:1664; CHECK-GI: // %bb.0:1665; CHECK-GI-NEXT: dup.2s v1, w01666; CHECK-GI-NEXT: mov d0, v0[1]1667; CHECK-GI-NEXT: uabdl.2d v0, v0, v11668; CHECK-GI-NEXT: ret1669 %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 01670 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 11671 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1672 %res = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind1673 %res1 = zext <2 x i32> %res to <2 x i64>1674 ret <2 x i64> %res11675}1676 1677define <2 x i64> @sabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {1678; CHECK-LABEL: sabdl_from_extract_dup:1679; CHECK: // %bb.0:1680; CHECK-NEXT: dup.2s v1, w01681; CHECK-NEXT: sabdl.2d v0, v0, v11682; CHECK-NEXT: ret1683 %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 01684 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 11685 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>1686 %res = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind1687 %res1 = zext <2 x i32> %res to <2 x i64>1688 ret <2 x i64> %res11689}1690 1691define <2 x i64> @sabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {1692; CHECK-SD-LABEL: sabdl2_from_extract_dup:1693; CHECK-SD: // %bb.0:1694; CHECK-SD-NEXT: dup.4s v1, w01695; CHECK-SD-NEXT: sabdl2.2d v0, v0, v11696; CHECK-SD-NEXT: ret1697;1698; CHECK-GI-LABEL: sabdl2_from_extract_dup:1699; CHECK-GI: // %bb.0:1700; CHECK-GI-NEXT: dup.2s v1, w01701; CHECK-GI-NEXT: mov d0, v0[1]1702; CHECK-GI-NEXT: sabdl.2d v0, v0, v11703; CHECK-GI-NEXT: ret1704 %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 01705 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 11706 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1707 %res = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind1708 %res1 = zext <2 x i32> %res to <2 x i64>1709 ret <2 x i64> %res11710}1711 1712define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {1713; CHECK-SD-LABEL: abspattern1:1714; CHECK-SD: // %bb.0:1715; CHECK-SD-NEXT: abs.2s v0, v01716; CHECK-SD-NEXT: ret1717;1718; CHECK-GI-LABEL: abspattern1:1719; CHECK-GI: // %bb.0:1720; CHECK-GI-NEXT: neg.2s v1, v01721; CHECK-GI-NEXT: cmge.2s v2, v0, #01722; CHECK-GI-NEXT: bif.8b v0, v1, v21723; CHECK-GI-NEXT: ret1724 %tmp1neg = sub <2 x i32> zeroinitializer, %a1725 %b = icmp sge <2 x i32> %a, zeroinitializer1726 %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg1727 ret <2 x i32> %abs1728}1729 1730; For GlobalISel, this generates terrible code until we can pattern match this to abs.1731define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {1732; CHECK-SD-LABEL: abspattern2:1733; CHECK-SD: // %bb.0:1734; CHECK-SD-NEXT: abs.4h v0, v01735; CHECK-SD-NEXT: ret1736;1737; CHECK-GI-LABEL: abspattern2:1738; CHECK-GI: // %bb.0:1739; CHECK-GI-NEXT: neg.4h v1, v01740; CHECK-GI-NEXT: cmgt.4h v2, v0, #01741; CHECK-GI-NEXT: bif.8b v0, v1, v21742; CHECK-GI-NEXT: ret1743 %tmp1neg = sub <4 x i16> zeroinitializer, %a1744 %b = icmp sgt <4 x i16> %a, zeroinitializer1745 %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg1746 ret <4 x i16> %abs1747}1748 1749define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {1750; CHECK-SD-LABEL: abspattern3:1751; CHECK-SD: // %bb.0:1752; CHECK-SD-NEXT: abs.8b v0, v01753; CHECK-SD-NEXT: ret1754;1755; CHECK-GI-LABEL: abspattern3:1756; CHECK-GI: // %bb.0:1757; CHECK-GI-NEXT: neg.8b v1, v01758; CHECK-GI-NEXT: cmlt.8b v2, v0, #01759; CHECK-GI-NEXT: bit.8b v0, v1, v21760; CHECK-GI-NEXT: ret1761 %tmp1neg = sub <8 x i8> zeroinitializer, %a1762 %b = icmp slt <8 x i8> %a, zeroinitializer1763 %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a1764 ret <8 x i8> %abs1765}1766 1767define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {1768; CHECK-SD-LABEL: abspattern4:1769; CHECK-SD: // %bb.0:1770; CHECK-SD-NEXT: abs.4s v0, v01771; CHECK-SD-NEXT: ret1772;1773; CHECK-GI-LABEL: abspattern4:1774; CHECK-GI: // %bb.0:1775; CHECK-GI-NEXT: neg.4s v1, v01776; CHECK-GI-NEXT: cmge.4s v2, v0, #01777; CHECK-GI-NEXT: bif.16b v0, v1, v21778; CHECK-GI-NEXT: ret1779 %tmp1neg = sub <4 x i32> zeroinitializer, %a1780 %b = icmp sge <4 x i32> %a, zeroinitializer1781 %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg1782 ret <4 x i32> %abs1783}1784 1785define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {1786; CHECK-SD-LABEL: abspattern5:1787; CHECK-SD: // %bb.0:1788; CHECK-SD-NEXT: abs.8h v0, v01789; CHECK-SD-NEXT: ret1790;1791; CHECK-GI-LABEL: abspattern5:1792; CHECK-GI: // %bb.0:1793; CHECK-GI-NEXT: neg.8h v1, v01794; CHECK-GI-NEXT: cmgt.8h v2, v0, #01795; CHECK-GI-NEXT: bif.16b v0, v1, v21796; CHECK-GI-NEXT: ret1797 %tmp1neg = sub <8 x i16> zeroinitializer, %a1798 %b = icmp sgt <8 x i16> %a, zeroinitializer1799 %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg1800 ret <8 x i16> %abs1801}1802 1803define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {1804; CHECK-SD-LABEL: abspattern6:1805; CHECK-SD: // %bb.0:1806; CHECK-SD-NEXT: abs.16b v0, v01807; CHECK-SD-NEXT: ret1808;1809; CHECK-GI-LABEL: abspattern6:1810; CHECK-GI: // %bb.0:1811; CHECK-GI-NEXT: neg.16b v1, v01812; CHECK-GI-NEXT: cmlt.16b v2, v0, #01813; CHECK-GI-NEXT: bit.16b v0, v1, v21814; CHECK-GI-NEXT: ret1815 %tmp1neg = sub <16 x i8> zeroinitializer, %a1816 %b = icmp slt <16 x i8> %a, zeroinitializer1817 %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a1818 ret <16 x i8> %abs1819}1820 1821define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {1822; CHECK-SD-LABEL: abspattern7:1823; CHECK-SD: // %bb.0:1824; CHECK-SD-NEXT: abs.2d v0, v01825; CHECK-SD-NEXT: ret1826;1827; CHECK-GI-LABEL: abspattern7:1828; CHECK-GI: // %bb.0:1829; CHECK-GI-NEXT: neg.2d v1, v01830; CHECK-GI-NEXT: cmle.2d v2, v0, #01831; CHECK-GI-NEXT: bit.16b v0, v1, v21832; CHECK-GI-NEXT: ret1833 %tmp1neg = sub <2 x i64> zeroinitializer, %a1834 %b = icmp sle <2 x i64> %a, zeroinitializer1835 %abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a1836 ret <2 x i64> %abs1837}1838 1839define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {1840; CHECK-SD-LABEL: uabd_i32:1841; CHECK-SD: // %bb.0:1842; CHECK-SD-NEXT: sabdl.2d v0, v0, v11843; CHECK-SD-NEXT: ret1844;1845; CHECK-GI-LABEL: uabd_i32:1846; CHECK-GI: // %bb.0:1847; CHECK-GI-NEXT: ssubl.2d v0, v0, v11848; CHECK-GI-NEXT: cmlt.2d v1, v0, #01849; CHECK-GI-NEXT: neg.2d v2, v01850; CHECK-GI-NEXT: bit.16b v0, v2, v11851; CHECK-GI-NEXT: ret1852 %aext = sext <2 x i32> %a to <2 x i64>1853 %bext = sext <2 x i32> %b to <2 x i64>1854 %abdiff = sub nsw <2 x i64> %aext, %bext1855 %abcmp = icmp slt <2 x i64> %abdiff, zeroinitializer1856 %ababs = sub nsw <2 x i64> zeroinitializer, %abdiff1857 %absel = select <2 x i1> %abcmp, <2 x i64> %ababs, <2 x i64> %abdiff1858 ret <2 x i64> %absel1859}1860 1861define <2 x i128> @uabd_i64(<2 x i64> %a, <2 x i64> %b) {1862; CHECK-SD-LABEL: uabd_i64:1863; CHECK-SD: // %bb.0:1864; CHECK-SD-NEXT: cmgt.2d v2, v0, v11865; CHECK-SD-NEXT: sub.2d v0, v0, v11866; CHECK-SD-NEXT: mov x1, xzr1867; CHECK-SD-NEXT: mov x3, xzr1868; CHECK-SD-NEXT: eor.16b v0, v0, v21869; CHECK-SD-NEXT: sub.2d v0, v2, v01870; CHECK-SD-NEXT: mov.d x2, v0[1]1871; CHECK-SD-NEXT: fmov x0, d01872; CHECK-SD-NEXT: ret1873;1874; CHECK-GI-LABEL: uabd_i64:1875; CHECK-GI: // %bb.0:1876; CHECK-GI-NEXT: mov d2, v0[1]1877; CHECK-GI-NEXT: mov d3, v1[1]1878; CHECK-GI-NEXT: fmov x8, d01879; CHECK-GI-NEXT: fmov x10, d11880; CHECK-GI-NEXT: asr x9, x8, #631881; CHECK-GI-NEXT: fmov x11, d21882; CHECK-GI-NEXT: fmov x13, d31883; CHECK-GI-NEXT: asr x12, x10, #631884; CHECK-GI-NEXT: subs x8, x8, x101885; CHECK-GI-NEXT: sbc x9, x9, x121886; CHECK-GI-NEXT: asr x14, x11, #631887; CHECK-GI-NEXT: asr x15, x13, #631888; CHECK-GI-NEXT: subs x10, x11, x131889; CHECK-GI-NEXT: sbc x11, x14, x151890; CHECK-GI-NEXT: cmp x9, #01891; CHECK-GI-NEXT: cset w12, mi1892; CHECK-GI-NEXT: csel w12, wzr, w12, eq1893; CHECK-GI-NEXT: cmp x11, #01894; CHECK-GI-NEXT: cset w13, mi1895; CHECK-GI-NEXT: csel w13, wzr, w13, eq1896; CHECK-GI-NEXT: negs x14, x81897; CHECK-GI-NEXT: ngc x15, x91898; CHECK-GI-NEXT: negs x16, x101899; CHECK-GI-NEXT: ngc x17, x111900; CHECK-GI-NEXT: tst w12, #0x11901; CHECK-GI-NEXT: csel x0, x14, x8, ne1902; CHECK-GI-NEXT: csel x1, x15, x9, ne1903; CHECK-GI-NEXT: tst w13, #0x11904; CHECK-GI-NEXT: csel x2, x16, x10, ne1905; CHECK-GI-NEXT: csel x3, x17, x11, ne1906; CHECK-GI-NEXT: ret1907 %aext = sext <2 x i64> %a to <2 x i128>1908 %bext = sext <2 x i64> %b to <2 x i128>1909 %abdiff = sub nsw <2 x i128> %aext, %bext1910 %abcmp = icmp slt <2 x i128> %abdiff, zeroinitializer1911 %ababs = sub nsw <2 x i128> zeroinitializer, %abdiff1912 %absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff1913 ret <2 x i128> %absel1914}1915 1916define <8 x i16> @pr88784(<8 x i8> %l0, <8 x i8> %l1, <8 x i16> %l2) {1917; CHECK-LABEL: pr88784:1918; CHECK: // %bb.0:1919; CHECK-NEXT: usubl.8h v0, v0, v11920; CHECK-NEXT: cmlt.8h v1, v2, #01921; CHECK-NEXT: ssra.8h v0, v2, #151922; CHECK-NEXT: eor.16b v0, v1, v01923; CHECK-NEXT: ret1924 %l4 = zext <8 x i8> %l0 to <8 x i16>1925 %l5 = ashr <8 x i16> %l2, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>1926 %l6 = zext <8 x i8> %l1 to <8 x i16>1927 %l7 = sub <8 x i16> %l4, %l61928 %l8 = add <8 x i16> %l5, %l71929 %l9 = xor <8 x i16> %l5, %l81930 ret <8 x i16> %l91931}1932 1933define <8 x i16> @pr88784_fixed(<8 x i8> %l0, <8 x i8> %l1, <8 x i16> %l2) {1934; CHECK-SD-LABEL: pr88784_fixed:1935; CHECK-SD: // %bb.0:1936; CHECK-SD-NEXT: uabdl.8h v0, v0, v11937; CHECK-SD-NEXT: ret1938;1939; CHECK-GI-LABEL: pr88784_fixed:1940; CHECK-GI: // %bb.0:1941; CHECK-GI-NEXT: usubl.8h v0, v0, v11942; CHECK-GI-NEXT: cmlt.8h v1, v0, #01943; CHECK-GI-NEXT: ssra.8h v0, v0, #151944; CHECK-GI-NEXT: eor.16b v0, v1, v01945; CHECK-GI-NEXT: ret1946 %l4 = zext <8 x i8> %l0 to <8 x i16>1947 %l6 = zext <8 x i8> %l1 to <8 x i16>1948 %l7 = sub <8 x i16> %l4, %l61949 %l5 = ashr <8 x i16> %l7, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>1950 %l8 = add <8 x i16> %l5, %l71951 %l9 = xor <8 x i16> %l5, %l81952 ret <8 x i16> %l91953}1954 1955