90 lines · plain
1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s2 3define <8 x i8> @rbit_8b(ptr %A) nounwind {4;CHECK-LABEL: rbit_8b:5;CHECK: rbit.8b6 %tmp1 = load <8 x i8>, ptr %A7 %tmp3 = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %tmp1)8 ret <8 x i8> %tmp39}10 11define <16 x i8> @rbit_16b(ptr %A) nounwind {12;CHECK-LABEL: rbit_16b:13;CHECK: rbit.16b14 %tmp1 = load <16 x i8>, ptr %A15 %tmp3 = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %tmp1)16 ret <16 x i8> %tmp317}18 19declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) nounwind readnone20declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>) nounwind readnone21 22define <8 x i16> @sxtl8h(ptr %A) nounwind {23;CHECK-LABEL: sxtl8h:24;CHECK: sshll.8h25 %tmp1 = load <8 x i8>, ptr %A26 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>27 ret <8 x i16> %tmp228}29 30define <8 x i16> @uxtl8h(ptr %A) nounwind {31;CHECK-LABEL: uxtl8h:32;CHECK: ushll.8h33 %tmp1 = load <8 x i8>, ptr %A34 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>35 ret <8 x i16> %tmp236}37 38define <4 x i32> @sxtl4s(ptr %A) nounwind {39;CHECK-LABEL: sxtl4s:40;CHECK: sshll.4s41 %tmp1 = load <4 x i16>, ptr %A42 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>43 ret <4 x i32> %tmp244}45 46define <4 x i32> @uxtl4s(ptr %A) nounwind {47;CHECK-LABEL: uxtl4s:48;CHECK: ushll.4s49 %tmp1 = load <4 x i16>, ptr %A50 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>51 ret <4 x i32> %tmp252}53 54define <2 x i64> @sxtl2d(ptr %A) nounwind {55;CHECK-LABEL: sxtl2d:56;CHECK: sshll.2d57 %tmp1 = load <2 x i32>, ptr %A58 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>59 ret <2 x i64> %tmp260}61 62define <2 x i64> @uxtl2d(ptr %A) nounwind {63;CHECK-LABEL: uxtl2d:64;CHECK: ushll.2d65 %tmp1 = load <2 x i32>, ptr %A66 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>67 ret <2 x i64> %tmp268}69 70; Check for incorrect use of vector bic.71; rdar://1155385972define void @test_vsliq(ptr nocapture %src, ptr nocapture %dest) nounwind noinline ssp {73entry:74; CHECK-LABEL: test_vsliq:75; CHECK-NOT: bic76; CHECK: movi.2d [[REG1:v[0-9]+]], #0x0000ff000000ff77; CHECK: and.16b v{{[0-9]+}}, v{{[0-9]+}}, [[REG1]]78 %0 = load <16 x i8>, ptr %src, align 1679 %and.i = and <16 x i8> %0, <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>80 %1 = bitcast <16 x i8> %and.i to <8 x i16>81 %vshl_n = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>82 %2 = or <8 x i16> %1, %vshl_n83 %3 = bitcast <8 x i16> %2 to <4 x i32>84 %vshl_n8 = shl <4 x i32> %3, <i32 16, i32 16, i32 16, i32 16>85 %4 = or <4 x i32> %3, %vshl_n886 %5 = bitcast <4 x i32> %4 to <16 x i8>87 store <16 x i8> %5, ptr %dest, align 1688 ret void89}90