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1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s2 3 4define void @fcmltz_4s(<4 x float> %a, ptr %p) nounwind {5;CHECK-LABEL: fcmltz_4s:6;CHECK: fcmlt.4s [[REG:v[0-9]+]], v0, #07;CHECK-NEXT: xtn.4h v[[REG_1:[0-9]+]], [[REG]]8;CHECK-NEXT: str d[[REG_1]], [x0]9;CHECK-NEXT: ret10 %tmp = fcmp olt <4 x float> %a, zeroinitializer11 %tmp2 = sext <4 x i1> %tmp to <4 x i16>12 store <4 x i16> %tmp2, ptr %p, align 813 ret void14}15 16define <2 x i32> @facge_2s(ptr %A, ptr %B) nounwind {17;CHECK-LABEL: facge_2s:18;CHECK: facge.2s19 %tmp1 = load <2 x float>, ptr %A20 %tmp2 = load <2 x float>, ptr %B21 %tmp3 = call <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)22 ret <2 x i32> %tmp323}24 25define <4 x i32> @facge_4s(ptr %A, ptr %B) nounwind {26;CHECK-LABEL: facge_4s:27;CHECK: facge.4s28 %tmp1 = load <4 x float>, ptr %A29 %tmp2 = load <4 x float>, ptr %B30 %tmp3 = call <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)31 ret <4 x i32> %tmp332}33 34define <2 x i64> @facge_2d(ptr %A, ptr %B) nounwind {35;CHECK-LABEL: facge_2d:36;CHECK: facge.2d37 %tmp1 = load <2 x double>, ptr %A38 %tmp2 = load <2 x double>, ptr %B39 %tmp3 = call <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)40 ret <2 x i64> %tmp341}42 43declare <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone44declare <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone45declare <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone46 47define <2 x i32> @facgt_2s(ptr %A, ptr %B) nounwind {48;CHECK-LABEL: facgt_2s:49;CHECK: facgt.2s50 %tmp1 = load <2 x float>, ptr %A51 %tmp2 = load <2 x float>, ptr %B52 %tmp3 = call <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)53 ret <2 x i32> %tmp354}55 56define <4 x i32> @facgt_4s(ptr %A, ptr %B) nounwind {57;CHECK-LABEL: facgt_4s:58;CHECK: facgt.4s59 %tmp1 = load <4 x float>, ptr %A60 %tmp2 = load <4 x float>, ptr %B61 %tmp3 = call <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)62 ret <4 x i32> %tmp363}64 65define <2 x i64> @facgt_2d(ptr %A, ptr %B) nounwind {66;CHECK-LABEL: facgt_2d:67;CHECK: facgt.2d68 %tmp1 = load <2 x double>, ptr %A69 %tmp2 = load <2 x double>, ptr %B70 %tmp3 = call <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)71 ret <2 x i64> %tmp372}73 74declare <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone75declare <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone76declare <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone77 78define i32 @facge_s(float %A, float %B) nounwind {79; CHECK-LABEL: facge_s:80; CHECK: facge {{s[0-9]+}}, s0, s181 %mask = call i32 @llvm.aarch64.neon.facge.i32.f32(float %A, float %B)82 ret i32 %mask83}84 85define i64 @facge_d(double %A, double %B) nounwind {86; CHECK-LABEL: facge_d:87; CHECK: facge {{d[0-9]+}}, d0, d188 %mask = call i64 @llvm.aarch64.neon.facge.i64.f64(double %A, double %B)89 ret i64 %mask90}91 92declare i64 @llvm.aarch64.neon.facge.i64.f64(double, double)93declare i32 @llvm.aarch64.neon.facge.i32.f32(float, float)94 95define i32 @facgt_s(float %A, float %B) nounwind {96; CHECK-LABEL: facgt_s:97; CHECK: facgt {{s[0-9]+}}, s0, s198 %mask = call i32 @llvm.aarch64.neon.facgt.i32.f32(float %A, float %B)99 ret i32 %mask100}101 102define i64 @facgt_d(double %A, double %B) nounwind {103; CHECK-LABEL: facgt_d:104; CHECK: facgt {{d[0-9]+}}, d0, d1105 %mask = call i64 @llvm.aarch64.neon.facgt.i64.f64(double %A, double %B)106 ret i64 %mask107}108 109declare i64 @llvm.aarch64.neon.facgt.i64.f64(double, double)110declare i32 @llvm.aarch64.neon.facgt.i32.f32(float, float)111 112define <8 x i8> @cmtst_8b(ptr %A, ptr %B) nounwind {113;CHECK-LABEL: cmtst_8b:114;CHECK: cmtst.8b115 %tmp1 = load <8 x i8>, ptr %A116 %tmp2 = load <8 x i8>, ptr %B117 %commonbits = and <8 x i8> %tmp1, %tmp2118 %mask = icmp ne <8 x i8> %commonbits, zeroinitializer119 %res = sext <8 x i1> %mask to <8 x i8>120 ret <8 x i8> %res121}122 123define <16 x i8> @cmtst_16b(ptr %A, ptr %B) nounwind {124;CHECK-LABEL: cmtst_16b:125;CHECK: cmtst.16b126 %tmp1 = load <16 x i8>, ptr %A127 %tmp2 = load <16 x i8>, ptr %B128 %commonbits = and <16 x i8> %tmp1, %tmp2129 %mask = icmp ne <16 x i8> %commonbits, zeroinitializer130 %res = sext <16 x i1> %mask to <16 x i8>131 ret <16 x i8> %res132}133 134define <4 x i16> @cmtst_4h(ptr %A, ptr %B) nounwind {135;CHECK-LABEL: cmtst_4h:136;CHECK: cmtst.4h137 %tmp1 = load <4 x i16>, ptr %A138 %tmp2 = load <4 x i16>, ptr %B139 %commonbits = and <4 x i16> %tmp1, %tmp2140 %mask = icmp ne <4 x i16> %commonbits, zeroinitializer141 %res = sext <4 x i1> %mask to <4 x i16>142 ret <4 x i16> %res143}144 145define <8 x i16> @cmtst_8h(ptr %A, ptr %B) nounwind {146;CHECK-LABEL: cmtst_8h:147;CHECK: cmtst.8h148 %tmp1 = load <8 x i16>, ptr %A149 %tmp2 = load <8 x i16>, ptr %B150 %commonbits = and <8 x i16> %tmp1, %tmp2151 %mask = icmp ne <8 x i16> %commonbits, zeroinitializer152 %res = sext <8 x i1> %mask to <8 x i16>153 ret <8 x i16> %res154}155 156define <2 x i32> @cmtst_2s(ptr %A, ptr %B) nounwind {157;CHECK-LABEL: cmtst_2s:158;CHECK: cmtst.2s159 %tmp1 = load <2 x i32>, ptr %A160 %tmp2 = load <2 x i32>, ptr %B161 %commonbits = and <2 x i32> %tmp1, %tmp2162 %mask = icmp ne <2 x i32> %commonbits, zeroinitializer163 %res = sext <2 x i1> %mask to <2 x i32>164 ret <2 x i32> %res165}166 167define <4 x i32> @cmtst_4s(ptr %A, ptr %B) nounwind {168;CHECK-LABEL: cmtst_4s:169;CHECK: cmtst.4s170 %tmp1 = load <4 x i32>, ptr %A171 %tmp2 = load <4 x i32>, ptr %B172 %commonbits = and <4 x i32> %tmp1, %tmp2173 %mask = icmp ne <4 x i32> %commonbits, zeroinitializer174 %res = sext <4 x i1> %mask to <4 x i32>175 ret <4 x i32> %res176}177 178define <2 x i64> @cmtst_2d(ptr %A, ptr %B) nounwind {179;CHECK-LABEL: cmtst_2d:180;CHECK: cmtst.2d181 %tmp1 = load <2 x i64>, ptr %A182 %tmp2 = load <2 x i64>, ptr %B183 %commonbits = and <2 x i64> %tmp1, %tmp2184 %mask = icmp ne <2 x i64> %commonbits, zeroinitializer185 %res = sext <2 x i1> %mask to <2 x i64>186 ret <2 x i64> %res187}188 189define <1 x i64> @fcmeq_d(<1 x double> %A, <1 x double> %B) nounwind {190; CHECK-LABEL: fcmeq_d:191; CHECK: fcmeq {{d[0-9]+}}, d0, d1192 %tst = fcmp oeq <1 x double> %A, %B193 %mask = sext <1 x i1> %tst to <1 x i64>194 ret <1 x i64> %mask195}196 197define <1 x i64> @fcmge_d(<1 x double> %A, <1 x double> %B) nounwind {198; CHECK-LABEL: fcmge_d:199; CHECK: fcmge {{d[0-9]+}}, d0, d1200 %tst = fcmp oge <1 x double> %A, %B201 %mask = sext <1 x i1> %tst to <1 x i64>202 ret <1 x i64> %mask203}204 205define <1 x i64> @fcmle_d(<1 x double> %A, <1 x double> %B) nounwind {206; CHECK-LABEL: fcmle_d:207; CHECK: fcmge {{d[0-9]+}}, d1, d0208 %tst = fcmp ole <1 x double> %A, %B209 %mask = sext <1 x i1> %tst to <1 x i64>210 ret <1 x i64> %mask211}212 213define <1 x i64> @fcmgt_d(<1 x double> %A, <1 x double> %B) nounwind {214; CHECK-LABEL: fcmgt_d:215; CHECK: fcmgt {{d[0-9]+}}, d0, d1216 %tst = fcmp ogt <1 x double> %A, %B217 %mask = sext <1 x i1> %tst to <1 x i64>218 ret <1 x i64> %mask219}220 221define <1 x i64> @fcmlt_d(<1 x double> %A, <1 x double> %B) nounwind {222; CHECK-LABEL: fcmlt_d:223; CHECK: fcmgt {{d[0-9]+}}, d1, d0224 %tst = fcmp olt <1 x double> %A, %B225 %mask = sext <1 x i1> %tst to <1 x i64>226 ret <1 x i64> %mask227}228 229define <1 x i64> @cmnez_d(<1 x i64> %A) nounwind {230; CHECK-LABEL: cmnez_d:231; CHECK: cmeq d[[EQ:[0-9]+]], d0, #0232; CHECK: mvn.8b v0, v[[EQ]]233 %tst = icmp ne <1 x i64> %A, zeroinitializer234 %mask = sext <1 x i1> %tst to <1 x i64>235 ret <1 x i64> %mask236}237