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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind {6; CHECK-LABEL: fcvtas_2s:7; CHECK: // %bb.0:8; CHECK-NEXT: fcvtas.2s v0, v09; CHECK-NEXT: ret10 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)11 ret <2 x i32> %tmp312}13 14define <4 x i32> @fcvtas_4s(<4 x float> %A) nounwind {15; CHECK-LABEL: fcvtas_4s:16; CHECK: // %bb.0:17; CHECK-NEXT: fcvtas.4s v0, v018; CHECK-NEXT: ret19 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A)20 ret <4 x i32> %tmp321}22 23define <2 x i64> @fcvtas_2d(<2 x double> %A) nounwind {24; CHECK-LABEL: fcvtas_2d:25; CHECK: // %bb.0:26; CHECK-NEXT: fcvtas.2d v0, v027; CHECK-NEXT: ret28 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)29 ret <2 x i64> %tmp330}31 32define <1 x i64> @fcvtas_1d(<1 x double> %A) nounwind {33; CHECK-LABEL: fcvtas_1d:34; CHECK: // %bb.0:35; CHECK-NEXT: fcvtas d0, d036; CHECK-NEXT: ret37 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %A)38 ret <1 x i64> %tmp339}40 41declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone42declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone43declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone44declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double>) nounwind readnone45 46define <2 x i32> @fcvtau_2s(<2 x float> %A) nounwind {47; CHECK-LABEL: fcvtau_2s:48; CHECK: // %bb.0:49; CHECK-NEXT: fcvtau.2s v0, v050; CHECK-NEXT: ret51 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)52 ret <2 x i32> %tmp353}54 55define <4 x i32> @fcvtau_4s(<4 x float> %A) nounwind {56; CHECK-LABEL: fcvtau_4s:57; CHECK: // %bb.0:58; CHECK-NEXT: fcvtau.4s v0, v059; CHECK-NEXT: ret60 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)61 ret <4 x i32> %tmp362}63 64define <2 x i64> @fcvtau_2d(<2 x double> %A) nounwind {65; CHECK-LABEL: fcvtau_2d:66; CHECK: // %bb.0:67; CHECK-NEXT: fcvtau.2d v0, v068; CHECK-NEXT: ret69 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)70 ret <2 x i64> %tmp371}72 73define <1 x i64> @fcvtau_1d(<1 x double> %A) nounwind {74; CHECK-LABEL: fcvtau_1d:75; CHECK: // %bb.0:76; CHECK-NEXT: fcvtau d0, d077; CHECK-NEXT: ret78 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> %A)79 ret <1 x i64> %tmp380}81 82declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone83declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone84declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone85declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double>) nounwind readnone86 87define <2 x i32> @fcvtms_2s(<2 x float> %A) nounwind {88; CHECK-LABEL: fcvtms_2s:89; CHECK: // %bb.0:90; CHECK-NEXT: fcvtms.2s v0, v091; CHECK-NEXT: ret92 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %A)93 ret <2 x i32> %tmp394}95 96define <4 x i32> @fcvtms_4s(<4 x float> %A) nounwind {97; CHECK-LABEL: fcvtms_4s:98; CHECK: // %bb.0:99; CHECK-NEXT: fcvtms.4s v0, v0100; CHECK-NEXT: ret101 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %A)102 ret <4 x i32> %tmp3103}104 105define <2 x i64> @fcvtms_2d(<2 x double> %A) nounwind {106; CHECK-LABEL: fcvtms_2d:107; CHECK: // %bb.0:108; CHECK-NEXT: fcvtms.2d v0, v0109; CHECK-NEXT: ret110 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A)111 ret <2 x i64> %tmp3112}113 114define <1 x i64> @fcvtms_1d(<1 x double> %A) nounwind {115; CHECK-LABEL: fcvtms_1d:116; CHECK: // %bb.0:117; CHECK-NEXT: fcvtms d0, d0118; CHECK-NEXT: ret119 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> %A)120 ret <1 x i64> %tmp3121}122 123declare <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float>) nounwind readnone124declare <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float>) nounwind readnone125declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone126declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double>) nounwind readnone127 128define <2 x i32> @fcvtmu_2s(<2 x float> %A) nounwind {129; CHECK-LABEL: fcvtmu_2s:130; CHECK: // %bb.0:131; CHECK-NEXT: fcvtmu.2s v0, v0132; CHECK-NEXT: ret133 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A)134 ret <2 x i32> %tmp3135}136 137define <4 x i32> @fcvtmu_4s(<4 x float> %A) nounwind {138; CHECK-LABEL: fcvtmu_4s:139; CHECK: // %bb.0:140; CHECK-NEXT: fcvtmu.4s v0, v0141; CHECK-NEXT: ret142 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A)143 ret <4 x i32> %tmp3144}145 146define <2 x i64> @fcvtmu_2d(<2 x double> %A) nounwind {147; CHECK-LABEL: fcvtmu_2d:148; CHECK: // %bb.0:149; CHECK-NEXT: fcvtmu.2d v0, v0150; CHECK-NEXT: ret151 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A)152 ret <2 x i64> %tmp3153}154 155define <1 x i64> @fcvtmu_1d(<1 x double> %A) nounwind {156; CHECK-LABEL: fcvtmu_1d:157; CHECK: // %bb.0:158; CHECK-NEXT: fcvtmu d0, d0159; CHECK-NEXT: ret160 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> %A)161 ret <1 x i64> %tmp3162}163 164declare <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone165declare <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone166declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone167declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double>) nounwind readnone168 169define <2 x i32> @fcvtps_2s(<2 x float> %A) nounwind {170; CHECK-LABEL: fcvtps_2s:171; CHECK: // %bb.0:172; CHECK-NEXT: fcvtps.2s v0, v0173; CHECK-NEXT: ret174 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A)175 ret <2 x i32> %tmp3176}177 178define <4 x i32> @fcvtps_4s(<4 x float> %A) nounwind {179; CHECK-LABEL: fcvtps_4s:180; CHECK: // %bb.0:181; CHECK-NEXT: fcvtps.4s v0, v0182; CHECK-NEXT: ret183 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A)184 ret <4 x i32> %tmp3185}186 187define <2 x i64> @fcvtps_2d(<2 x double> %A) nounwind {188; CHECK-LABEL: fcvtps_2d:189; CHECK: // %bb.0:190; CHECK-NEXT: fcvtps.2d v0, v0191; CHECK-NEXT: ret192 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)193 ret <2 x i64> %tmp3194}195 196define <1 x i64> @fcvtps_1d(<1 x double> %A) nounwind {197; CHECK-LABEL: fcvtps_1d:198; CHECK: // %bb.0:199; CHECK-NEXT: fcvtps d0, d0200; CHECK-NEXT: ret201 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %A)202 ret <1 x i64> %tmp3203}204 205declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone206declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone207declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone208declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double>) nounwind readnone209 210define <2 x i32> @fcvtpu_2s(<2 x float> %A) nounwind {211; CHECK-LABEL: fcvtpu_2s:212; CHECK: // %bb.0:213; CHECK-NEXT: fcvtpu.2s v0, v0214; CHECK-NEXT: ret215 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> %A)216 ret <2 x i32> %tmp3217}218 219define <4 x i32> @fcvtpu_4s(<4 x float> %A) nounwind {220; CHECK-LABEL: fcvtpu_4s:221; CHECK: // %bb.0:222; CHECK-NEXT: fcvtpu.4s v0, v0223; CHECK-NEXT: ret224 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> %A)225 ret <4 x i32> %tmp3226}227 228define <2 x i64> @fcvtpu_2d(<2 x double> %A) nounwind {229; CHECK-LABEL: fcvtpu_2d:230; CHECK: // %bb.0:231; CHECK-NEXT: fcvtpu.2d v0, v0232; CHECK-NEXT: ret233 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> %A)234 ret <2 x i64> %tmp3235}236 237define <1 x i64> @fcvtpu_1d(<1 x double> %A) nounwind {238; CHECK-LABEL: fcvtpu_1d:239; CHECK: // %bb.0:240; CHECK-NEXT: fcvtpu d0, d0241; CHECK-NEXT: ret242 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> %A)243 ret <1 x i64> %tmp3244}245 246declare <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone247declare <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone248declare <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double>) nounwind readnone249declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double>) nounwind readnone250 251define <2 x i32> @fcvtns_2s(<2 x float> %A) nounwind {252; CHECK-LABEL: fcvtns_2s:253; CHECK: // %bb.0:254; CHECK-NEXT: fcvtns.2s v0, v0255; CHECK-NEXT: ret256 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> %A)257 ret <2 x i32> %tmp3258}259 260define <4 x i32> @fcvtns_4s(<4 x float> %A) nounwind {261; CHECK-LABEL: fcvtns_4s:262; CHECK: // %bb.0:263; CHECK-NEXT: fcvtns.4s v0, v0264; CHECK-NEXT: ret265 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> %A)266 ret <4 x i32> %tmp3267}268 269define <2 x i64> @fcvtns_2d(<2 x double> %A) nounwind {270; CHECK-LABEL: fcvtns_2d:271; CHECK: // %bb.0:272; CHECK-NEXT: fcvtns.2d v0, v0273; CHECK-NEXT: ret274 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> %A)275 ret <2 x i64> %tmp3276}277 278define <1 x i64> @fcvtns_1d(<1 x double> %A) nounwind {279; CHECK-LABEL: fcvtns_1d:280; CHECK: // %bb.0:281; CHECK-NEXT: fcvtns d0, d0282; CHECK-NEXT: ret283 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double> %A)284 ret <1 x i64> %tmp3285}286 287declare <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float>) nounwind readnone288declare <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float>) nounwind readnone289declare <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double>) nounwind readnone290declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double>) nounwind readnone291 292define <2 x i32> @fcvtnu_2s(<2 x float> %A) nounwind {293; CHECK-LABEL: fcvtnu_2s:294; CHECK: // %bb.0:295; CHECK-NEXT: fcvtnu.2s v0, v0296; CHECK-NEXT: ret297 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A)298 ret <2 x i32> %tmp3299}300 301define <4 x i32> @fcvtnu_4s(<4 x float> %A) nounwind {302; CHECK-LABEL: fcvtnu_4s:303; CHECK: // %bb.0:304; CHECK-NEXT: fcvtnu.4s v0, v0305; CHECK-NEXT: ret306 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A)307 ret <4 x i32> %tmp3308}309 310define <2 x i64> @fcvtnu_2d(<2 x double> %A) nounwind {311; CHECK-LABEL: fcvtnu_2d:312; CHECK: // %bb.0:313; CHECK-NEXT: fcvtnu.2d v0, v0314; CHECK-NEXT: ret315 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A)316 ret <2 x i64> %tmp3317}318 319define <1 x i64> @fcvtnu_1d(<1 x double> %A) nounwind {320; CHECK-LABEL: fcvtnu_1d:321; CHECK: // %bb.0:322; CHECK-NEXT: fcvtnu d0, d0323; CHECK-NEXT: ret324 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> %A)325 ret <1 x i64> %tmp3326}327 328declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone329declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone330declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone331declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double>) nounwind readnone332 333define <2 x i32> @fcvtzs_2s(<2 x float> %A) nounwind {334; CHECK-LABEL: fcvtzs_2s:335; CHECK: // %bb.0:336; CHECK-NEXT: fcvtzs.2s v0, v0337; CHECK-NEXT: ret338 %tmp3 = fptosi <2 x float> %A to <2 x i32>339 ret <2 x i32> %tmp3340}341 342define <4 x i32> @fcvtzs_4s(<4 x float> %A) nounwind {343; CHECK-LABEL: fcvtzs_4s:344; CHECK: // %bb.0:345; CHECK-NEXT: fcvtzs.4s v0, v0346; CHECK-NEXT: ret347 %tmp3 = fptosi <4 x float> %A to <4 x i32>348 ret <4 x i32> %tmp3349}350 351define <2 x i64> @fcvtzs_2d(<2 x double> %A) nounwind {352; CHECK-LABEL: fcvtzs_2d:353; CHECK: // %bb.0:354; CHECK-NEXT: fcvtzs.2d v0, v0355; CHECK-NEXT: ret356 %tmp3 = fptosi <2 x double> %A to <2 x i64>357 ret <2 x i64> %tmp3358}359 360; FIXME: Generate "fcvtzs d0, d0"?361define <1 x i64> @fcvtzs_1d(<1 x double> %A) nounwind {362; CHECK-SD-LABEL: fcvtzs_1d:363; CHECK-SD: // %bb.0:364; CHECK-SD-NEXT: fcvtzs x8, d0365; CHECK-SD-NEXT: fmov d0, x8366; CHECK-SD-NEXT: ret367;368; CHECK-GI-LABEL: fcvtzs_1d:369; CHECK-GI: // %bb.0:370; CHECK-GI-NEXT: fcvtzs d0, d0371; CHECK-GI-NEXT: ret372 %tmp3 = fptosi <1 x double> %A to <1 x i64>373 ret <1 x i64> %tmp3374}375 376define <2 x i32> @fcvtzs_2s_intrinsic(<2 x float> %A) nounwind {377; CHECK-LABEL: fcvtzs_2s_intrinsic:378; CHECK: // %bb.0:379; CHECK-NEXT: fcvtzs.2s v0, v0380; CHECK-NEXT: ret381 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float> %A)382 ret <2 x i32> %tmp3383}384 385define <4 x i32> @fcvtzs_4s_intrinsic(<4 x float> %A) nounwind {386; CHECK-LABEL: fcvtzs_4s_intrinsic:387; CHECK: // %bb.0:388; CHECK-NEXT: fcvtzs.4s v0, v0389; CHECK-NEXT: ret390 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float> %A)391 ret <4 x i32> %tmp3392}393 394define <2 x i64> @fcvtzs_2d_intrinsic(<2 x double> %A) nounwind {395; CHECK-LABEL: fcvtzs_2d_intrinsic:396; CHECK: // %bb.0:397; CHECK-NEXT: fcvtzs.2d v0, v0398; CHECK-NEXT: ret399 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double> %A)400 ret <2 x i64> %tmp3401}402 403define <1 x i64> @fcvtzs_1d_intrinsic(<1 x double> %A) nounwind {404; CHECK-LABEL: fcvtzs_1d_intrinsic:405; CHECK: // %bb.0:406; CHECK-NEXT: fcvtzs d0, d0407; CHECK-NEXT: ret408 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> %A)409 ret <1 x i64> %tmp3410}411 412declare <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float>) nounwind readnone413declare <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float>) nounwind readnone414declare <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double>) nounwind readnone415declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double>) nounwind readnone416 417define <2 x i32> @fcvtzu_2s(<2 x float> %A) nounwind {418; CHECK-LABEL: fcvtzu_2s:419; CHECK: // %bb.0:420; CHECK-NEXT: fcvtzu.2s v0, v0421; CHECK-NEXT: ret422 %tmp3 = fptoui <2 x float> %A to <2 x i32>423 ret <2 x i32> %tmp3424}425 426define <4 x i32> @fcvtzu_4s(<4 x float> %A) nounwind {427; CHECK-LABEL: fcvtzu_4s:428; CHECK: // %bb.0:429; CHECK-NEXT: fcvtzu.4s v0, v0430; CHECK-NEXT: ret431 %tmp3 = fptoui <4 x float> %A to <4 x i32>432 ret <4 x i32> %tmp3433}434 435define <2 x i64> @fcvtzu_2d(<2 x double> %A) nounwind {436; CHECK-LABEL: fcvtzu_2d:437; CHECK: // %bb.0:438; CHECK-NEXT: fcvtzu.2d v0, v0439; CHECK-NEXT: ret440 %tmp3 = fptoui <2 x double> %A to <2 x i64>441 ret <2 x i64> %tmp3442}443 444; FIXME: Generate "fcvtzu d0, d0"?445define <1 x i64> @fcvtzu_1d(<1 x double> %A) nounwind {446; CHECK-SD-LABEL: fcvtzu_1d:447; CHECK-SD: // %bb.0:448; CHECK-SD-NEXT: fcvtzu x8, d0449; CHECK-SD-NEXT: fmov d0, x8450; CHECK-SD-NEXT: ret451;452; CHECK-GI-LABEL: fcvtzu_1d:453; CHECK-GI: // %bb.0:454; CHECK-GI-NEXT: fcvtzu d0, d0455; CHECK-GI-NEXT: ret456 %tmp3 = fptoui <1 x double> %A to <1 x i64>457 ret <1 x i64> %tmp3458}459 460define <2 x i32> @fcvtzu_2s_intrinsic(<2 x float> %A) nounwind {461; CHECK-LABEL: fcvtzu_2s_intrinsic:462; CHECK: // %bb.0:463; CHECK-NEXT: fcvtzu.2s v0, v0464; CHECK-NEXT: ret465 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float> %A)466 ret <2 x i32> %tmp3467}468 469define <4 x i32> @fcvtzu_4s_intrinsic(<4 x float> %A) nounwind {470; CHECK-LABEL: fcvtzu_4s_intrinsic:471; CHECK: // %bb.0:472; CHECK-NEXT: fcvtzu.4s v0, v0473; CHECK-NEXT: ret474 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float> %A)475 ret <4 x i32> %tmp3476}477 478define <2 x i64> @fcvtzu_2d_intrinsic(<2 x double> %A) nounwind {479; CHECK-LABEL: fcvtzu_2d_intrinsic:480; CHECK: // %bb.0:481; CHECK-NEXT: fcvtzu.2d v0, v0482; CHECK-NEXT: ret483 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double> %A)484 ret <2 x i64> %tmp3485}486 487define <1 x i64> @fcvtzu_1d_intrinsic(<1 x double> %A) nounwind {488; CHECK-LABEL: fcvtzu_1d_intrinsic:489; CHECK: // %bb.0:490; CHECK-NEXT: fcvtzu d0, d0491; CHECK-NEXT: ret492 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> %A)493 ret <1 x i64> %tmp3494}495 496declare <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float>) nounwind readnone497declare <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float>) nounwind readnone498declare <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double>) nounwind readnone499declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double>) nounwind readnone500 501define <2 x float> @frinta_2s(<2 x float> %A) nounwind {502; CHECK-LABEL: frinta_2s:503; CHECK: // %bb.0:504; CHECK-NEXT: frinta.2s v0, v0505; CHECK-NEXT: ret506 %tmp3 = call <2 x float> @llvm.round.v2f32(<2 x float> %A)507 ret <2 x float> %tmp3508}509 510define <4 x float> @frinta_4s(<4 x float> %A) nounwind {511; CHECK-LABEL: frinta_4s:512; CHECK: // %bb.0:513; CHECK-NEXT: frinta.4s v0, v0514; CHECK-NEXT: ret515 %tmp3 = call <4 x float> @llvm.round.v4f32(<4 x float> %A)516 ret <4 x float> %tmp3517}518 519define <2 x double> @frinta_2d(<2 x double> %A) nounwind {520; CHECK-LABEL: frinta_2d:521; CHECK: // %bb.0:522; CHECK-NEXT: frinta.2d v0, v0523; CHECK-NEXT: ret524 %tmp3 = call <2 x double> @llvm.round.v2f64(<2 x double> %A)525 ret <2 x double> %tmp3526}527 528declare <2 x float> @llvm.round.v2f32(<2 x float>) nounwind readnone529declare <4 x float> @llvm.round.v4f32(<4 x float>) nounwind readnone530declare <2 x double> @llvm.round.v2f64(<2 x double>) nounwind readnone531 532define <2 x float> @frinti_2s(<2 x float> %A) nounwind {533; CHECK-LABEL: frinti_2s:534; CHECK: // %bb.0:535; CHECK-NEXT: frinti.2s v0, v0536; CHECK-NEXT: ret537 %tmp3 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %A)538 ret <2 x float> %tmp3539}540 541define <4 x float> @frinti_4s(<4 x float> %A) nounwind {542; CHECK-LABEL: frinti_4s:543; CHECK: // %bb.0:544; CHECK-NEXT: frinti.4s v0, v0545; CHECK-NEXT: ret546 %tmp3 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %A)547 ret <4 x float> %tmp3548}549 550define <2 x double> @frinti_2d(<2 x double> %A) nounwind {551; CHECK-LABEL: frinti_2d:552; CHECK: // %bb.0:553; CHECK-NEXT: frinti.2d v0, v0554; CHECK-NEXT: ret555 %tmp3 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %A)556 ret <2 x double> %tmp3557}558 559declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) nounwind readnone560declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone561declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) nounwind readnone562 563define <2 x float> @frintm_2s(<2 x float> %A) nounwind {564; CHECK-LABEL: frintm_2s:565; CHECK: // %bb.0:566; CHECK-NEXT: frintm.2s v0, v0567; CHECK-NEXT: ret568 %tmp3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A)569 ret <2 x float> %tmp3570}571 572define <4 x float> @frintm_4s(<4 x float> %A) nounwind {573; CHECK-LABEL: frintm_4s:574; CHECK: // %bb.0:575; CHECK-NEXT: frintm.4s v0, v0576; CHECK-NEXT: ret577 %tmp3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A)578 ret <4 x float> %tmp3579}580 581define <2 x double> @frintm_2d(<2 x double> %A) nounwind {582; CHECK-LABEL: frintm_2d:583; CHECK: // %bb.0:584; CHECK-NEXT: frintm.2d v0, v0585; CHECK-NEXT: ret586 %tmp3 = call <2 x double> @llvm.floor.v2f64(<2 x double> %A)587 ret <2 x double> %tmp3588}589 590declare <2 x float> @llvm.floor.v2f32(<2 x float>) nounwind readnone591declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone592declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone593 594define <2 x float> @frintn_2s(<2 x float> %A) nounwind {595; CHECK-LABEL: frintn_2s:596; CHECK: // %bb.0:597; CHECK-NEXT: frintn.2s v0, v0598; CHECK-NEXT: ret599 %tmp3 = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %A)600 ret <2 x float> %tmp3601}602 603define <4 x float> @frintn_4s(<4 x float> %A) nounwind {604; CHECK-LABEL: frintn_4s:605; CHECK: // %bb.0:606; CHECK-NEXT: frintn.4s v0, v0607; CHECK-NEXT: ret608 %tmp3 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %A)609 ret <4 x float> %tmp3610}611 612define <2 x double> @frintn_2d(<2 x double> %A) nounwind {613; CHECK-LABEL: frintn_2d:614; CHECK: // %bb.0:615; CHECK-NEXT: frintn.2d v0, v0616; CHECK-NEXT: ret617 %tmp3 = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %A)618 ret <2 x double> %tmp3619}620 621declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) nounwind readnone622declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) nounwind readnone623declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) nounwind readnone624 625define <2 x float> @frintp_2s(<2 x float> %A) nounwind {626; CHECK-LABEL: frintp_2s:627; CHECK: // %bb.0:628; CHECK-NEXT: frintp.2s v0, v0629; CHECK-NEXT: ret630 %tmp3 = call <2 x float> @llvm.ceil.v2f32(<2 x float> %A)631 ret <2 x float> %tmp3632}633 634define <4 x float> @frintp_4s(<4 x float> %A) nounwind {635; CHECK-LABEL: frintp_4s:636; CHECK: // %bb.0:637; CHECK-NEXT: frintp.4s v0, v0638; CHECK-NEXT: ret639 %tmp3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %A)640 ret <4 x float> %tmp3641}642 643define <2 x double> @frintp_2d(<2 x double> %A) nounwind {644; CHECK-LABEL: frintp_2d:645; CHECK: // %bb.0:646; CHECK-NEXT: frintp.2d v0, v0647; CHECK-NEXT: ret648 %tmp3 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %A)649 ret <2 x double> %tmp3650}651 652declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone653declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone654declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone655 656define <2 x float> @frintx_2s(<2 x float> %A) nounwind {657; CHECK-LABEL: frintx_2s:658; CHECK: // %bb.0:659; CHECK-NEXT: frintx.2s v0, v0660; CHECK-NEXT: ret661 %tmp3 = call <2 x float> @llvm.rint.v2f32(<2 x float> %A)662 ret <2 x float> %tmp3663}664 665define <4 x float> @frintx_4s(<4 x float> %A) nounwind {666; CHECK-LABEL: frintx_4s:667; CHECK: // %bb.0:668; CHECK-NEXT: frintx.4s v0, v0669; CHECK-NEXT: ret670 %tmp3 = call <4 x float> @llvm.rint.v4f32(<4 x float> %A)671 ret <4 x float> %tmp3672}673 674define <2 x double> @frintx_2d(<2 x double> %A) nounwind {675; CHECK-LABEL: frintx_2d:676; CHECK: // %bb.0:677; CHECK-NEXT: frintx.2d v0, v0678; CHECK-NEXT: ret679 %tmp3 = call <2 x double> @llvm.rint.v2f64(<2 x double> %A)680 ret <2 x double> %tmp3681}682 683declare <2 x float> @llvm.rint.v2f32(<2 x float>) nounwind readnone684declare <4 x float> @llvm.rint.v4f32(<4 x float>) nounwind readnone685declare <2 x double> @llvm.rint.v2f64(<2 x double>) nounwind readnone686 687define <2 x float> @frintz_2s(<2 x float> %A) nounwind {688; CHECK-LABEL: frintz_2s:689; CHECK: // %bb.0:690; CHECK-NEXT: frintz.2s v0, v0691; CHECK-NEXT: ret692 %tmp3 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %A)693 ret <2 x float> %tmp3694}695 696define <4 x float> @frintz_4s(<4 x float> %A) nounwind {697; CHECK-LABEL: frintz_4s:698; CHECK: // %bb.0:699; CHECK-NEXT: frintz.4s v0, v0700; CHECK-NEXT: ret701 %tmp3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %A)702 ret <4 x float> %tmp3703}704 705define <2 x double> @frintz_2d(<2 x double> %A) nounwind {706; CHECK-LABEL: frintz_2d:707; CHECK: // %bb.0:708; CHECK-NEXT: frintz.2d v0, v0709; CHECK-NEXT: ret710 %tmp3 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %A)711 ret <2 x double> %tmp3712}713 714declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone715declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone716declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone717 718define <2 x float> @fcvtxn_2s(<2 x double> %A) nounwind {719; CHECK-LABEL: fcvtxn_2s:720; CHECK: // %bb.0:721; CHECK-NEXT: fcvtxn v0.2s, v0.2d722; CHECK-NEXT: ret723 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)724 ret <2 x float> %tmp3725}726 727define <4 x float> @fcvtxn_4s(<2 x float> %ret, <2 x double> %A) nounwind {728; CHECK-LABEL: fcvtxn_4s:729; CHECK: // %bb.0:730; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0731; CHECK-NEXT: fcvtxn2 v0.4s, v1.2d732; CHECK-NEXT: ret733 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)734 %res = shufflevector <2 x float> %ret, <2 x float> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>735 ret <4 x float> %res736}737 738declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone739 740define <2 x i32> @fcvtzsc_2s(<2 x float> %A) nounwind {741; CHECK-LABEL: fcvtzsc_2s:742; CHECK: // %bb.0:743; CHECK-NEXT: fcvtzs.2s v0, v0, #1744; CHECK-NEXT: ret745 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %A, i32 1)746 ret <2 x i32> %tmp3747}748 749define <4 x i32> @fcvtzsc_4s(<4 x float> %A) nounwind {750; CHECK-LABEL: fcvtzsc_4s:751; CHECK: // %bb.0:752; CHECK-NEXT: fcvtzs.4s v0, v0, #1753; CHECK-NEXT: ret754 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %A, i32 1)755 ret <4 x i32> %tmp3756}757 758define <2 x i64> @fcvtzsc_2d(<2 x double> %A) nounwind {759; CHECK-LABEL: fcvtzsc_2d:760; CHECK: // %bb.0:761; CHECK-NEXT: fcvtzs.2d v0, v0, #1762; CHECK-NEXT: ret763 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double> %A, i32 1)764 ret <2 x i64> %tmp3765}766 767declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone768declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone769declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32) nounwind readnone770 771define <2 x i32> @fcvtzuc_2s(<2 x float> %A) nounwind {772; CHECK-LABEL: fcvtzuc_2s:773; CHECK: // %bb.0:774; CHECK-NEXT: fcvtzu.2s v0, v0, #1775; CHECK-NEXT: ret776 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %A, i32 1)777 ret <2 x i32> %tmp3778}779 780define <4 x i32> @fcvtzuc_4s(<4 x float> %A) nounwind {781; CHECK-LABEL: fcvtzuc_4s:782; CHECK: // %bb.0:783; CHECK-NEXT: fcvtzu.4s v0, v0, #1784; CHECK-NEXT: ret785 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %A, i32 1)786 ret <4 x i32> %tmp3787}788 789define <2 x i64> @fcvtzuc_2d(<2 x double> %A) nounwind {790; CHECK-LABEL: fcvtzuc_2d:791; CHECK: // %bb.0:792; CHECK-NEXT: fcvtzu.2d v0, v0, #1793; CHECK-NEXT: ret794 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double> %A, i32 1)795 ret <2 x i64> %tmp3796}797 798declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone799declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone800declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32) nounwind readnone801 802define <2 x float> @scvtf_2sc(<2 x i32> %A) nounwind {803; CHECK-LABEL: scvtf_2sc:804; CHECK: // %bb.0:805; CHECK-NEXT: scvtf.2s v0, v0, #1806; CHECK-NEXT: ret807 %tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %A, i32 1)808 ret <2 x float> %tmp3809}810 811define <4 x float> @scvtf_4sc(<4 x i32> %A) nounwind {812; CHECK-LABEL: scvtf_4sc:813; CHECK: // %bb.0:814; CHECK-NEXT: scvtf.4s v0, v0, #1815; CHECK-NEXT: ret816 %tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %A, i32 1)817 ret <4 x float> %tmp3818}819 820define <2 x double> @scvtf_2dc(<2 x i64> %A) nounwind {821; CHECK-LABEL: scvtf_2dc:822; CHECK: // %bb.0:823; CHECK-NEXT: scvtf.2d v0, v0, #1824; CHECK-NEXT: ret825 %tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %A, i32 1)826 ret <2 x double> %tmp3827}828 829declare <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone830declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone831declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone832 833define <2 x float> @ucvtf_2sc(<2 x i32> %A) nounwind {834; CHECK-LABEL: ucvtf_2sc:835; CHECK: // %bb.0:836; CHECK-NEXT: ucvtf.2s v0, v0, #1837; CHECK-NEXT: ret838 %tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %A, i32 1)839 ret <2 x float> %tmp3840}841 842define <4 x float> @ucvtf_4sc(<4 x i32> %A) nounwind {843; CHECK-LABEL: ucvtf_4sc:844; CHECK: // %bb.0:845; CHECK-NEXT: ucvtf.4s v0, v0, #1846; CHECK-NEXT: ret847 %tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %A, i32 1)848 ret <4 x float> %tmp3849}850 851define <2 x double> @ucvtf_2dc(<2 x i64> %A) nounwind {852; CHECK-LABEL: ucvtf_2dc:853; CHECK: // %bb.0:854; CHECK-NEXT: ucvtf.2d v0, v0, #1855; CHECK-NEXT: ret856 %tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %A, i32 1)857 ret <2 x double> %tmp3858}859 860define void @autogen_SD28458(<8 x double> %val.f64, ptr %addr.f32) {861; CHECK-SD-LABEL: autogen_SD28458:862; CHECK-SD: // %bb.0:863; CHECK-SD-NEXT: fcvtn v2.2s, v2.2d864; CHECK-SD-NEXT: fcvtn v0.2s, v0.2d865; CHECK-SD-NEXT: fcvtn2 v2.4s, v3.2d866; CHECK-SD-NEXT: fcvtn2 v0.4s, v1.2d867; CHECK-SD-NEXT: stp q0, q2, [x0]868; CHECK-SD-NEXT: ret869;870; CHECK-GI-LABEL: autogen_SD28458:871; CHECK-GI: // %bb.0:872; CHECK-GI-NEXT: fcvtn v0.2s, v0.2d873; CHECK-GI-NEXT: fcvtn v2.2s, v2.2d874; CHECK-GI-NEXT: fcvtn2 v0.4s, v1.2d875; CHECK-GI-NEXT: fcvtn2 v2.4s, v3.2d876; CHECK-GI-NEXT: stp q0, q2, [x0]877; CHECK-GI-NEXT: ret878 %Tr53 = fptrunc <8 x double> %val.f64 to <8 x float>879 store <8 x float> %Tr53, ptr %addr.f32880 ret void881}882 883define void @autogen_SD19225(ptr %addr.f64, ptr %addr.f32) {884; CHECK-SD-LABEL: autogen_SD19225:885; CHECK-SD: // %bb.0:886; CHECK-SD-NEXT: ldp q1, q0, [x1]887; CHECK-SD-NEXT: fcvtl2 v2.2d, v0.4s888; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s889; CHECK-SD-NEXT: fcvtl2 v3.2d, v1.4s890; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s891; CHECK-SD-NEXT: stp q0, q2, [x0, #32]892; CHECK-SD-NEXT: stp q1, q3, [x0]893; CHECK-SD-NEXT: ret894;895; CHECK-GI-LABEL: autogen_SD19225:896; CHECK-GI: // %bb.0:897; CHECK-GI-NEXT: ldp q0, q1, [x1]898; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s899; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s900; CHECK-GI-NEXT: fcvtl v3.2d, v1.2s901; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s902; CHECK-GI-NEXT: stp q2, q0, [x0]903; CHECK-GI-NEXT: stp q3, q1, [x0, #32]904; CHECK-GI-NEXT: ret905 %A = load <8 x float>, ptr %addr.f32906 %Tr53 = fpext <8 x float> %A to <8 x double>907 store <8 x double> %Tr53, ptr %addr.f64908 ret void909}910 911declare <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone912declare <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone913declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone914