320 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -O0 -fast-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FI4; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI5 6; CHECK-GI: warning: Instruction selection used fallback path for test_vcvt_bf16_f647 8define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {9; CHECK-LABEL: test_vcvt_f64_f32:10; CHECK: // %bb.0:11; CHECK-NEXT: fcvtl v0.2d, v0.2s12; CHECK-NEXT: ret13 %vcvt1.i = fpext <2 x float> %x to <2 x double>14 ret <2 x double> %vcvt1.i15}16 17define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {18; CHECK-LABEL: test_vcvt_high_f64_f32:19; CHECK: // %bb.0:20; CHECK-NEXT: fcvtl2 v0.2d, v0.4s21; CHECK-NEXT: ret22 %cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>23 %vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>24 ret <2 x double> %vcvt1.i25}26 27define <2 x double> @test_vcvt_high_v1f64_f32_bitcast(<4 x float> %x) nounwind readnone ssp {28; CHECK-LABEL: test_vcvt_high_v1f64_f32_bitcast:29; CHECK: // %bb.0:30; CHECK-NEXT: fcvtl2 v0.2d, v0.4s31; CHECK-NEXT: ret32 %bc1 = bitcast <4 x float> %x to <2 x double>33 %ext = shufflevector <2 x double> %bc1, <2 x double> undef, <1 x i32> <i32 1>34 %bc2 = bitcast <1 x double> %ext to <2 x float>35 %r = fpext <2 x float> %bc2 to <2 x double>36 ret <2 x double> %r37}38 39define <2 x double> @test_vcvt_high_v1i64_f32_bitcast(<2 x i64> %x) nounwind readnone ssp {40; CHECK-LABEL: test_vcvt_high_v1i64_f32_bitcast:41; CHECK: // %bb.0:42; CHECK-NEXT: fcvtl2 v0.2d, v0.4s43; CHECK-NEXT: ret44 %ext = shufflevector <2 x i64> %x, <2 x i64> undef, <1 x i32> <i32 1>45 %bc2 = bitcast <1 x i64> %ext to <2 x float>46 %r = fpext <2 x float> %bc2 to <2 x double>47 ret <2 x double> %r48}49 50define <2 x double> @test_vcvt_high_v2i32_f32_bitcast(<4 x i32> %x) nounwind readnone ssp {51; CHECK-LABEL: test_vcvt_high_v2i32_f32_bitcast:52; CHECK: // %bb.0:53; CHECK-NEXT: fcvtl2 v0.2d, v0.4s54; CHECK-NEXT: ret55 %ext = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 2, i32 3>56 %bc2 = bitcast <2 x i32> %ext to <2 x float>57 %r = fpext <2 x float> %bc2 to <2 x double>58 ret <2 x double> %r59}60 61define <2 x double> @test_vcvt_high_v4i16_f32_bitcast(<8 x i16> %x) nounwind readnone ssp {62; CHECK-LABEL: test_vcvt_high_v4i16_f32_bitcast:63; CHECK: // %bb.0:64; CHECK-NEXT: fcvtl2 v0.2d, v0.4s65; CHECK-NEXT: ret66 %ext = shufflevector <8 x i16> %x, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>67 %bc2 = bitcast <4 x i16> %ext to <2 x float>68 %r = fpext <2 x float> %bc2 to <2 x double>69 ret <2 x double> %r70}71 72define <2 x double> @test_vcvt_high_v8i8_f32_bitcast(<16 x i8> %x) nounwind readnone ssp {73; CHECK-LABEL: test_vcvt_high_v8i8_f32_bitcast:74; CHECK: // %bb.0:75; CHECK-NEXT: fcvtl2 v0.2d, v0.4s76; CHECK-NEXT: ret77 %ext = shufflevector <16 x i8> %x, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>78 %bc2 = bitcast <8 x i8> %ext to <2 x float>79 %r = fpext <2 x float> %bc2 to <2 x double>80 ret <2 x double> %r81}82 83define <4 x float> @test_vcvt_high_v1i64_f16_bitcast(<2 x i64> %x) nounwind readnone ssp {84; CHECK-LABEL: test_vcvt_high_v1i64_f16_bitcast:85; CHECK: // %bb.0:86; CHECK-NEXT: fcvtl2 v0.4s, v0.8h87; CHECK-NEXT: ret88 %ext = shufflevector <2 x i64> %x, <2 x i64> undef, <1 x i32> <i32 1>89 %bc2 = bitcast <1 x i64> %ext to <4 x half>90 %r = fpext <4 x half> %bc2 to <4 x float>91 ret <4 x float> %r92}93 94define <4 x float> @test_vcvt_high_v2i32_f16_bitcast(<4 x i32> %x) nounwind readnone ssp {95; CHECK-LABEL: test_vcvt_high_v2i32_f16_bitcast:96; CHECK: // %bb.0:97; CHECK-NEXT: fcvtl2 v0.4s, v0.8h98; CHECK-NEXT: ret99 %ext = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 2, i32 3>100 %bc2 = bitcast <2 x i32> %ext to <4 x half>101 %r = fpext <4 x half> %bc2 to <4 x float>102 ret <4 x float> %r103}104 105define <4 x float> @test_vcvt_high_v4i16_f16_bitcast(<8 x i16> %x) nounwind readnone ssp {106; CHECK-LABEL: test_vcvt_high_v4i16_f16_bitcast:107; CHECK: // %bb.0:108; CHECK-NEXT: fcvtl2 v0.4s, v0.8h109; CHECK-NEXT: ret110 %ext = shufflevector <8 x i16> %x, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>111 %bc2 = bitcast <4 x i16> %ext to <4 x half>112 %r = fpext <4 x half> %bc2 to <4 x float>113 ret <4 x float> %r114}115 116define <4 x float> @test_vcvt_high_v8i8_f16_bitcast(<16 x i8> %x) nounwind readnone ssp {117; CHECK-LABEL: test_vcvt_high_v8i8_f16_bitcast:118; CHECK: // %bb.0:119; CHECK-NEXT: fcvtl2 v0.4s, v0.8h120; CHECK-NEXT: ret121 %ext = shufflevector <16 x i8> %x, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>122 %bc2 = bitcast <8 x i8> %ext to <4 x half>123 %r = fpext <4 x half> %bc2 to <4 x float>124 ret <4 x float> %r125}126 127define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {128; CHECK-LABEL: test_vcvt_f32_f64:129; CHECK: // %bb.0:130; CHECK-NEXT: fcvtn v0.2s, v0.2d131; CHECK-NEXT: ret132 %vcvt1.i = fptrunc <2 x double> %v to <2 x float>133 ret <2 x float> %vcvt1.i134}135 136define <2 x bfloat> @test_vcvt_bf16_f64(<2 x double> %v) nounwind readnone ssp {137; CHECK-SD-LABEL: test_vcvt_bf16_f64:138; CHECK-SD: // %bb.0:139; CHECK-SD-NEXT: fcvtxn v0.2s, v0.2d140; CHECK-SD-NEXT: movi.4s v1, #1141; CHECK-SD-NEXT: movi.4s v2, #127, msl #8142; CHECK-SD-NEXT: ushr.4s v3, v0, #16143; CHECK-SD-NEXT: add.4s v2, v0, v2144; CHECK-SD-NEXT: and.16b v1, v3, v1145; CHECK-SD-NEXT: fcmeq.4s v3, v0, v0146; CHECK-SD-NEXT: orr.4s v0, #64, lsl #16147; CHECK-SD-NEXT: add.4s v1, v1, v2148; CHECK-SD-NEXT: bit.16b v0, v1, v3149; CHECK-SD-NEXT: shrn.4h v0, v0, #16150; CHECK-SD-NEXT: ret151;152; CHECK-FI-LABEL: test_vcvt_bf16_f64:153; CHECK-FI: // %bb.0:154; CHECK-FI-NEXT: fcvtxn v1.2s, v0.2d155; CHECK-FI-NEXT: // implicit-def: $q0156; CHECK-FI-NEXT: fmov d0, d1157; CHECK-FI-NEXT: ushr.4s v1, v0, #16158; CHECK-FI-NEXT: movi.4s v2, #1159; CHECK-FI-NEXT: and.16b v1, v1, v2160; CHECK-FI-NEXT: add.4s v1, v1, v0161; CHECK-FI-NEXT: movi.4s v2, #127, msl #8162; CHECK-FI-NEXT: add.4s v1, v1, v2163; CHECK-FI-NEXT: mov.16b v2, v0164; CHECK-FI-NEXT: orr.4s v2, #64, lsl #16165; CHECK-FI-NEXT: fcmeq.4s v0, v0, v0166; CHECK-FI-NEXT: bsl.16b v0, v1, v2167; CHECK-FI-NEXT: shrn.4h v0, v0, #16168; CHECK-FI-NEXT: ret169;170; CHECK-GI-LABEL: test_vcvt_bf16_f64:171; CHECK-GI: // %bb.0:172; CHECK-GI-NEXT: fcvtxn v0.2s, v0.2d173; CHECK-GI-NEXT: movi.4s v1, #1174; CHECK-GI-NEXT: movi.4s v2, #127, msl #8175; CHECK-GI-NEXT: ushr.4s v3, v0, #16176; CHECK-GI-NEXT: add.4s v2, v0, v2177; CHECK-GI-NEXT: and.16b v1, v3, v1178; CHECK-GI-NEXT: fcmeq.4s v3, v0, v0179; CHECK-GI-NEXT: orr.4s v0, #64, lsl #16180; CHECK-GI-NEXT: add.4s v1, v1, v2181; CHECK-GI-NEXT: bit.16b v0, v1, v3182; CHECK-GI-NEXT: shrn.4h v0, v0, #16183; CHECK-GI-NEXT: ret184 %vcvt1.i = fptrunc <2 x double> %v to <2 x bfloat>185 ret <2 x bfloat> %vcvt1.i186}187 188define half @test_vcvt_f16_f32(<1 x float> %x) {189; CHECK-SD-LABEL: test_vcvt_f16_f32:190; CHECK-SD: // %bb.0:191; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0192; CHECK-SD-NEXT: fcvt h0, s0193; CHECK-SD-NEXT: ret194;195; CHECK-FI-LABEL: test_vcvt_f16_f32:196; CHECK-FI: // %bb.0:197; CHECK-FI-NEXT: fmov d1, d0198; CHECK-FI-NEXT: // implicit-def: $q0199; CHECK-FI-NEXT: fmov d0, d1200; CHECK-FI-NEXT: // kill: def $s0 killed $s0 killed $q0201; CHECK-FI-NEXT: fcvt h0, s0202; CHECK-FI-NEXT: ret203;204; CHECK-GI-LABEL: test_vcvt_f16_f32:205; CHECK-GI: // %bb.0:206; CHECK-GI-NEXT: fcvt h0, s0207; CHECK-GI-NEXT: ret208 %tmp = fptrunc <1 x float> %x to <1 x half>209 %elt = extractelement <1 x half> %tmp, i32 0210 ret half %elt211}212 213define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {214; CHECK-SD-LABEL: test_vcvt_high_f32_f64:215; CHECK-SD: // %bb.0:216; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0217; CHECK-SD-NEXT: fcvtn2 v0.4s, v1.2d218; CHECK-SD-NEXT: ret219;220; CHECK-FI-LABEL: test_vcvt_high_f32_f64:221; CHECK-FI: // %bb.0:222; CHECK-FI-NEXT: fmov d2, d0223; CHECK-FI-NEXT: // implicit-def: $q0224; CHECK-FI-NEXT: fmov d0, d2225; CHECK-FI-NEXT: fcvtn2 v0.4s, v1.2d226; CHECK-FI-NEXT: ret227;228; CHECK-GI-LABEL: test_vcvt_high_f32_f64:229; CHECK-GI: // %bb.0:230; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0231; CHECK-GI-NEXT: fcvtn2 v0.4s, v1.2d232; CHECK-GI-NEXT: ret233 %cvt = fptrunc <2 x double> %v to <2 x float>234 %vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>235 ret <4 x float> %vcvt2.i236}237 238define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {239; CHECK-LABEL: test_vcvtx_f32_f64:240; CHECK: // %bb.0:241; CHECK-NEXT: fcvtxn v0.2s, v0.2d242; CHECK-NEXT: ret243 %vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind244 ret <2 x float> %vcvtx1.i245}246 247define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {248; CHECK-SD-LABEL: test_vcvtx_high_f32_f64:249; CHECK-SD: // %bb.0:250; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0251; CHECK-SD-NEXT: fcvtxn2 v0.4s, v1.2d252; CHECK-SD-NEXT: ret253;254; CHECK-FI-LABEL: test_vcvtx_high_f32_f64:255; CHECK-FI: // %bb.0:256; CHECK-FI-NEXT: fmov d2, d0257; CHECK-FI-NEXT: // implicit-def: $q0258; CHECK-FI-NEXT: fmov d0, d2259; CHECK-FI-NEXT: fcvtxn2 v0.4s, v1.2d260; CHECK-FI-NEXT: ret261;262; CHECK-GI-LABEL: test_vcvtx_high_f32_f64:263; CHECK-GI: // %bb.0:264; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0265; CHECK-GI-NEXT: fcvtxn2 v0.4s, v1.2d266; CHECK-GI-NEXT: ret267 %vcvtx2.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind268 %res = shufflevector <2 x float> %x, <2 x float> %vcvtx2.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>269 ret <4 x float> %res270}271 272define i16 @to_half(float %in) {273; CHECK-SD-LABEL: to_half:274; CHECK-SD: // %bb.0:275; CHECK-SD-NEXT: fcvt h0, s0276; CHECK-SD-NEXT: fmov w0, s0277; CHECK-SD-NEXT: ret278;279; CHECK-FI-LABEL: to_half:280; CHECK-FI: // %bb.0:281; CHECK-FI-NEXT: fcvt h1, s0282; CHECK-FI-NEXT: // implicit-def: $w0283; CHECK-FI-NEXT: fmov s0, w0284; CHECK-FI-NEXT: fmov s0, s1285; CHECK-FI-NEXT: fmov w0, s0286; CHECK-FI-NEXT: // kill: def $w1 killed $w0287; CHECK-FI-NEXT: ret288;289; CHECK-GI-LABEL: to_half:290; CHECK-GI: // %bb.0:291; CHECK-GI-NEXT: fcvt h0, s0292; CHECK-GI-NEXT: fmov w0, s0293; CHECK-GI-NEXT: ret294 %res = call i16 @llvm.convert.to.fp16.f32(float %in)295 ret i16 %res296}297 298define float @from_half(i16 %in) {299; CHECK-SD-LABEL: from_half:300; CHECK-SD: // %bb.0:301; CHECK-SD-NEXT: fmov s0, w0302; CHECK-SD-NEXT: fcvt s0, h0303; CHECK-SD-NEXT: ret304;305; CHECK-FI-LABEL: from_half:306; CHECK-FI: // %bb.0:307; CHECK-FI-NEXT: fmov s0, w0308; CHECK-FI-NEXT: // kill: def $h0 killed $h0 killed $s0309; CHECK-FI-NEXT: fcvt s0, h0310; CHECK-FI-NEXT: ret311;312; CHECK-GI-LABEL: from_half:313; CHECK-GI: // %bb.0:314; CHECK-GI-NEXT: fmov s0, w0315; CHECK-GI-NEXT: fcvt s0, h0316; CHECK-GI-NEXT: ret317 %res = call float @llvm.convert.from.fp16.f32(i16 %in)318 ret float %res319}320