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1; RUN: llc < %s -mtriple=arm64-apple-ios3.0.0 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s2; ModuleID = 'arm64_vecCmpBr.c'3target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"4 5 6define i32 @anyZero64(<4 x i16> %a) #0 {7; CHECK: _anyZero64:8; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v09; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]10; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]11; CHECK: [[LABEL]]:12; CHECK-NEXT: b _bar13entry:14 %0 = bitcast <4 x i16> %a to <8 x i8>15 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #316 %1 = trunc i32 %vminv.i to i817 %tobool = icmp eq i8 %1, 018 br i1 %tobool, label %if.then, label %return19 20if.then: ; preds = %entry21 %call1 = tail call i32 @bar() #422 br label %return23 24return: ; preds = %entry, %if.then25 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]26 ret i32 %retval.027}28 29declare i32 @bar(...) #130 31define i32 @anyZero128(<8 x i16> %a) #0 {32; CHECK: _anyZero128:33; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v034; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]35; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]36; CHECK: [[LABEL]]:37; CHECK-NEXT: b _bar38 39entry:40 %0 = bitcast <8 x i16> %a to <16 x i8>41 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #342 %1 = trunc i32 %vminv.i to i843 %tobool = icmp eq i8 %1, 044 br i1 %tobool, label %if.then, label %return45 46if.then: ; preds = %entry47 %call1 = tail call i32 @bar() #448 br label %return49 50return: ; preds = %entry, %if.then51 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]52 ret i32 %retval.053}54 55define i32 @anyNonZero64(<4 x i16> %a) #0 {56; CHECK: _anyNonZero64:57; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v058; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]59; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]60; CHECK: [[LABEL]]:61; CHECK-NEXT: mov w0, #062 63entry:64 %0 = bitcast <4 x i16> %a to <8 x i8>65 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #366 %1 = trunc i32 %vmaxv.i to i867 %tobool = icmp eq i8 %1, 068 br i1 %tobool, label %return, label %if.then69 70if.then: ; preds = %entry71 %call1 = tail call i32 @bar() #472 br label %return73 74return: ; preds = %entry, %if.then75 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]76 ret i32 %retval.077}78 79define i32 @anyNonZero128(<8 x i16> %a) #0 {80; CHECK: _anyNonZero128:81; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v082; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]83; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]84; CHECK: [[LABEL]]:85; CHECK-NEXT: mov w0, #086entry:87 %0 = bitcast <8 x i16> %a to <16 x i8>88 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #389 %1 = trunc i32 %vmaxv.i to i890 %tobool = icmp eq i8 %1, 091 br i1 %tobool, label %return, label %if.then92 93if.then: ; preds = %entry94 %call1 = tail call i32 @bar() #495 br label %return96 97return: ; preds = %entry, %if.then98 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]99 ret i32 %retval.0100}101 102define i32 @allZero64(<4 x i16> %a) #0 {103; CHECK: _allZero64:104; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0105; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]106; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]107; CHECK: [[LABEL]]:108; CHECK-NEXT: b _bar109entry:110 %0 = bitcast <4 x i16> %a to <8 x i8>111 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3112 %1 = trunc i32 %vmaxv.i to i8113 %tobool = icmp eq i8 %1, 0114 br i1 %tobool, label %if.then, label %return115 116if.then: ; preds = %entry117 %call1 = tail call i32 @bar() #4118 br label %return119 120return: ; preds = %entry, %if.then121 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]122 ret i32 %retval.0123}124 125define i32 @allZero128(<8 x i16> %a) #0 {126; CHECK: _allZero128:127; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0128; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]129; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]130; CHECK: [[LABEL]]:131; CHECK-NEXT: b _bar132entry:133 %0 = bitcast <8 x i16> %a to <16 x i8>134 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3135 %1 = trunc i32 %vmaxv.i to i8136 %tobool = icmp eq i8 %1, 0137 br i1 %tobool, label %if.then, label %return138 139if.then: ; preds = %entry140 %call1 = tail call i32 @bar() #4141 br label %return142 143return: ; preds = %entry, %if.then144 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]145 ret i32 %retval.0146}147 148define i32 @allNonZero64(<4 x i16> %a) #0 {149; CHECK: _allNonZero64:150; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0151; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]152; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]153; CHECK: [[LABEL]]:154; CHECK-NEXT: mov w0, #0155entry:156 %0 = bitcast <4 x i16> %a to <8 x i8>157 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3158 %1 = trunc i32 %vminv.i to i8159 %tobool = icmp eq i8 %1, 0160 br i1 %tobool, label %return, label %if.then161 162if.then: ; preds = %entry163 %call1 = tail call i32 @bar() #4164 br label %return165 166return: ; preds = %entry, %if.then167 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]168 ret i32 %retval.0169}170 171define i32 @allNonZero128(<8 x i16> %a) #0 {172; CHECK: _allNonZero128:173; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0174; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]175; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]176; CHECK: [[LABEL]]:177; CHECK-NEXT: mov w0, #0178entry:179 %0 = bitcast <8 x i16> %a to <16 x i8>180 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3181 %1 = trunc i32 %vminv.i to i8182 %tobool = icmp eq i8 %1, 0183 br i1 %tobool, label %return, label %if.then184 185if.then: ; preds = %entry186 %call1 = tail call i32 @bar() #4187 br label %return188 189return: ; preds = %entry, %if.then190 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]191 ret i32 %retval.0192}193 194declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2195 196declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2197 198declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2199 200declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2201 202attributes #0 = { nounwind ssp "target-cpu"="cyclone" }203attributes #1 = { "target-cpu"="cyclone" }204attributes #2 = { nounwind readnone }205attributes #3 = { nounwind }206attributes #4 = { nobuiltin nounwind }207