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1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s2 3define <16 x i8> @foov16i8(<8 x i16> %a0, <8 x i16> %b0) nounwind readnone ssp {4; CHECK-LABEL: foov16i8:5 %vshrn_low_shift = lshr <8 x i16> %a0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>6 %vshrn_low = trunc <8 x i16> %vshrn_low_shift to <8 x i8>7 %vshrn_high_shift = lshr <8 x i16> %b0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>8 %vshrn_high = trunc <8 x i16> %vshrn_high_shift to <8 x i8>9; CHECK: shrn.8b v0, v0, #510; CHECK-NEXT: shrn2.16b v0, v1, #511; CHECK-NEXT: ret12 %1 = bitcast <8 x i8> %vshrn_low to <1 x i64>13 %2 = bitcast <8 x i8> %vshrn_high to <1 x i64>14 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>15 %3 = bitcast <2 x i64> %shuffle.i to <16 x i8>16 ret <16 x i8> %317}18 19define <8 x i16> @foov8i16(<4 x i32> %a0, <4 x i32> %b0) nounwind readnone ssp {20; CHECK-LABEL: foov8i16:21 %vshrn_low_shift = lshr <4 x i32> %a0, <i32 5, i32 5, i32 5, i32 5>22 %vshrn_low = trunc <4 x i32> %vshrn_low_shift to <4 x i16>23 %vshrn_high_shift = lshr <4 x i32> %b0, <i32 5, i32 5, i32 5, i32 5>24 %vshrn_high = trunc <4 x i32> %vshrn_high_shift to <4 x i16>25; CHECK: shrn.4h v0, v0, #526; CHECK-NEXT: shrn2.8h v0, v1, #527; CHECK-NEXT: ret28 %1 = bitcast <4 x i16> %vshrn_low to <1 x i64>29 %2 = bitcast <4 x i16> %vshrn_high to <1 x i64>30 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>31 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>32 ret <8 x i16> %333}34 35define <4 x i32> @foov4i32(<2 x i64> %a0, <2 x i64> %b0) nounwind readnone ssp {36; CHECK-LABEL: foov4i32:37 %vshrn_low_shift = lshr <2 x i64> %a0, <i64 5, i64 5>38 %vshrn_low = trunc <2 x i64> %vshrn_low_shift to <2 x i32>39 %vshrn_high_shift = lshr <2 x i64> %b0, <i64 5, i64 5>40 %vshrn_high = trunc <2 x i64> %vshrn_high_shift to <2 x i32>41; CHECK: shrn.2s v0, v0, #542; CHECK-NEXT: shrn2.4s v0, v1, #543; CHECK-NEXT: ret44 %1 = bitcast <2 x i32> %vshrn_low to <1 x i64>45 %2 = bitcast <2 x i32> %vshrn_high to <1 x i64>46 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>47 %3 = bitcast <2 x i64> %shuffle.i to <4 x i32>48 ret <4 x i32> %349}50 51define <8 x i16> @bar(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {52; CHECK-LABEL: bar:53 %vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind54 %vaddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind55; CHECK: addhn.4h v0, v0, v156; CHECK-NEXT: addhn2.8h v0, v2, v357; CHECK-NEXT: ret58 %1 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>59 %2 = bitcast <4 x i16> %vaddhn2.i10 to <1 x i64>60 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>61 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>62 ret <8 x i16> %363}64 65define <8 x i16> @baz(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {66; CHECK-LABEL: baz:67 %vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind68 %vshrn_high_shift = ashr <4 x i32> %b0, <i32 5, i32 5, i32 5, i32 5>69 %vshrn_high = trunc <4 x i32> %vshrn_high_shift to <4 x i16>70; CHECK: addhn.4h v0, v0, v171; CHECK-NEXT: shrn2.8h v0, v2, #572; CHECK-NEXT: ret73 %1 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>74 %2 = bitcast <4 x i16> %vshrn_high to <1 x i64>75 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>76 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>77 ret <8 x i16> %378}79 80define <8 x i16> @raddhn(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {81; CHECK-LABEL: raddhn:82entry:83; CHECK: raddhn.4h v0, v0, v184; CHECK-NEXT: raddhn2.8h v0, v2, v385; CHECK-NEXT: ret86 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind87 %vraddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind88 %0 = bitcast <4 x i16> %vraddhn2.i to <1 x i64>89 %1 = bitcast <4 x i16> %vraddhn2.i10 to <1 x i64>90 %shuffle.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>91 %2 = bitcast <2 x i64> %shuffle.i to <8 x i16>92 ret <8 x i16> %293}94 95define <8 x i16> @vrshrn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind readnone ssp {96; CHECK-LABEL: vrshrn:97; CHECK: rshrn.8b v0, v0, #598; CHECK-NEXT: rshrn2.16b v0, v2, #699; CHECK-NEXT: ret100 %vrshrn_n1 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %a0, i32 5)101 %vrshrn_n4 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %b0, i32 6)102 %1 = bitcast <8 x i8> %vrshrn_n1 to <1 x i64>103 %2 = bitcast <8 x i8> %vrshrn_n4 to <1 x i64>104 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>105 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>106 ret <8 x i16> %3107}108 109define <8 x i16> @vrsubhn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind readnone ssp {110; CHECK-LABEL: vrsubhn:111; CHECK: rsubhn.8b v0, v0, v1112; CHECK: rsubhn2.16b v0, v2, v3113; CHECK-NEXT: ret114 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) nounwind115 %vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) nounwind116 %1 = bitcast <8 x i8> %vrsubhn2.i to <1 x i64>117 %2 = bitcast <8 x i8> %vrsubhn2.i10 to <1 x i64>118 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>119 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>120 ret <8 x i16> %3121}122 123define <8 x i16> @noOpt1(<2 x i32> %a0, <2 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {124; CHECK-LABEL: noOpt1:125 %vqsub2.i = tail call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %a0, <2 x i32> %a1) nounwind126 %vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind127; CHECK: sqsub.2s v0, v0, v1128; CHECK-NEXT: addhn2.8h v0, v2, v3129 %1 = bitcast <2 x i32> %vqsub2.i to <1 x i64>130 %2 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>131 %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>132 %3 = bitcast <2 x i64> %shuffle.i to <8 x i16>133 ret <8 x i16> %3134}135 136declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone137 138declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone139declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone140declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone141declare <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone142declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone143declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone144declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone145 146