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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s3 4define <8 x i8> @v_orrimm(ptr %A) nounwind {5; CHECK-LABEL: v_orrimm:6; CHECK: // %bb.0:7; CHECK-NEXT: ldr d0, [x0]8; CHECK-NEXT: orr.2s v0, #1, lsl #249; CHECK-NEXT: ret10 %tmp1 = load <8 x i8>, ptr %A11 %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>12 ret <8 x i8> %tmp313}14 15define <16 x i8> @v_orrimmQ(ptr %A) nounwind {16; CHECK-LABEL: v_orrimmQ:17; CHECK: // %bb.0:18; CHECK-NEXT: ldr q0, [x0]19; CHECK-NEXT: orr.4s v0, #1, lsl #2420; CHECK-NEXT: ret21 %tmp1 = load <16 x i8>, ptr %A22 %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>23 ret <16 x i8> %tmp324}25 26define <8 x i8> @v_bicimm(ptr %A) nounwind {27; CHECK-LABEL: v_bicimm:28; CHECK: // %bb.0:29; CHECK-NEXT: ldr d0, [x0]30; CHECK-NEXT: bic.2s v0, #255, lsl #2431; CHECK-NEXT: ret32 %tmp1 = load <8 x i8>, ptr %A33 %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >34 ret <8 x i8> %tmp335}36 37define <16 x i8> @v_bicimmQ(ptr %A) nounwind {38; CHECK-LABEL: v_bicimmQ:39; CHECK: // %bb.0:40; CHECK-NEXT: ldr q0, [x0]41; CHECK-NEXT: bic.4s v0, #255, lsl #2442; CHECK-NEXT: ret43 %tmp1 = load <16 x i8>, ptr %A44 %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >45 ret <16 x i8> %tmp346}47 48define <2 x double> @foo(<2 x double> %bar) nounwind {49; CHECK-LABEL: foo:50; CHECK: // %bb.0:51; CHECK-NEXT: fmov.2d v1, #1.0000000052; CHECK-NEXT: fadd.2d v0, v0, v153; CHECK-NEXT: ret54 %add = fadd <2 x double> %bar, <double 1.0, double 1.0>55 ret <2 x double> %add56}57 58define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {59; CHECK-LABEL: movi_4s_imm_t1:60; CHECK: // %bb.0: // %entry61; CHECK-NEXT: movi.4s v0, #7562; CHECK-NEXT: ret63entry:64 ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>65}66 67define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {68; CHECK-LABEL: movi_4s_imm_t2:69; CHECK: // %bb.0: // %entry70; CHECK-NEXT: movi.4s v0, #75, lsl #871; CHECK-NEXT: ret72entry:73 ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>74}75 76define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {77; CHECK-LABEL: movi_4s_imm_t3:78; CHECK: // %bb.0: // %entry79; CHECK-NEXT: movi.4s v0, #75, lsl #1680; CHECK-NEXT: ret81entry:82 ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>83}84 85define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {86; CHECK-LABEL: movi_4s_imm_t4:87; CHECK: // %bb.0: // %entry88; CHECK-NEXT: movi.4s v0, #75, lsl #2489; CHECK-NEXT: ret90entry:91 ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>92}93 94define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {95; CHECK-LABEL: movi_8h_imm_t5:96; CHECK: // %bb.0: // %entry97; CHECK-NEXT: movi.8h v0, #7598; CHECK-NEXT: ret99entry:100 ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>101}102 103; rdar://11989841104define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {105; CHECK-LABEL: movi_8h_imm_t6:106; CHECK: // %bb.0: // %entry107; CHECK-NEXT: movi.8h v0, #75, lsl #8108; CHECK-NEXT: ret109entry:110 ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>111}112 113define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {114; CHECK-LABEL: movi_4s_imm_t7:115; CHECK: // %bb.0: // %entry116; CHECK-NEXT: movi.4s v0, #75, msl #8117; CHECK-NEXT: ret118entry:119 ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>120}121 122define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {123; CHECK-LABEL: movi_4s_imm_t8:124; CHECK: // %bb.0: // %entry125; CHECK-NEXT: movi.4s v0, #75, msl #16126; CHECK-NEXT: ret127entry:128 ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>129}130 131define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {132; CHECK-LABEL: movi_16b_imm_t9:133; CHECK: // %bb.0: // %entry134; CHECK-NEXT: movi.16b v0, #75135; CHECK-NEXT: ret136entry:137 ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>138}139 140define <2 x i64> @movi_2d_imm_t10() nounwind readnone ssp {141; CHECK-LABEL: movi_2d_imm_t10:142; CHECK: // %bb.0: // %entry143; CHECK-NEXT: movi.2d v0, #0xff00ff00ff00ff144; CHECK-NEXT: ret145entry:146 ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>147}148 149define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp {150; CHECK-LABEL: movi_4s_imm_t11:151; CHECK: // %bb.0: // %entry152; CHECK-NEXT: fmov.4s v0, #-0.32812500153; CHECK-NEXT: ret154entry:155 ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>156}157 158define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp {159; CHECK-LABEL: movi_2d_imm_t12:160; CHECK: // %bb.0: // %entry161; CHECK-NEXT: fmov.2d v0, #-0.17187500162; CHECK-NEXT: ret163entry:164 ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>165}166